Systolic Architecture of Adaptive Post Detection Integration CFAR Processor in Binomial Distribution Pulse Jamming* Ivan Garvanov and Christo Kabakchiev Institute of Information Technologies, Bulgarian Academy of Sciences “Acad. G. Bonchev” Str., bl. 2, 1113 Sofia, Bulgaria e-mail:
[email protected];
[email protected] Plamen Daskalov “Multiprocessor Systems” Ltd., 63 Shipchensky prohod Blvd., 1574 Sofia, Bulgaria e-mail:
[email protected]
Abstract. A new parallel algorithm for signal processing and a parallel systolic architecture of a CFAR processor with adaptive censoring and post detection integration (API) are presented in the paper. The processor proposed is used for target detection when echoes from targets are performed in conditions of binomial distribution pulse jamming. The property of the algorithm proposed is its ability automatically to determine and censor the unwanted samples corrupted by pulse jamming in both, the two-dimensional reference window and the test cell, before noise level estimation. In case of binomial distribution pulse jamming for big repetition frequency, the censoring capabilities of the algorithm offered from Behar is small and the probability of false alarm is not constant. We offer the vector at the output of the reference window to be sorted and censored again. In such a way the influence of pulse jamming environment over adaptive threshold is reduced to minimum. The systolic architecture of the API CFAR is designed. Computational losses of the systolic architecture are estimated as a number of processor elements and computational steps needed for real-time implementation.
1 Introduction Target detection is declared if the signal value exceeds the threshold. Conventional cell averaging constant false alarm rate (CA CFAR) detectors are proposed by Finn and Johnson in [1]. The presence of strong binomial distributed pulse jamming in both, the test resolution cells and the reference cells, can cause drastic degradation in the performance of a CA CFAR processor. In many practical situations, however, the environment is characterized by the presence of strong pulse jamming (PJ) with high intensity and binomial distribution. We assume that the noise in the test cell is Rayleigh envelope distributed and the target returns are fluctuating according to Swerling II model. There are a lot of methods for increasing the efficiency of CFAR processors in case of non-stationary interference. One of these methods is the use of ordered statistics for estimating the interference level in the reference window, suggested by Rohling [2], Rickard and Dillard [3]. Another approach for estimating the *
This work is supported by IIT – 010044, MPS Ltd. Grant “RDR”, Bulgarian NF “SR” Grant ¹7 I – 902/99 and Ministry of Defense Grant ¹7 20.
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interference level, proposed by Himonas and Barkat in [4], is used in this paper. Later Himonas suggested in [5] this method to be used for removing of randomly arriving interference impulses from the test cell, when the reference window contains no impulse interference. Behar, Kabakchiev and Doukovska in [6] offered an adaptive censoring PI CFAR detector in the presence of pulse jamming and offered systolic architecture of this detector. When the probability for the appearance of pulse jamming is high, and the sizes of the reference and the test windows are small, the censoring algorithm in [6] is unsatisfactory. In this paper we propose new modification of the parallel algorithm from [6]. After additional censoring, the estimate in the reference window of the parallel algorithm is similar to that of the optimal algorithm. In such a way the influence of pulse jamming environment over adaptive threshold is reduced to minimum. That leads to increasing of the probability of detection. The possibility for parallel processing of the samples in the reference window is used in the obtained parallel computing architecture of the target detection algorithm. Radar signal processing is performed by images (bit matrices) in real-time. It is known that the two-dimensional window is sliding over an image, passing the distance cells one by one. It is also known that systolic architectures are very appropriate for real-time implementation in signal processing. For the design of a systolic architecture we have used the “superposition” approach according to which the known systolic architectures are used for each of the algorithm nodes. The designed parallel systolic architecture is suitable for conventional multiprocessor realization. 2 Signal Model Let us assume that L pulses hit the target, which is modeled according to Swerling II case. The received signal is sampled in range by using (M+1) resolution cells resulting in a matrix with (M+1) rows and (L) columns. Each column of the data matrix consists of the values of the signal obtained for (L) pulse intervals in one range resolution cell. Let us also assume that the first (M/2) and the last (M/2) rows of the data matrix are used as a reference window in order to estimate the “noiseplus-interference” level in the test resolution cell of the radar. In this case the samples of the reference cells result in a matrix X of the size (MxL). The test cell or the radar target image includes the elements of the (M/2+1) row of the data matrix and is a vector Z of the length (L). In conditions of binomial distribution of pulse jamming [7], the background environment includes the interference-plus-noise situation, which may appear at the output of the receiver with the probability 2ε( 1 −ε), the interference-plus-noise situation with the probability ε 2 and the noise only situation with the probability (1 − ε)2 , where ε = 1 − 1 − tc F , F is the average repetition frequency of PJ and tc is the length of pulse transmission. The distribution is binomial when the probability of PJ is above 0.2 as is given in [10]. The elements of the reference window are independent random variables with the compound exponential distribution law:
2
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(1 − ε)2 exp− x 2ε( 1 − ε) i + exp
− xi + λ λ ( 1+ r ) 0 0 1 + r j ) λ0 ( j − xi ε2 , + exp i = 1,...N ( ) λ0 ( 1 + 2r j ) λ 1 + 2 r 0 j f (xi )=
λ0
(1)
where N=ML and λo is the average power of the receiver noise, rj / λo is the average per pulse value of the interference-to-noise ratio (INR) at the receiver input. In the presence of a desired signal from a target the elements of the test resolution cell are independent random variables with the following distribution law: f( z j )= +
(1 − ε)2 exp − z j + 2ε(1 − ε) exp − z j + λ ( λ0 ( λ0 ( 1 + s) λ ( 1 + s ) 1 + r + s ) 1 + r + s ) 0 0 j j
−zj ε2 , exp λ0 ( 1 + 2r j + s ) λ ( 1 + 2 r + s ) j 0
(2)
j = 1,...L
where s is the average per pulse value of the “signal-to-noise” ratio (SNR) at the receiver input. 3 Analysis of API CFAR Processor The censoring algorithm consists of the following stages: The elements of the reference window x = (x1 , x2 ... x N )and the test resolution
cell z = ( z1 , z2 ... z L )are rank-ordered according to increasing magnitude.
1 (3) x1() ≤ x2(1)... ≤ xi(1)... ≤ x (N1) and z1(1) ≤ z2(1)... ≤ z (j1)... ≤ z (L1) Each of the so ranked elements is compared to the adaptive threshold, according to the following rule: (4) xi(+1)1 ≥ six Ti x , i = 1,..., N − 1 and z (j1+)1 ≥ s zj Tjz , j = 1,..., L − 1
where six =
i
∑x l =1
(1) l
and s zj =
j
∑ z( ) . The scale factors Ti x 1
l =1
l
z
and Tj are determined
in accordance with the given level of probability of false censoring ( Pfcen ), as in [4]: α N L 1 1 and P cen = Pfcen α = fα i 1 + Ti x (N − i )i j 1 + T z (L − j )j
[
]
[
j
]
(5)
The recursive procedure is stopped when the condition (4) becomes true. In this way the samples of the reference window and the test resolution cell are divided into two parts. The first part contains the “clean” elements, i.e. without pulse jamming. All these elements can be used for calculating the estimate V and the summed signal q0. k l (6) 1 1 and q = z () V = x () *
∑
n =1
*
n
0
∑
n =1
n
After the stop of the recursive procedure, it is assumed that most or all of the random impulses of pulse jamming are in the second part of the reference window and the test resolution cell. In this case the probability of target detection in the presence of binomial distribution pulse jamming may be calculated as in [6], using the following expression:
3
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i k N L l −1 k + i −1 Tα ( 1 + s) PD () s = ∑ p k ∑ pl ∑ k +i i ( k =1 l =1 i =0 Tα + s +1)
(7)
where pk and pl are the probability that “k” elements from the reference window and “l” elements from the test window contain only the receiver noise before 2 censoring. The probability for absence of pulse jamming in the element is ( 1 − ε). The expressions for the probabilities pk and pl are:
(
N 2k 2 pk = 1 − ε) 1 − ( 1 − ε) k (
)
N −k
L 2l 2 L −l and p = 1 − ε) ( 1−( 1 − ε) ) l ( l
(8)
The probability of false alarm is evaluated by (7), setting s = 0 . When we use a parallel algorithm with small sizes of the reference and the test windows, the achieved estimates of the environment in the API CFAR processor are not correct. In this paper we propose new modification of the parallel algorithm from [6]. It works successfully in the presence of binomial distribution pulse jamming. We have offered to form a vector, which includes clean elements after censoring in the reference window. This vector must be sorted and censored again, because in some of the channels of this vector of the parallel algorithm the censoring is not good, especially when the repetition frequency of pulse jamming is high. In this case the estimate in the reference window in the new parallel algorithm is similar to that of the optimal algorithm presented in [6]. 4 Numerical results We study in this paper the censoring capabilities of an API CFAR detector in strong binomial pulse jamming. The average power of the receiver noise is λ0 = 1 . The results for the probability of censoring are received by using Monte-Carlo simulation. The probability of censoring of the offered new algorithm, for probability of false censoring from 10-6 to 10-3, is presented on Fig.1. The probability for the appearance of pulse jamming is 0.6 and the size of the reference window is M=16 and L=16. The unwanted samples are censored more efficiently as the probability of false censoring increases, because the adaptive threshold in each step of the censoring process decreases. The censoring capabilities of the suggested parallel algorithm in [6] and the new parallel algorithm, only for the reference window, are presented on Fig.2. The experimental results are obtained for the following parameters: size of the reference window M=16, L=16, 32, 64, probability of false censoring Pfc=10-3, probability for the appearance of pulse jamming ε =0.8. When the size of the reference window increases, the probability of censoring also increases. When we use additional censoring, the estimate in the reference window is similar to the estimate of the optimal algorithm considered in [6].
4
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Fig. 1 Probability of censoring for Pfc from 10-6 to 10-3
Fig. 2 Probability of censoring of new and old algorithm (M=16, L=16, 32, 64)
The censoring capabilities in the test window with size L=16, 32, 64, 128, 256, are presented on Fig.3. The probability for the appearance of pulse jamming in the elements is 0.8. As expected, the probability of censoring increases when the size of the reference window increases. Censoring improves when the difference between the signal power and the interference power increases (over 3-5dB).
Fig. 3 Probability of censoring in the test window for SNR=20dB
Fig. 4 Probability of censoring in the test window for SNR=10, 20, 30dB
The probability of censoring in the reference window with a size L=64 is presented on Fig.4. The probability for the appearance of pulse jamming is 0.3 and 0.8, for different values of the interference to noise ratio. Also, as the probability for the appearance of pulse jamming in the elements increases the probability of censoring in these samples for a given INR decreases (over 3-5dB). 5 Parallel Architecture of an API CFAR Processor The systolic parallel architecture of a CA CFAR processor with adaptive censoring and non-coherent integration is presented on Fig.5, and it is similar to the one presented in [6]. The computational blocks for sorting and censoring of the vectors are denoted as Sl and Cl , where l = 1...L + 2 .
5
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Fig. 5 Systolic architecture of a CA CFAR processor with adaptive censoring and non-coherent integration
The suggested on Fig.5 parallel systolic architecture is also suitable for multiprocessor realization. The systolic architectures of the sorting and censoring computational blocks are shown on Fig.6 and Fig.7. The logical operation of the processor elements is shown on Fig. 8. x1,1 x1,2 x1,3 x1,4
PE1 PE1
.... x1,M-1 x1,M PE1
PE2 PE1 PE1
PE1
PE2
PE1
PE1 PE1
PE1
....
.... PE1
....
PE1
PE2 PE1
.... ....
x1,1 (1) x1,2 (1) (1) x1,3 (1) x1,4
.... (1)
PE1
PE1
PE2
x1,M-1 x1,M (1)
Fig. 6 Systolic architecture of the sorting algorithm
The systolic architecture of the sorting block is realized in accordance with the well-known “Odd - Even Transposition Sort” method. This method is used in the systolic architecture of adaptive MTD processors described in [8]. The analysis of the architecture shows that four types of processor elements are needed for the realization of an API CFAR processor: PE1, PE2, PE3 and PE4. T1 T2 TM-1 1 1
S
1,k*
Fig. 7 Systolic structure of the censoring algorithm
6
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in 1 in 2
in
x2in in x1 x in x1
in 2
x
PE3
x
Out
x
Out
x3in PE4
out 2
in 1
} ,x } in 2
x out = x in
Out
x3in
{ = max{ x
x 1out = min x 1in , x 2in
Out 1 Out 2
x in + x in , if x in ≤ x in x in x out = 2 in 3 in 3 in 2in 1 x 2 , if x 3 > x 2 x 1 1, if x 3in ≥ x 1in x 2in x out = in in in 0, if x 3 < x 1 x 2
Fig. 8 Processor elements PE1, PE2, PE3 and PE4, and their logical operation
6. Estimation of the Systolic Architecture Parameters We use the following basic measures to evaluate the systolic architecture parameters: the number of processing elements, the number of computational steps and the speed-up of the computational process. The computational measures of the processor, calculated for each stage of signal processing, are as follows: 1. Sorting of vectors: Number of elements PE1=[L(M-1)2+(L-1)2]/2; PE2=L(M-2)+(L-2)+D ; where D1=(M-L), if M ≥ L or D1=L(L-M), if M
