Techniques for Improving the Efficiency of Sequential Circuit Test ...

Techniques for Improving the Efficiency of Sequential Circuit Test Generation1 Xijiang Lin2 Mentor Graphics Corporation 8005 S.W. Boeckman Wilsonville, OR 97070-777

Irith Pomeranz Sudhakar M. Reddy Electrical and Computer Engineering Department University of Iowa Iowa City, IA 52242

Abstract

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New Techniques

In this section, we describe several techniques to improve the effectiveness of the deterministic test generation process. At the end of this section, we also give a technique to improve genetic optimization based test generation.

New techniques are presented in this paper to improve the efficiency of a test generation procedure for synchronous sequential circuits. These techniques aid the test generation procedure by reducing the search space, carrying out nonchronological backtracking, and reusing the test generation effort. They have been integrated into an existing sequential test generation system MIX to constitute a new system, named MIX-PLUS. The experimental results for the ISCAS89 and ADDENDUM-93 benchmark circuits demonstrate the effectiveness of these techniques in improving the fault coverage and test generation efficiency.

2.1 Dynamic J-frontier Reduction In deterministic test generation, two kinds of objectives are maintained. These are stored in the sets D-frontier and Jfrontier. The elements of the D-frontier are the gates to whose inputs an error value due to the target fault has propagated. The elements of the J-frontier are the line values to be justified. Since the indirect implication is used and the selection of next D-frontier element to be propagated is based on observability, it is possible that the J-frontier elements created before do not help to activate the fault site and/or propagate the D-frontier element targeted next. If such J-frontier elements are justified, the effort spent will be wasted. To make the search for the fault propagation sequence more efficient, the following technique is proposed to automatically reduce the J-frontier size. One D-frontier element with maximal observability is picked based on SCOAP testability analysis [16]. Then, a primary output poi at which the fault effect may be observed is selected. The J-frontier elements in the cone dominated by poi are given higher priority for justification than the J-frontier elements outside of the cone, since they may be more useful for aiding fault propagation. When no J-frontier element is located in the cone dominated by poi, the target D-frontier technique [4] is used to propagate the D-frontier element with the maximal observability before justifying the J-frontier elements outside the cone. If the fault effect is propagated to a primary output poi, we find the cone dominated by poi and then remove all the Jfrontier elements outside of this cone from the J-frontier list, as they will not help observe the fault effects at poi.

Introduction

The problem of test generation for logic circuits has been proven to be NP-complete. Extensive studies have been done to find efficient procedures to achieve complete or close-to-complete fault coverage, resulting in two main categories of test generation strategies, i.e., deterministic test generation [1]-[5] and simulation-based test generation [6][11]. In [12][13], these two strategies are combined to improve the fault coverage that can be achieved in practical time. The test generation system MIX [13] improved the fault coverage further by applying the restricted multiple observation time strategy [14]. In this paper, we propose several new techniques to improve the effectiveness of deterministic test generation procedures and one technique to improve the effectiveness of genetic optimization based procedures. The proposed techniques are integrated into the test generation system MIX [13] to build a new system called MIXPLUS. In the published literature, MIX reported the best fault coverage and fault efficiency for the ISCAS-89 and the ADDENDUM-93 benchmark circuits. The run time of MIX was also smaller than other test generators that obtained comparable fault coverages. The experimental results obtained by applying MIX-PLUS to the same benchmark circuits demonstrate the effectiveness of the proposed techniques in improving the fault coverage and test generation efficiency. This paper is organized as follows. Section 2 describes the proposed techniques. Experimental results are presented in Section 3. Section 4 concludes the paper.

2.2 Improved Fault Activation and Fault Effect Propagation In the fault activation and propagation phase of a deterministic test generation procedure that uses forward time processing for fault activation and propagation, the target fault is activated in the first time frame under the assumption that the present state lines of the first time frame for both the fault-free and the faulty circuits are fully controllable. Furthermore, since the fault is activated for the first time only in this time frame, none of the present state variable values of the first time frame in the fault-free and the faulty circuits carry differing binary values. Therefore, a signal line g in a

1. The work reported was supported in part by a research grant from NEC USA Inc., and by NSF Grant MIP-9725053. 2. The work was done while the author was a graduate student in the Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa.

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time frame i ≥ 1 must have the same logic value in the faultfree and the faulty circuits if g is unreachable from the fault site in any time frame 1 ≤ j ≤ i , i.e., the assignment of g = α , α ∈ { 0, 1 } , in the fault-free(faulty) circuit, implies g = α in the faulty(fault-free) circuit. We use this observation to increase the number of mandatory assignments during test generation. Increased mandatory assignments reduce the number of backtracks and hence help improve the run time.

2.4 Conflict Directed Search In deterministic test generation procedures, the branchand-bound strategy is generally used to search for a solution satisfying a given objective. When a conflict occurs, backtracking is done to a decision that has untried choices. In order to reduce the number of backtracks, the decision point backtracked to should be related to the conflict identified. Otherwise, additional backtracks will be required to resolve the conflict resulting in wasted effort. To reach the goal of backtracking to an affective decision point, we use conflict directed search inspired by the work in [17]. After assigning known values, i.e., logic 1 or 0, to a set of lines L in a logic circuit, the values of the lines in L may imply known values on another set of lines L’. For any line l in L’, the reason for fixing l to the known value is due to the values of a subset of lines in L. For example, after fixing all the inputs of an AND gate to logic 1, the reason for fixing the output of that gate to 1 is due to all its inputs. During test generation, all line values are initially unknown, and some of them become known as test generation progresses. After one line value becomes known, its value cannot be changed unless backtracking occurs. The reason for fixing a line to a known value is recorded in a directed graph, called the implication graph, defined next: Definition 1: An implication graph is a directed graph describing the logic value dependencies among the line values in a circuit. Each node in the implication graph corresponds to a line with a known value. The incoming edges of a node give the complete reason for fixing that node to a known value. As defined above, the implication graph is a directed graph that is dynamically maintained. Corresponding to each line in the ILA model of the circuit, which is currently assigned a known value (i.e., 0 or 1), there is a node in the implication graph. There is an edge (i, j) in the implication graph if the value on line j is implied by the value on line i. The implications may be direct or indirect as described below. • Direct Implication: Direct implications include two types of operations, simulation and justification.

2.3 Relaxing States to be Justified After a fault is activated in the first time frame and the fault effect is propagated to a primary output in a time frame i > 1 , the values of the present state variables of the first time frame have to be justified. Some of the state variable values may be over-specified(specified as 0 or 1 instead of being unspecified). Similar over-specification of states may occur in time frames prior to time frame 1 while attempting to justify the desired present state value of the first time frame. In HITEC [4], the over-specification of circuit states is reduced by changing, one at a time, the specified value of a present state variable to the unspecified value and checking to see if the desired objectives are still met. We propose a different approach to relax the over-specified state variables. The basic idea is similar to the one in [15], suggested to improve the run time of fault simulation. However, the procedure we use is different and helps relax a large number of overspecified state variables as well as relaxing the harder to control state variables. Furthermore, our goal here is to improve the run time for test generation. a=0

c

b=0

d e f

g=0

h=0

Fig. 1: Unnecessary assignment at b=0

The proposed method to relax state variables uses a two step process. In each step, line values are relaxed so as to preserve the output values and/or the next state variable values at an appropriate time frame as explained in the next paragraph. In the first step, the line values are relaxed by traversing the circuit from the primary outputs or next state lines to the primary inputs and/or the present state lines of the appropriate time frame of the ILA model. In this step, whenever a choice exists, the harder to control signal lines are relaxed with a higher priority. The controllability of signal lines is measured using the SCOAP[16] analysis. This step may not relax some over-specified values due to the order of choosing lines to be relaxed. In Figure 1, if we choose c to justify g=0 and choose e to justify h=0, neither a=0 nor b=0 will be relaxed. Obviously, only one of them is required. In the second step, the line values are relaxed by traversing the circuit from the primary inputs and/or present state lines of the appropriate time frame towards primary outputs or next state lines. In this step, we relax the values assigned at the present state lines without carrying out implications while retaining all specified values on the primary inputs. Implementation details can be found in [18]. During the fault activation and propagation phase of the test generator, the appropriate output of the ILA used in relaxing the state variables is the primary output to which the effect of the target fault has been propagated. During the state justification phase using reverse time processing, the appropriate outputs are the next state variables of a time frame of the ILA that need to be justified.

a=0 b

a c c

(a) An AND gate (b) Implication graph Fig. 2: Simulation

Simulation is an implication procedure from the inputs of a gate to its output. The reason for fixing the gate’s output to a known value is due to a subset of its inputs. In Figure 2, the assignment a=0 implies c=0. In the implication graph, an edge from node a to node c is added to indicate that it is line a that caused line c to become known. d=1 e

d

f

f=0 e

(a) An AND gate (b) Implication graph Fig. 3: Justification

Justification is an implication procedure from a gate output to its inputs. The reason for fixing one of the inputs of a gate to a known value is due to its output and a subset of its inputs. In Figure 3, setting f=0 after d=1 implies e=0. The reason for fixing e to 0 is due to the

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d = 0 → a = 0 as shown in Figure Figure 6(a). After the next decision b=0 is made, a conflict occurs and the nodes involved in the conflict are g, h, and k. For node g, the assignments b=0, d=0, j=1 imply g=1 and the assignments b=0, d=0, and k=0 imply g=0. Similar observation can be found for nodes h and k. Starting from node set {g, h, k} in the implication graph shown in Figure 7(a), the support set of the nodes involved in the conflict is {b, d, j, k}. Since b=0 is the latest decision point in the support set, signal b is changed to its alternate value 1 and new edges d → b and b → b are added into the implication graph to indicate that the reasons for changing b to value 1 are b and d. The modified implication graph after assigning b=1 is shown in Figure 7(b). This change causes another conflict and the latest decision in the support set of the nodes involved in the conflict is d. Therefore, backtracking to the decision node d instead of a occurs, as shown in Figure 7(b).

value assignments on lines d and f. Therefore, new edges from d to e and f to e are added in the implication graph. Indirect Implication: Some logic dependencies among the line values cannot be derived by direct implications. In Figure 4, the new assignment c=0 implies d=1 and e=1. This relation cannot be derived from direct implication. Static learning and dynamic learning [2] are two procedures to derive the indirect implications. The corresponding edges of the implication graph are shown in Figure 4(b). a b

c=0 c e d

(a) An example circuit

d

e

a

(b) Implication graph

e

i=0

Fig. 4: Indirect implication

The nodes in the implication graph can be classified into two types called fixed nodes and derived nodes defined below. Definition 2: A fixed node in an implication graph is a node without any incoming edge. Definition 3: A derived node in an implication graph is a node having at least one incoming edge. For any given line l with a known value, the subset of the fixed nodes that imply the value of l is referred to as the support set of l. Definition 4: The support set of a set of nodes V in an implication graph is a set of fixed nodes which have a path to some node in V. Nodes with disjoint support sets are independent, in the sense that one does not imply the value of the other. Note that fixing a signal to a known value may have several independent reasons. For example, when the logic value 0 is assigned to all the inputs of an AND gate, the reason for fixing its output to 0 can be any one of its inputs. When the implication graph is built, only one reason is used and the others are ignored. Hence, two signals that are structurally dependent may be classified as independent signals in the implication graph. 2.4.1 Applications of the Implication Graph We use the implication graph to achieve effective nonchronological backtracking and to dynamically identify invalid states. Next, we discuss the use of the implication graph to achieve effective non-chronological backtracking. Since all the line values corresponding to derived nodes in an implication graph are implied by the line values corresponding to the fixed nodes, it can be seen that the reason for a conflict is the line values corresponding to the union of the support sets of each node involved in the conflict. Definition 5: A node n in an implication graph is said to be involved in a conflict if logic values assigned to a set of nodes implies n to be 1 and logic values assigned to another set of nodes implies n to be 0 simultaneously in the corresponding circuit. To avoid the conflict, one of the nodes in the support set must have its value changed. If none of the nodes in the support set has a remaining choice to change their values, then the search being conducted has no solution. Consider the three objectives i=0, j=1 and k=0 shown in Figure 5. Assume that the initial decision tree is

b

f

c

j=1

d g k=0 h

Fig. 5: A circuit to illustrate non-chronological backtracking d 0 d 0

a Jump

0 a b

0 0

1

Conflict

(a) Initial decision tree (b) Decision tree after making decision at line b Fig. 6: Decision tree for the circuit shown in Figure 5 a

i

j

d e

b h

f

k

a

i e

b

k

h

f

c g

j

d

c g

Conflict

(a) Implication graph after assigning b=0

Conflict

(b) Implication graph after assigning b=1

Fig. 7: Implication graph for the circuit shown in Figure 5

The implication graph is also used to expand the cubes corresponding to the invalid states. This is done by recording the state variable lines in the support set of the nodes involved in a conflict. Details of this procedure are not given here. But we use the circuit shown in Figure 8 to describe how to expand the cube of an invalid state {def}={011}.

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Suppose that the first decision is c=0. It implies b=1 and then causes a conflict at signals b, c, f. The state variable set involved in this conflict is U1={e, f}. After trying the alternative value of c=1, another conflict occurs and its support set includes state variables U2={e, f}. Since there is no choice left, the target state is an invalid state and this state is expanded to be U 1 ∪ U 2 , i.e., {def}={X11}. a

b c

d=0

e=1

f=1

state(i.e., a state not visited earlier), else it is equal to 0. The position of the vector with the maximum fitness is used as the crossover point in the hope of improving the fitness of the individuals in the next generation.

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Experimental Results

The test generation system MIX-PLUS was implemented by integrating the proposed new techniques into the test generation system MIX and run on an HP 9000-780 workstation. It was applied to the ISCAS-89 and the ADDENDUM-93 benchmark circuits to assess the effectiveness of the proposed techniques. Table 1 shows the test generation results. For each circuit, the total number of collapsed faults is given under column FLT. The number of faults detected under the restricted multiple observation time strategy and the number of untestable faults are reported under columns DET and UNT, respectively. Column VEC shows the test sequence length, and column CPU shows the CPU time in seconds taken by the test generation process. Under column MIX, we show the same data for MIX. In parentheses under the column DET of MIX-PLUS, we also show the number of faults detected under the single observation time strategy when applying the generated test sequences. We point out that some faults that can be detected under the single observation time strategy are detected by MIX-PLUS under the restricted multiple observation time strategy. Once a fault is detected under the latter strategy, it will not be considered again under the conventional one. Compared with the test generation results of MIX, MIXPLUS detected more faults for 8 out of 32 circuits and identified more untestable faults for 16 out of 32 circuits. The run times of MIX-PLUS are considerably smaller than those of MIX for most of the circuits. In Table 1, we also show the test generation results of STRATEGATE [11], a GA-based test generator. As can be seen from the table, MIX-PLUS detects more faults than STRATEGATE for all circuits. The run times are not directly comparable since STRATEGATE results were obtained on a HP-J210 workstation. To assess the effects of simulating justification sequences for single flip-flops, the number of faults detected in this way is shown under the column JUST-DFF. It should be pointed out that not all the flip-flops were considered during the process of simulating the justification sequences for single flip-flops. Only the flip-flops which did not take the values 0 or 1 during the state-driven test generation, the first phase of MIX and MIX-PLUS were considered. In addition, only the faults not detected during this phase are considered. For some well known difficult to test circuits, a large number of faults are detected by the simulation of the (partial) justification sequences as shown in Table 1. For example, 28% of faults are detected in s1423 by simulating the justification sequences for single flip-flops.

FF

FF

FF

Fig. 8: A circuit to illustrate expanding a cube of an invalid state

Expanding invalid state cubes is a by-product of nonchronological backtracking. When test generation is in the state justification phase, we record the next state variables involved in the conflict at each justification time frame. As the backtracking process moves back to the previous time frame, the recorded next state variables in the current time frame represent an invalid state which should be avoided in the future search process. For a circuit with N nodes where a node may be adjacent to at most K other nodes, the space complexity of the implication graph is O(KN). In practice, smaller implication graphs are obtained since, typically, only a small number of implications occur that need to be recorded in the implication graph.

2.5 Simulation of the Justification Sequence for Single Flip-flops In MIX [13], a subset of the invalid states is identified by determining if some flip-flop states cannot be justified. For some flip-flops, this procedure finds a sequence to justify the desired state, or a partial sequence may be found before the procedure aborts. Since these sequences are available, they are passed to a fault simulator to determine if they detect any yet undetected faults. We found that for many circuits, these sequences detect several faults as will be shown in Section 3.

2.6 Crossover with a Static Crossover Point In genetic algorithms, crossover is one of the evolution operations to generate offspring from two parents by crossing the parents at a selected point. Assuming a single point crossover, the scheme for selecting the crossover point has great effect on the quality of the population in the next generation. Normally, the crossover point is selected randomly. We found that such a random choice for a crossover point often does not create good individuals in the context of test generation. To solve this problem, we propose the static crossover point described below. We measure the fitness of each vector Vi in an individual consisting of n vectors as follows: 0.6 × P 1 + 0.2 × P 2 fitness i = ------------------------------------------------ + 0.2 × P 3 # of faults simulated where, fitnessi is the fitness of vector Vi; P1 denotes the number of faults detected when Vi is applied; P 2 denotes the number of flip-flops carrying fault effects after Vi is simulated; P 3 is equal to 1 if the next state under Vi is a new

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Concluding Remarks

In this paper, we presented several new techniques to improve the test generation effectiveness for synchronous sequential circuits. These techniques improve the sequential test generation process in several ways. Dynamic J-frontier reduction and a two-step procedure for removing unnecessarily specified values of state variables help the test generation procedure concentrate on areas of the search space where solutions are likely to be. Identical values in the faultfree and the faulty circuits during the fault propagation phase of test generation help increase the number of mandatory assignments. As a result, the search space is reduced. Aided by the implication graph, non-chronological backtracking is realized to reduce the number of backtracks. With the impli-

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Table 1. Test Generation Results MIX-PLUS Circuits FLT DET UNT VEC s208 215 150(137) 65 101 s298 308 273(265) 34 204 s344 342 335(329) 7 96 s349 350 341(334) 9 125 s382 399 378(364) 15 1111 s386 384 314(314) 70 192 s400 424 395(382) 23 1413 s420 430 204(179) 226 115 s444 474 436(424) 29 1131 s510 564 564(0) 0 465 s526 555 463(453) 55 1726 s526n 553 465(452) 56 1453 s641 467 408(404) 59 131 s713 581 480(476) 101 120 s820 850 815(814) 35 741 s832 870 819(817) 51 684 s838 857 303(253) 554 109 s953 1079 1069(90) 10 594 s967 1066 1047(79) 19 465 s1196 1242 1239(1239) 3 299 s1238 1355 1283(1283) 72 319 s1269 1343 1339(240) 3 314 s1423 1515 1457(1405) 18 1673 s1488 1486 1446(1442) 40 665 s1494 1506 1455(1452) 51 585 s3271 3270 3253(3253) 7 1051 s3330 2870 2124(2124) 745 541 s3384 3380 3346(3323) 1 1010 s4863 4763 4638(4638) 126 489 s5378 4603 3659(3639) 907 1271 s35932 39094 35110(35100) 3984 255 prolog 3305 2325(2325) 977 865

CPU 0.66 4.77 0.68 1.12 321 1.13 405 1.49 540 7.38 1375 1324 2.23 1.99 9.18 7.97 3.91 17.2 28.9 4.05 5.3 53 2976 20.5 18.1 403 56.1 2301 19 2488 1401 143

MIX JUST-DFF DET UNT VEC CPU 0 150 65 128 3.1 0 273 26 206 30.1 7 335 5 76 6.4 7 341 7 104 4.2 15 375 4 834 493 0 314 70 226 11.1 21 396 12 1170 467 0 204 226 100 15.6 14 435 16 870 750 0 564 0 587 80 119 462 48 1545 1342 134 14 408 59 131 4.3 8 480 101 130 7.3 0 815 35 838 67 0 819 51 881 93 0 303 501 109 223 0 1069 6 563 327 0 1047 13 530 444 0 1239 3 306 14.5 0 1283 72 347 18.9 0 1339 3 341 49.5 422 1455 18 1658 3412 0 1446 40 918 184 0 1455 50 759 176 0 3246 0 1394 1870 0 2124 707 756 997 3 3334 15 1406 2059 0 4638 125 612 1190 389 3643 749 1766 7601 0 35109 3984 296 25248 0 2325 694 958 6250

cation graph, additional invalid states can be identified and hence the possibility of entering the invalid state space is reduced. Simulating (partial) justification sequences for single flip-flops often helps detect a large number of faults. Crossover with a static crossover point provides an effective way to select the crossover point during the evolution operation of the genetic algorithm. With the aid of the proposed techniques, the system MIX-PLUS improved both the fault coverage and fault efficiency while simultaneously reducing the run time compared to the original test generation system MIX. The results demonstrated the effectiveness of the proposed techniques.

STRATEGATE DET VEC CPU 265 306 329 85 364 1486 486 384 2424 424 1945 1206 454 2642 3270 404 166 476 176 80 814 590 218 818 701 1414 3943 4572 1444 593 1453 540 456 3639 11571 136080 35100 257 39240 -

216-219 [7] P. Prinetto, M. Rebaudengo, and M. S. Reorda, ‘‘An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithm’’, ITC, 1994, pp. 240-249. [8] E. M. Rudnick, J. G. Holm, D.G. Saab, and J. H. Patel, “Application of Simple Genetic Algorithms to Sequential Circuit Test Generation,” Proc. European Design Test Conference, 1994, pp. 40-45. [9] E. M. Rudnick, J. H. Patel, G. S. Greenstein and T. M. Niermann, “Sequential Circuit Test Generation in a Genetic Algorithm Framework,” Proc. DAC, June 1994, pp. 698-704. [10] I. Pomeranz and S. M. Reddy, “LOCSTEP: A Logic Simulation Based Test Generation Procedure,” 25th Fault-tolerant Computing Symp., pp. 110-119, June 1995. [11] M. S. Hsiao, E. M. Rudnick, and J. H. Patel, “Sequential Circuit Test Generation Using Dynamic State Traversal,” European Design and Test Conference, pp. 22-28, 1996. [12] E. M. Rudnick and J. H. Patel, “Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation,” Proc. 32rd Design Autom. Conf., June 1995, pp. 183-188. [13] X. Lin, I. Pomeranz and S. M. Reddy, “MIX: A Test Generation System for Synchronous Sequential circuits,” Proc. 11th Intl. Conf. on VLSI Design, pp. 456-463, January 1998. [14] I. Pomeranz and S. M. Reddy, “The Multiple Observation Time Test Strategy,” IEEE Tran. on Computer, pp. 627-637, May 1992. [15] S. B. Akers, B. Krishnamurthy, S. Park, and A. Swaminathan ‘‘Why is Less Information from Logic Simulation More Useful in Fault Simulation?,” Intl. Test Conf., pp. 786-800, 1990. [16] L. H. Goldstein and E. L. Thigpen, ‘‘SCOAP: Sandia Controllability/Observability Analysis Procedure,” Proc. 17th IEEE Design Automation Conf., pp. 190-196, 1980. [17] J. P. M. Silva and K. A. Sakallah, “GRASP — A new search algorithm for satisfiability,” ICCAD, pp. 220-227, 1996. [18] X. Lin, “Sequential Circuit Test Generation,” Ph.D. Thesis, University of Iowa, 1998.

Acknowledgments The first author, X. Lin, would like to thank Dr. Srimat Chakradhar and Mr. Kiran Doreswamy of NEC USA Inc. for valuable discussions on the use of the implication graph.

References [1] R. Marlett, ‘‘An Efficient Test Generation System for Sequential Circuits,’’ 23rd DAC, June 1986, pp.250-256. [2] M. Schulz and E. Auth, “ESSENTIAL: An Efficient SelfLearning Test Pattern Generation Algorithm For Sequential Circuits,” 1989 ITC, pp. 28-37. [3] W. Cheng and T. Chakraborty, “Gentest — An Automatic Test Generation System for Sequential Circuits,” IEEE Computer, pp. 43-49, April 1989. [4] T. Niermann and J. Patel, “HITEC: A Test Generation Package fo Sequential Circuits,” European Conf. on Design Automation 1991, pp. 214-218. [5] T. Kelsey, K. Saluja, and S. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Trans. on Computer, vol. 42, pp. 1361-1371, November 1993. [6] D. G. Saab, et. al., “CRIS: A Test Cultivation Program for Sequential VLSI Circuits,” Intl. Conf. on CAD, Nov. 1992, pp.

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