Abstract. Variation has an increasingly negative impact on key interconnect applications, including clock skew and signal line delay. Here we consider both ...
International Interconnect Technology Conference (IITC), June 2001, San Francisco, CA.
Technology Scaling Impact of Variation on Clock Skew and Interconnect Delay Vikas Mehrotra and Duane Boning Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge, MA 02139 Abstract Variation has an increasingly negative impact on key interconnect applications, including clock skew and signal line delay. Here we consider both random and systematic variation in interconnect and device parameters as technology scales from 180nm to 50nm. For the case considered, we show that (1) clock skew increases from about 15% to 30% of the clock cycle, and (2) modeling systematic variation sources enables tighter tolerance design that can substantially reduce this skew as well as reduce wire length limitations. I. Introduction As technology scales, shrinking interconnect pitch and increasing clock frequency and chip size put greater constraints on circuit design and technology. Additionally, variation in the interconnect and devices results in even tighter design requirements: a key issue is to understand how much variation exists in a given design and what its impact is on circuit performance. It is also important to differentiate between systematic variation sources versus those that are purely random. Systematic variation sources are often modeled as a function of the process and layout parameters, especially interconnect variation (e.g.[1]). Using deterministic variation models in circuit simulation can improve circuit performance in at least two ways. If the variation is greater than desired, post-design correction can be performed on the layout where possible. If the actual variation is less than the worst-case tolerance, design uncertainty can be reduced through better modeling. This allows for a more aggressive approach (referred to here as “tighter tolerance design”) and avoids unnecessary overdesign. Several previous works have addressed the issue of process variation and its impact on circuit performance. In [2], closed form models for sensitivity to different parameter variations are derived for a clock tree. In [3], the technology scaling impact on delay is studied including interconnect and device variations. However, both of these studies use worstcase approaches to determine the impact on skew and delay. In our previous work [4,5] a methodology is described to study the impact of systematic variation but random variation sources are not considered. In this paper, we propose an integrated variation analysis technique and consider for the first time the effects of both systematic and random variation in the interconnect and devices simultaneously to get a better perspective on the impact of variation as a whole. We illustrate the performance gain using our new method for two case studies: clock skew
in an H-tree and wire length variation in optimally buffered interconnect; these cases consider circuit and variation issues beyond those in [4,5]. II. Variation Modeling A. Clock Tree With copper interconnect and a metal chemicalmechanical polishing (CMP) process, the main source of interconnect thickness variation comes from planarization. Metal thickness variation is a strong function of local pattern density and metal linewidth and can be modeled using the procedure given in [1]. The inter-layer dielectric (ILD) variation is small with metal CMP, and metal linewidth variation has a smaller impact in clocks because of wider lines. In addition to interconnect variation, device variation must also be taken into account if intermediate buffers or repeaters are used to drive the clock signal (see Fig. 1). The important device variation parameters include Leff, Vt, tox. The variation in Leff (also referred to as poly CD or L-poly) has a systematic component as well as a random component. Several works have studied the CD variation in poly and metal lines (e.g. [6,7]). Although some of the variation can be corrected using optical proximity correction (OPC), significant discrepancies still exist between the measurements and models even after correction. For simulation purposes, we assume that half of the poly CD variation can be modeled (and corrected) using OPC and half of it is purely random. In addition to these device variation sources, we also study the effects of power supply (VDD) variation. We model this as a random variation source across the chip. Latch
IBM, 180nm, Cu Interconnect
Clock Driver Intermediate Buffers (Repeaters) Fig. 1: The clock tree used to simulate the effects of interconnect and device variation on skew. This H-tree consists of two intermediate buffer stages with balanced loads at the latches for each path, with a total of 996 paths. For clarity, the intermediate buffers and the latch are shown for only one path.
Output
Input
B. Optimally Buffered Interconnect The interconnect delay is computed based on the configuration shown in Fig. 2, with intermediate buffers inserted to minimize delay. The interconnect capacitance is computed based on the models given in [8] and the wire length is optimized according to the method given in [9]. For optimally buffered interconnect, we must consider variation in the intermediate buffers as well as the wires. Here, metal linewidth (LW) (and linespace (LS)) variation must also be considered. The metal linewidth variation behavior is similar to that of poly CD, where a fraction of the total variation is systematic. The metal thickness, device, and power supply variation are considered in the same way as for the clock tree.
...... 2
1
N-1
N
Fig. 2: Intermediate buffers are inserted between long wires used for routing to reduce overall path delay. Variation in the interconnect and devices can reduce the maximum length available before a latch must be inserted to meet the given clock frequency requirement.
III. Clock Skew For our first case study, we look at the impact of variation on clock skew in an H-tree [10], as shown in Fig. 1. The tree is nearly symmetric and is designed using Cu interconnect. We simulate the effects of variation for the circuit as designed in the 180nm generation and then scale it to the 50nm generation based (approximately) on the interconnect and device scaling projections given in [11] and the variation scaling scenario described by [3] (see Tables 1 and 2). Note that percentage variation tolerances are not expected to scale as we approach the 50nm generation. Table 1: Interconnect Parameters Parameter
180nm
50nm
LW/LS
1X
0.25X
Aspect Ratio
1X
Dielectric Constant
The total clock skew is computed as follows. First, the H-tree is simulated without any interconnect or device variation using Hspice. Next, the metal thickness variation in the interconnect is modeled according to [1] and the methodology described in [5] is used to model the systematic variation based on spatial information in the layout. The device variation is then computed separately for the buffer stages and the latch by modeling the H-tree with the appropriate interconnect load as given by [9] and shown in Fig. 3. Monte-Carlo simulations are performed using the tolerances for the devices and VDD as given in Table 2 for two different cases: Case 1: Use 3- σ limits for Leff, Vt, tox, VDD Case 2: Use 3- σ limits for Vt, tox, VDD Use (50%) tighter tolerance for Leff assuming fraction of variation is systematic R1/2
R2/4
RN/2N
R3/8
........ 2C1
4C2
2NCN
8C3
Fig. 3: The equivalent circuit used to model the buffer loads. Each branch in the equivalent RC network represents a branch in the H-tree.
Table 3 lists the total clock skew for the various cases, including the design scaled to the 50nm generation. A significant reduction in the skew can be obtained by tightening the Leff tolerance. In this case study, modeling CMP variation results in lower than expected skew due to cancellation effects, while worst-case analysis would always predict a larger skew uncertainty than the case without any variation. Table 3: Clock Skew in H-Tree for 180nm and 50nm Technologies Variation Source
180nm
50nm
180nm
50nm
1.3X
None
45.53
22.12
4.55
6.62
3.5
1.4
Cu CMP (systematic model)
36.85
14.83
3.69
4.44
Chip Size
17mm x 17mm
34mm x 34mm 71.28
11.66
21.34
1GHz
3GHz
Devices & VDD
116.58
Global Clock Frequency
Devices & VDD (tighter Leff tolerance)
96.96
53.40
9.70
15.59
Total Skew (worst-case device & VDD tolerances)
162.11
93.40
16.21
27.96
Total Skew (systematic model for metal thickness & tighter Leff tolerance)
133.81
68.23
13.38
20.43
28.30
25.17
2.83
7.53
Table 2: Device and Power Supply Parameters and 3-sigma Variations
180nm
50nm
Parameter
Nominal
Variation (%)
Nominal
Variation (%)
Leff (nm)
180
20
50
40
tox (nm)
2.2
10
0.7
20
Vt (V)
0.40
10
0.25
15
Skew Reduction (systematic models)
VDD (V)
1.8
10
0.9
10
Units
psec
% of clock period
IV. Variation in Optimally Buffered Interconnect For our second case study, we look at the effects of variation on optimally buffered interconnect. We choose a desired clock frequency constraint and compute the impact of variation on the maximum interconnect length, Lmax. Interconnect parameters are based on the roadmap [11]. Fig. 4 shows the degradation in Lmax for global and local interconnect lines of various pitch (constant LW and variable LS) as a function of technology. The effect on Lmax using both worstcase tolerances as well as a systematic model for metal thickness and a tighter tolerance on metal and poly CD variation are shown (assuming OPC correction is used). The effect on Lmax due to different variation sources is given in Fig. 5. Global Interconnect
Degradation in Lmax (%)
60
50
Worst-Case 40
30
20
10
LS=1X LS=2X LS=3X
Model 0 50
100
150
200
250
V. Conclusion When considering the effects of variation on circuit performance, both random and systematic variation must be included. The clock skew case study shows that random variation in the device and power supply contributes to a large percentage of the total skew. Systematic variation modeling can be used to minimize the uncertainty in skew or delay. The clock skew in our example was reduced by over 25ps for the 180nm case. A comparable reduction is seen with the design scaled to 50nm, but it is a much larger portion of the clock period because of the increase in global clock frequency. Although increasing buffer sizes can further reduce the skew, it comes at the expense of greater power dissipation, which is an important issue in high performance designs. We see that as technology scales, variation modeling becomes increasingly important in reducing uncertainty. For minimum pitch global lines, over 20% reduction in Lmax uncertainty is possible in the 50nm generation compared to less than 10% in the 250nm generation. Finally, even though both of our case studies are representative of “interconnect dominant” circuits, device variations contribute the most to variation uncertainty. Therefore, understanding and modeling device variation (especially poly CD) will be a crucial part of successful interconnect circuit design as technology scales.
Technology Generation (nm)
(a)
VI. Acknowledgments
Local Interconnect
The authors would like to thank Sani Nassif of IBM Austin Research Lab for providing the clock tree for our simulations. This work is supported in part by a grant from the MARCO Interconnect Focus Center.
Degradation in Lmax (%)
60
Worst-Case
50
40
VII. References 30
20
10
Model
0 50
100
LS=1X LS=2X LS=3X 150
200
250
Technology Generation (nm)
(b)
Fig. 4: The percentage reduction in Lmax due to worst-case variation tolerances and that due to a systematic model for metal thickness and tighter tolerance on linewidth and poly CD variation assuming OPC correction for global (a) and local (b) interconnect. Global Interconnect
Local Interconnect 60
Metal Thickness Linewidth Device Total
50
Degradation in Lmax (%)
Degradation in Lmax (%)
60
40
30
20
10
0 50
100
150
200
Technology Generation (nm)
250
Metal Thickness Linewidth Device Total
50
40
30
20
10
0 50
100
150
200
250
Technology Generation (nm)
(a) (b) Fig. 5: The degradation in Lmax due to different variation sources considered independently for global (a) and local (b) interconnect using worst-case tolerances. The total does not add since one source may offset another.
[1] T. Tugbawa et al., “A Mathematical Model of Pattern Dependencies in Cu CMP Processes,” Proc. CMP Symposium, Electrochemical Society, Oct. 1999. [2] P. Zarkesh-Ha et al., “Optimum Chip Clock Distribution Networks,” Proc. IITC, June 1999. [3] S. Nassif, “Design for Variability in DSM Technologies,” Proc. ISQED, 2000. [4] V. Mehrotra et al., “Modeling the Effects of Manufacturing Variation on High-Speed Microprocessor Interconnect Performance,” Proc. IEDM, Dec. 1998. [5] V. Mehrotra et al., “A Methodology for Modeling the Effects of Systematic Within-Die Interconnect and Device Variation on Circuit Performance,” Proc. DAC, June 2000. [6] L. Liebmann et al., “Understanding Across Chip Linewidth Variation: The First Step Toward Optical Proximity Correction,” Proc. SPIE, vol. 3051, 1997. [7] B. Stine et al., “Simulating the Impact of Poly-CD Variation on Circuit Performance,” IEEE Trans. Semiconductor Manufacturing, vol. 11, no. 4, Nov. 1998. [8] T. Sakurai, “Simple Formulas for Two- and Three- Dimensional Capacitances,” IEEE Trans. Electron Devices, vol. ED-30, no.2, 1983. [9] H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, 1990. [10] H. Hofstee et al., “A 1GHz Single-Issue 64b PowerPC Processor, “Proc. ISSCC, Feb. 2000. [11] Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 1999.
