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0.84 ps Resolution Clock Skew Measurement via Subsampling Bharadwaj Amrutur, Member, IEEE, Pratap Kumar Das, Student Member, IEEE, and Rajath Vasudevamurthy, Student Member, IEEE

Abstract—An all-digital on-chip clock skew measurement system via subsampling is presented. The clock nodes are subsampled with a near-frequency asynchronous sampling clock to result in beat signals which are themselves skewed in the same proportion but on a larger time scale. The beat signals are then suitably masked to extract only the skews of the rising edges of the clock signals. We propose a histogram of the arithmetic difference of the beat signals which decouples the relationship of clock jitter to the minimum measurable skew, and allows skews arbitrarily close to zero to be measured with a precision limited largely by measurement time, unlike the conventional XOR based histogram approach. We also analytically show that the proposed approach leads to an unbiased estimate of skew. The measured results from a 65 nm delay measurement front-end indicate that for an input skew range of 1 fan-out-of-4 (FO4) delay, 3 resolution of 0.84 ps can be obtained with an integral error of 0.65 ps. We also experimentally demonstrate that a frequency modulation on a sampling clock maintains precision, indicating the robustness of the technique to jitter. We also show how FM modulation helps in restoring precision in case of rationally related clocks. Index Terms—Arithmetic difference, asynchronous subsampling, clock skew measurement, frequency modulation, histogram analysis, time-to-digital converter.

I. INTRODUCTION RECISE on-chip delay measurement has been a challenge since the evolution of digital integrated circuits. With tight timing budgets, there is a need for measuring the skew in the clock network in the presence of increasing process variability, to enable active skew compensation. This requires measurement of skews between the periodic clock signals at various leaf nodes. Delay measurement of many circuit structures can also be converted to skew measurement of periodic signals by exciting these with a periodic source. In general, the delay is digitized using various types of time-to-digital converters (TDC). Authors in [1] propose a very precise coarse-fine time-to-digital converter based on the principle of Successive Approximation ADCs and a time amplifier. The authors in [2] propose a flash time-to-digital converter which utilizes arbiters and can be calibrated for a very high resolution. It uses the spread of arbiter threshold voltages for getting a set of digital codes from an array of arbiters to measure the delay. But it is limited by the nonuniform distribution of the offsets of the arbiters, and also

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Manuscript received February 25, 2010; revised August 05, 2010; accepted September 20, 2010. The authors are with the Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore-560012, India (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2010.2083706

works for a small timing range. The authors in [3] and [4] survey some of the popular digital techniques for delay measurements which use tapped and vernier delay line methods. Some of the issues of the traditional vernier delay line are addressed by using a component-invariant vernier delay line in [5]. Most of these TDCs have the capability to measure delays between edges of two aperiodic signals. They can also make a single shot measurement—that is, a single occurrence of an edge pair can be used to determine their time separation. The authors in [6] propose a scheme to characterize the period jitter by obtaining the cumulative distribution function of the clock edges, and modify it to measure the skew between two leaf nodes of a clock distribution network. However, when measuring skews between periodic signals, asynchronous sampling followed by histogram analysis leads to a simpler implementation. Asynchronous sampling has been proposed as a way to evaluate data converters in [7]. Asynchronous sampling clock achieves the effect of uniform random sampling across all the voltage bins for the data converter. This idea has been applied in [8]–[11] to calibrate the delay between two clock phases. Instead of obtaining histogram counts across voltage bins, the authors set up a histogram to count the number of times the asynchronous sampling clock occurs in-between the edges of the two periodic signals under measurement, by taking an XOR of the sampled outputs. The ratio of the histogram count to the total number of samples gives an estimate of the phase spacing. However, in this approach, the minimum skew that can be measured is limited by the clock jitter. As an illustration, if the two edges are at nominally zero skew, due to uncorrelated jitter between them, every once in a while, the sampler outputs will be different. This in turn causes the XOR output to go high resulting in an increment to the histogram counter, which will is then show an erroneous nonzero value for the skew. If the uncorrelated jitter for each of the two edges, then we can expect the minimum nonzero skew that can be detected with . The authors in [8] propose a 99% probability to be work-around to this limitation by measuring the skews of each clock node with reference to another signal which has a delay . Our proposed approach does away much larger than with the need for another clock signal against which to measure each node’s delay. In the Appendix, we show analytically that this approach presents an unbiased estimator of skew. We experimentally validate the technique using a 65 nm test chip and verify that the clock jitter doesn’t limit the precision, but only measurement time does. Our current work is an improvement to an earlier work discussed in [12], which has a more complex hardware implementation. The paper is organized as follows: in Section II we describe an alternative technique to determine a bin hit, which in turn gives us the input skew estimate.

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Fig. 2. Illustration of signal period amplification in subsampling system.

Fig. 1. Illustration of subsampling system. An extra sampler is introduced at each leaf node for skew measurement.

This eliminates the dependency of bin size on clock jitter and is limited (theoretically) by measurement time only. We describe our experimental setup to validate these ideas in Section III. The measurement results from a 65 nm test chip is provided in Section IV, followed by our conclusions in Section V. II. HISTOGRAM OF ARITHMETIC DIFFERENCE Fig. 3. Illustration of different source of errors in the measurement system.

A. System Overview Consider an arbitrary buffer and interconnect network, in which we need to measure the skew (or delay) between two , as shown in Fig. 1. For example, this could be nodes a clock distribution network and the nodes of interest might be leaf nodes of such a network. By exciting the input of this , of period T we can network with a periodic clock source expect periodic outputs at the two leaf nodes, which have a relative skew of . We introduce two samplers at each of these nodes, which are clocked by a separate sampling clock, with a slightly different period .1 We can use a (obtained sampling clock which is either asynchronous to by using an independent crystal source) or is rationally related (via a DLL/PLL), but has additional jitter added (through FM). The output of the two samplers will be beat signals as shown , which is in Fig. 2, whose period is given as essentially the sampling clock period amplified by a factor . The input skew is also amplified as a skew between . The skew in the subsampled outputs to be is then digitally terms of unit interval, i.e., the fraction measured by the proposed delay measurement unit. Note that will any skew in the sampling clock to the two samplers also add to the skew in the beat signals as shown in Fig. 3. But this is inevitable for any skew measurement in a distributed network which requires a reference clock. Similarly, input of the two samplers in conjunction voltage offset of the input signals also adds to the skew with finite slew in the beat signals. Hence, what the delay measurement unit ac. Thus, the tually measures is accuracy of measurement is limited by the quality of sampling clock distribution and input sampler mismatch. However, we will show later that the precision of the measurements will be

0 >

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1Note that T 1T as well as any nT 1T will also work for an integer n. However for n 1, the measurement time is increased by the factor of n to achieve the same accuracy.

largely determined by the measurement time and this will be the focus of discussion in the rest of the paper. For measuring the skew between two nodes and , a setup is used as shown in Fig. 4. Samplers are introduced at and to give subsampled signals and . These signals are processed with the aid of de-bounce and masking state machines to mask out the falling edge statistics to give , . Their dif, is accumulated in a counter for sampling ference, clock cycles. It is then right shifted by k bits (divided by ) to . Note that the delay meaobtain the digital code word for surement unit, consisting of the state machines and counters, can be shared across all the sampled nodes. By using a multiplexer to select two subsampled signals, skews between pairs of nodes can be obtained. The pair-wise skew information can then be stitched together to give the overall skew distribution across all the measured nodes. Since the subsampled outputs are in the domain of the sampling clock, which is the same as that for the delay measurement unit, routing of these signals is simplified greatly. The only constraint is the need for the same number of pipeline delays for each of the subsampled signals. This also allows for easy measurement of skews in a very high speed clock networks. Because the delay measurement unit can be shared, the area overhead for this approach is very small. Due to jitter and finite rise-time of the signals and the metastability of the samplers, their outputs will have bounces between the digital values, as shown in Fig. 5. Since we are interested in finding the skews for only one polarity of edges of and , we need to suitably mask out the samthe inputs pled signals corresponding to the falling edges. This is done via two state machines, as shown in Fig. 5. The timing waveforms of the signals used in the state machines are also sketched. The de-bounce state machine detects the first rising edge on the samsignal to cover for the high dupler output, and asserts the ration of the beat signal . The high duration of the beat signal

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Fig. 4. Setup for skew estimation.

Fig. 5. State machines and timing diagrams for various signals in the skew estimator unit.

is determined by a timer clocked by the sampling clock. After or the timer crosses the threshold, the first time either of fall, the mask signal, m, is de-asserted to de-assert and simultaneously. Now the signals and contain only the rising edge information for the input signals and , and hence their histogram analysis gives the rising edge statistics. do not get false triggered To ensure that the enable signals and to go to zero due to the bouncing edges of near the rising transitions, the threshold value should be set to an appropriate ratio. value. The upper limit on that is imposed by the In our implementation, it is set to 16 as for all the cases when and was set to 2 when as for lower ratios, getting more than two bouncing transitions around a rising edge of is highly unlikely for the practical values of jitter on the clocks. When a histogram count of the XOR of the two subsampled signals is taken as presented in [8]–[11], due to presence of jitter

on the clocks, one can expect errors for estimated skews of the order of the jitter. This can be easily understood for the case and (Fig. 6). In of exactly zero nominal skew between and , the histogram this case, due to uncorrelated jitter in count will increment to a nonzero value, which is related to the . This effect is termed as reordering issue uncorrelated in [8]. The authors in [8] get around this by using a reference and measure signal which has a much larger delay than the delays of the individual nodes against this. The values are then subtracted to give the delay between the original nodes. The proposed arithmetic difference in effect achieves this, but without needing an extra reference signal, thus reducing area and power. High resolution measurement requires the sampling clock to uniformly sample at all times between the rising edges of and . This is guaranteed by using an asynchronous sampling clock derived from an independent crystal.

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Fig. 6. Illustration of error due to jitter in input clocks for measurement of skews around zero. Fig. 7. Chip layout of the delay measurement front-end taped out in 65 nm industrial CMOS process.

B. Analytical Overview When the sampling clock is asynchronous to the clock is an irrational number driving the measurement nodes, where N is an and hence can be written as . This causes the sampling edge to fall integer and uniformly across the entire period of the sampled signal. Hence, the percentage of time the sampling edge falls in between the sampled edges is directly proportional to the skew as a fraction of the period. and be the times, within a clock period when , Let cross the logic high threshold respectively, and let be the time when the sampling clock crosses the sampling threshold. Due to become random variables. The average of jitter, , , and the arithmetic difference between the sampler outputs over sampling clock cycles is used as an estimate for the skew (1) where , the arithmetic difference between the sampler outputs. It is shown in the Appendix that: (2) Thus, the delay measurement statistic is an unbiased estimator of the skew as a fraction of the clock period (UI). A theoretical loose upper bound for the standard deviation of the estimate(derived in the Appendix) is (3)

III. EXPERIMENTAL SETUP We have fabricated a test chip in a 65 nm process node (Fig. 7). The test structures essentially consist of a number of samplers, buffers and a multiplexer, which provide the front-end for the skew estimator as discussed in Fig. 4. The two clock inputs whose skew we want to measure are supplied from outside the chip so that calibrated skews can be introduced and the performance of the technique can be studied. Similarly, the reference clock was also provided from outside to enable . The beat experimentation with different values of T and signal outputs from the multiplexers were directly taken out

Fig. 8. Measurement setup in the lab.

of the chip and processed in a FPGA board, so that various de-bouncing algorithms and digital processing options could be experimented with in a flexible manner. Since we did not have signal generators to generate two input clocks with skews in the subpico second resolution, we synthesize such delays using a cable of fixed length, and varying clock frequency. A single clock source is passed through a cable of length chosen to provide a delay of about one clock period. Then the relative delays between the edges at the input and output of the cable are given by the difference in the propagation delay through the cable and a clock period. Thus, precise delays between the edges of the input and output of the cable can be obtained by adjusting the clock period (Fig. 8). Good quality RF coaxial cables are chosen to ensure that the signals through them are not distorted due to attenuation of high-speed components. For the two clock sources, two vector signal generators (R&S SM300 and Agilent E4428C) were used. The sinusoidal signals were converted to square waves using a high speed comparator

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Fig. 10. Measured input-output delay for an input delay range of

Fig. 9. Input-output delay characteristic for an input delay range of delay and the residual error after linear fit.

6600 ps.

61FO4

ADCMP562. The rms jitter at the input of the test chip was measured to be 30 ps. The highest frequency of operation was limited by the I/O specifications of the test chip and the peripheral devices for reliable operation. Hence, the cable delay and the input delay range were chosen so that it gives zero input delay to the test chip around that frequency. IV. MEASUREMENT RESULTS Fig. 9 shows the measured output of the delay measurement unit as a function of the input delays and the residue plot after ns, doing a linear fit, with the choice of parameters ps and . For removing the delay offset due to routing from the chip pads to the sampler inputs, the input delay was swept till the output delay was measured to be zero. Within the test chip too, by shorting the sampler inputs, the input delay could be set to zero which also measured delay very close to zero (actually that gives the delay due to sampler offset). In all graphs which report results for externally provided delays, we have canceled the delay offsets due to the routing from chip pads to sampler inputs. For an input delay range of around 1 FO4 delay ( 20 ps), the measured standard deviation for each

Fig. 11. Measured standard deviation as a function of number of samples for asynchronous case.

point varies between 0.2 and 0.3 ps. The measured maximum error after a linear curve fit (integral error) is 0.65 ps. For the wider input delay range of 600 ps, the maximum integral error is 8 ps (Fig. 10). We have also tested with larger input delay ranges of 1.5 ns, which results in an integral error of 40 ps. The larger integral errors for higher input delay ranges are due to fluctuations in the rise time of the input signal to the chip. This has been verified using an Agilent 54854A (4 GHz, 20 GSa/s) Oscilloscope to observe the signals at the chip inputs. Fig. 11 shows the measured standard deviation of an on-chip delay element as a function of the number of samples for an inns, ternal delay generator with parameters of ps, and varying k. The standard deviation reduces with samples and square root of the number of samples up to sammatches well with (3). It saturates to 0.14 ps beyond ples and hence is the limit of the resolution that is achievable with our setup, leading to a resolution of 0.84 ps. Theoretically, with the assumption of independence between each of the core clocks and the sampling clocks, the variance of estimated skew

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Fig. 12. Measured standard deviation as a function of number of samples for rationally related sampling clock case with FM, for different modulation indices.

decreases monotonically as the number of samples increases. However, in a practical setup, correlations between the core clocks (leaf nodes) show up as they are derived from the same source. Moreover, the samples across time are also correlated noise in the signal sources, and their statistics are due to time dependent. Hence, the variance of estimated skew is lower bounded due to these correlated jitter components, which cannot be reduced by simple averaging. Adding jitter to the signals doesn’t affect the resolution and in fact improves resolution in certain cases. For example consider the case when the sampling clock is rationally related to . In this the measurement clock with period as . However case, the measurement resolution is limited to it can be increased to almost the same level as that of the asynchronous sampling case by using frequency modulation on the sampling clock. This acts as jitter and randomizes the sampling edges, mimicking the asynchronous case. For validating this in the lab, we connected the reference out signal of the core clock source to the reference in point of the sampling clock used in Fig. 8. With this change both the sources are frequency locked to a single crystal and using their internal PLLs they generate rationally related core and sampling clock frequencies. The sampling clock source has the option of providing frequency modulation, which is used to create artificial jitter. Fig. 12 shows the standard deviation of measured delay of an internal delay source for ns, , with and without frequency modulation. The error in measured delays is large for the case of no frequency modulation. However, measured standard deviation decreases as square root of number of samples similar to the asynchronous case of (3), for FM deviation of 5 kHz. The results are same for frequency modulation frequencies of 20 Hz or 100 Hz except the fact that for smaller modulation indexes , the minimum standard deviation obtainable was 0.3 ps where as with higher FM dev. of 5 and 80 kHz it could be improved to 0.14 ps. Such a phenomenon where noise improves resolution is well known in threshold systems [13]. Fig. 13 shows the measured delay of an internal delay element for ns. For the cases when across different

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Fig. 13. Measured delay of internal delay element across different ns with and without applying frequency modulation. :

T = 8 33

1T’s for

is integer, the error becomes high. The number of samples for . With frequency modulation, each measurement is at least even for the integer ratio case, the delay error reduces to that for as shown in Fig. 13. other values of Besides the averaging error, the other sources of error in the skew measurement are the mismatches in the input offset voltage of the two samplers and the skews in the sampling between the two clock. With a voltage offset of samplers and a input slew rate of , the error introduced is , and needs to be minimized by careful sizing and fast edge rates. If the two test nodes are close by, then we can also apply offset compensation scheme like in [8] by giving zero delay inputs to the samplers and compensating their offsets by digitally calibrating their trigger points. The skew at the sampling clock inputs of the two samplers must be minimized by careful routing. This component of error is bound to be there in any scheme where the skew between two distant nodes are to be measured as that necessitates a reference clock. As a simple application of this technique, we measure the setup window mismatches of samplers using a test structure shown in Fig. 14(a). Eight pairs of samplers are fed by the same input signal and each pair’s output is fed to the delay measurement unit. Note that a single delay measurement unit can be used to measure delays across many pairs of nodes, thus reducing the area overhead significantly. Since the samplers are laid out in close proximity, there is no input skew in the data as well as the clock inputs and what is measured is the effect of sampler mismatches. Fig. 14(b) shows the measured sampler mismatch for the eight pairs to be within 1 ps with a standard deviation of ns, ps and samples taken 0.14 ps with for averaging. The rather large offset of the sampler mismatches is due to poor rise time of the sampling clock, which was confirmed with post layout simulations. In another experiment, we measured the supply voltage dependency of the delay of an internal buffer using the setup as shown in Fig. 15(a). The measured delay in Fig. 15(b) was close to the layout-simulated delay of the internal buffer. Lesser number of samples were required in this measurement as compared to those taken for Figs. 9 and 10 as in this case, the input

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Fig. 14. Characterization of sampler mismatch. (a) setup to measure mismatch between eight pairs of samplers. (b) Measured results.

Fig. 15. Characterization of dependence of delay of an internal buffer on supply voltage. (a) setup to measure supply voltage dependence of delay of an internal buffer; (b) results obtained.

delay being that of an internal buffer is more stable than the externally fed cable delays. As shown in the figure, delay increments of less than 1 ps can be resolved. sampling clock cycles and we The measurement time is can relate it to standard deviation and hence resolution , from (3), as (4) The measurement time per conversion is around 140 ms in order to obtain a resolution of 0.84 ps. In case of shared

measurement across different leaf nodes, the measurement time will be increased by the number of leaf nodes for which the measurement has to be performed. Hence, there exists a trade-off between the area overhead and the measurement time. But, since the skew measurement unit requires relatively small area (around 1 K NAND2 equivalent gates) and doesn’t need any placement constraints, multiple copies of it can be replicated to reduce the total measurement time for shared measurement cases. Because of relatively small gate count and very low activity factor (since the data inputs are subsampled inputs), the power consumed in the delay measurement module is quite insignificant.

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V. CONCLUSION Asynchronous subsampling followed by statistical averaging allows measurement of static skews between periodic signals. The proposed techniques of de-bouncing followed by averaging of the arithmetic difference of the signals remove any dependency of resolution with sampling clock jitter, unlike in previous works. Measured results from a 65 nm test chip indicate resolution of 0.84 ps the ability to measure skews with a and integral error of 0.65 ps for an input skew range of 1 FO4 delay( 20 ps). The technique can also be used to measure larger , where T is the clock period. The skews even close to precision is unaffected by clock jitter as a measurement resolution of 0.84 ps is obtained with clock sources with 30 ps rms jitter. This is further validated by experiments where frequency modulation on sampling clock preserves the resolution. In fact, in certain cases where the sampling clock is rationally related to core clock, frequency modulation improves resolution, which is otherwise degraded.

with that

, the difference of the ith samples. It follows (10)

sampling instant. where is the Let the clock period be and the sampling clock period be , where , where is an integer and . This causes the sampling edge to fall uniformly across the entire period of the sampled signal to create one beat beat periods, so period. Let the measurement be taken over . Hence, (9) can be rewritten as

(11) Let period. Then

be the starting phases in each beat

APPENDIX In this appendix, we will sketch the derivations for (2) and be the times within a clock (3) of the main text. Let , cross the logic high threshold period when data clocks , be the time when the sampling clock respectively, and let crosses the sampling threshold. Due to jitter, these are random variables. Without loss of generality, let the mean of be zero. is , the quantity to be estimated. The mean of Let

(12) Substituting from (10), applying the law of iterated expectation and reordering the summation, we get

(13) and let (5) is the random compowhere is the mean value of , and nent. It is of interest to determine the probability that the samplers sample a logic high. A sampler samples a logic high if the sampled clock edge occurs earlier than the sampling clock edge. Hence (6) Let

. Let

be the CDF of

. From (6) (7)

Let

. Let

be the CDF of

, (with PDF of ), the Since s are uniform over 0 to inner expectation is identical for each and can be evaluated as the following integral:

(14) The above summation can be replaced by an integral over the entire clock period . However, if we assume that the skew and the jitter of the clocks are small compared to the period , as then the limits of the integration can be replaced by (15)

. Then In general, evaluating this integral is difficult. However, in this particular case, we can revert to the following trick of differentiating (15) with respect to (8) (16)

The output of the delay measurement unit of (Fig. 1) is given as Since the term inside the integral is a PDF and integrates to unity, proving (2) (9)

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The variance of

9

can be bounded as

from which the bound on the standard deviation of S given in (3) follows:

[10] D. Weinlader, H. Ron, C.-K. K. Yang, and M. Horowitz, “An eight channel 35 gsample/s CMOS timing analyzer,” in Proc. ISSCC Dig. Tech. Papers, 2000, pp. 170–171. [11] D. Fick, N. Liu, Z. Foo, M. Fojtik, J.-S. Seo, D. Sylvester, and D. Blaauw, “In situ delay-slack monitor for high-performance processors using an all-digital self-calibrating 5 ps resolution time-to-digital converter,” in ISSCC Dig. Tech. Papers, 2010, pp. 188–189. [12] P. K. Das, B. Amrutur, J. Sridhar, and V. Visvanathan, “On-chip clock network skew measurement,” in Proc. A-SSCC Dig. Tech. Papers, 2008, pp. 401–404. [13] L. Gammaitoni, “Stochastic resonance and the dithering effect in threshold physical systems,” Phys. Rev. E, vol. 52, no. 5, pp. 4691–4699, Nov. 1995.

ACKNOWLEDGMENT The authors gratefully acknowledge the help of Dr. V. Viswanathan and J. Sridhar from Texas Instruments, Bangalore for their support in chip fabrication; V. Janakiraman for help during chip design; V. Syam for help in board design and J. Balaji for discussions.

Bharadwaj Amrutur (M’08) received the B.Tech. degree in computer science and engineering from Indian Institute of Science, Bombay, India, in 1990 and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Palo Alto, CA, in 1994 and 1999, respectively. He has worked at Bell Labs, Agilent Labs and Greenfield Networks. He is currently an Assistant Professor in the Department of Electrical Communication Engineering at Indian Institute of Science, Bangalore, India, working in the areas of VLSI

(17) From (9) and (17) (18)

REFERENCES [1] M. Lee and A. Abidi, “A 9 b, 1.25 ps resolution coarse-fine time-todigital converter in 90 nm cmos that amplifies a time residue,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 769–777, Apr. 2008. [2] V. Gutnik and A. Chandrakasan, “On-chip pico second time measurement,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, 2000, pp. 52–53. [3] M. A. Abas, G. Russell, and D. J. Kinniment, “Built-in time measurement circuits—A comparative design study,” IET Computers & Digital Techn., vol. 1, no. 2, pp. 87–97, Mar. 2007. [4] P. J. Restle, R. L. Franch, N. K. James, W. V. Huott, T. M. Skergan, S. C. Wilson, N. S. Schwartz, and J. G. Clabes, “Timing uncertainty measurements on the power5 microprocessor,” in Proc. ISSCC Dig. Tech. Papers, 2004, pp. 292–293. [5] A. H. Chan and G. W. Roberts, “A jitter characterization system using a component-invariant vernier delay line,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 1, pp. 79–95, Jan. 2004. [6] K. A. Jenkins, A. P. Jose, Z. Xu, and K. L. Shepard, “On-chip circuit for measuring period jitter and skew of clock distribution networks,” in Proc. IEEE CICC Dig. Tech. Papers, 2007, pp. 157–160. [7] J. Doernberg, H.-S. Lee, and D. A. Hodges, “Full-speed testing of a/d converters,” IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 820–827, Dec. 1984. [8] L.-M. Lee, D. Weinlader, and C.-K. K. Yang, “A sub-10-ps multiphase sampling system using redundancy,” IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 265–273, Sep. 2006. [9] T. A. Knotts, D. Chu, and J. Sommer, “A 500 MHz time digitizer ic with 15.625 ps resolution,” in Proc. ISSCC Dig. Tech. Papers, 1994, pp. 58–59.

Circuits and Systems.

Pratap Kumar Das (S’08) received the B.Tech. degree in instrumentation and electronics engineering, from College of Engineering and Technology, Bhubaneswar, India in 2005. Since 2005, he has been pursuing the Ph.D. degree at the Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore. One of his papers was selected to be among the Noteworthy Technical Papers in the Asian Solid-State Circuit Conference, 2008. His research interests include custom digital circuit design for measuring and mitigating variability in deep submicron CMOS technologies.

Rajath Vasudevamurthy (S’09) received the B. E. degree in Electronics and Communication Engineering, from R. V. College of Engineering, Bangalore, India in 2007. Since 2007, he has been working toward the Ph.D. degree at the Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore. His research interests include VLSI Circuits and Systems, Mathematical modeling and Communication systems.