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Test Sequence Generation For Stuck-Open Faults in CMOS Circuits

Peilin Song, John Hammen and Jien-Chung Lo Department of Electrical and Computer Engineering The University of Rhode Island Kingston, RI 02881-0805

Abstract

This paper describes the use of a previously proposed test generation program named Jethro [1] on test sequence generation for stuck-open (SOP) faults in CMOS circuits. Test pro les for gates and/or VLSI cells that consist of local minimum test sequence are made available for Jethro to generate the global test set. This paper presents the derivation of such test pro les with respect to SOP in CMOS simplex and complex gates. The formation of test pro les also guarantees local robust tests. Results on ISCAS85 benchmark circuits are presented. 1

1 Introduction

Test coverage of a production test has a direct impact on the defective parts per million (DPM) measurement. Increasing the test coverage of the realistic defects is a very important issue. Knowing that single stuck-at fault (SSAF) model will not cover most probable defects in CMOS gates [2, 3, 4, 5, 6], stuck-open fault (SOP) model has been introduced to improve the detection of the realistic defects [2]. The detection of a stuck-open fault needs a sequence of two test vectors. The rst pattern is applied to initialize the output of the gate; and the second one is then used to detect the stuck-open fault [3, 4, 5, 6]. Moreover, the tests for stuck-open faults could be invalidated by the timing skews/delay, glitches, or charge distribution between various nodes of a faulty gate [7, 8]. Robust tests have been introduced to avoid these problems [7, 9]. Many methods of deriving test patterns for SOP faults have been proposed [4, 5, 6, 9, 10, 11, 12, 13]. Both the gate level model [4, 5, 6, 9, 12, 13] and the switch level model [10, 11] have been adopted to gen1 This work is supported by the National Science Foundation under grant MIP-9308085

erate the test patterns. Jain and Agrawal [6] have presented a procedure which logically converts a CMOS network containing stuck-open faults into an equivalent circuit with stuck-at faults, and hence, the introduction of the B-block element. Thereby, the conventional test generation algorithms for SSFA model can be used to generate the tests for SOP model. However, the B-block memory element may make the test generation problem very dicult and it cannot model all the cases for stuck-open faults. In [12], Cox and Rajski have proposed a technique of transforming stuck-open faults in a CMOS circuit into equivalent transition faults in the equivalent gatelevel circuit. Although the robust tests can be generated, it is time-consuming since all possible combinations of values from inputs of a gate are applied to calculate the correspond outputs. The idea of converting a CMOS circuit with stuckopen faults into an equivalent gate level circuit with equivalent sequence of stuck-at faults has been used in [13]. In [13], it was shown that the stuck-open test set could be given by rearranging the sequence of stuck-at test patterns. In particular, the second test pattern in a sequence for the detection of stuck-open fault was chosen rst based on the equivalent stuck-at fault for one node. The rst test pattern, detecting the opposite stuck-at fault at the output, could be identi ed accordingly. Unfortunately, the condition for a robust test cannot be guaranteed using this scheme. In this paper, instead of converting the stuck-open faults into stuck-at faults, we analyze and simulate a CMOS gate at circuit level with stuck-open faults to determine the test sequences. This is a time consuming process and may require some interactions. Therefore, in an one-time eort, we simulate all the basic cells from the standard VLSI library and prestore all the local minimum test sequences in Test Pro-

les database. We then use a previously proposed test generation program named Jethro to generate the test sequence for the circuit under test (CUT). In [1], we have reported the SSAF model test generation using Jethro. This program has been designed with a prevision to handle the generation of test sequences. The core of the test generation program is a modi ed FAN [14]. This paper is organized as follows. In Section 2, we will describe the test generation program Jethro [1] and its adaptation to test generation for SOP faults. Section 3 will discuss in detail the methodology of deriving robust test sequences for both simplex and complex CMOS gates and the construction of test pro les. In Section 4, we present the results on the ISCAS85 benchmark circuits [15]. Section 5 gives conclusions and future directions.

2 Test Generation Program

In this section, we describe the test generation program Jethro that generates test set for CUT based on the pre-computed test pro les.

2.1 Overview

In order to generate the test sequences for CUT, the global list of targets is assembled from the local target list of every cell in the whole circuit's netlist. A slightly modi ed FAN [14] algorithm is used to generate global solutions to satisfy these local requirements/sequences. In this study, by the time the FAN algorithm is used to generate test patterns, any cell from the CUT can be seen as a black box. Because it is assumed that matching the target from the test pro le will create a discrepancy on the output of the cell under test, the test generation problem becomes that of nding a global test pattern that will both match the target and propagate the resulting error to a primary output. Here, the only information needed from the test pro le is the actual targets and the boolean function realized by each cell. Because FAN, as given in [14] is designed to operate on the single stuck-at fault, it was necessary to slightly modify the algorithm in order to test for the local targets given by the test pro les. The rst step of the FAN algorithm is to assign an error to the cell under test, and compute the implications of this assignment. In our case, it is to assign the input values to the cell under test as speci ed by the local target. Note

that the assignment of the input values can lead to an inconsistency when the implications are computed, immediately showing the target to be untestable. If this is not the case, then the appropriate error value is placed on the output of the cell under test, and FAN can proceed as usual in its attempt to propagate this error.

2.2 Dynamic Compaction

The dynamic compaction scheme used in this system operates by choosing a primary local target, and, if a test is successfully generated for this local target, checking to see if any secondary local targets can be satis ed given the current PI assignments. This is accomplished by using the FAN algorithm with the restriction that no line in the circuit that is currently assigned can be changed. Thus, if a test is not possible for the current secondary target given the already assigned PI's, FAN will nd the target to be untestable in this global test pattern. If the current secondary target is satis ed by current PI assignments, FAN will immediately return `success', and the target can be marked as done. If there exists PI's that are not speci ed in the current global test pattern, a third scenario can arise where the current PI assignments do not constitute a test for the current secondary target, but a test may be possible by assigning one or more currently unassigned PI's to a binary value. In this case, FAN will either continue to ll in the unspeci ed primary inputs, in order to cover the secondary target, or it will nd the secondary target to be untestable given the PI assignments that constitute a test for the primary target. This type of compaction is more aggressive than typical approaches that randomly ll in unspeci ed primary input values and fault simulate possible secondary faults, because every line is heuristically assigned in order to meet some goal. Thus, we would expect better compaction. A possible problem is of course the relatively large computation time associated with running the entire FAN algorithm, as opposed to fault simulation, but this has not been found to be a problem for the results of this paper.

2.3 Example

Let's use circuit c17 from the MCNC ISCAS85 benchmark suite as an example to illustrate the proposed test generation process. Figure 1 shows circuit

Targets

Targets

1 3

0 1

gate 1 1

10

D

gate 2

6 2

7

X

2

11

X 3

D 1 5

22

4

X

gate 3 gate 4

16

0

X

D

6

X

23

gate 5

19

gate 6

01 10 11 01 10 11 01 10 11 01 10 11 01 10 11 01 10 11

1 3

0 1

gate 1 10

1

1

gate 2 11

6 2

7

0

2

1 1 5

D 3

22

4

6

D

gate 3 gate 4

16

0

1

0

D

23

gate 5

19

gate 6

01 10 11 01 10 11 01 10 11 01 10 11 01 10 11 01 10 11

Figure 1: The benchmark circuit c17 with list of local targets after primary assignments.

Figure 2: Removing the entries from the list of targets, after primary and secondary assignments to satisfy (01) at gate 1.

c17 which consists of six two-input NAND gates. The target list is generated as shown on the right of Figure 1 according to the test pro le for the single stuck-at faults of a two-input NAND gate. The rst target to be attempted is 01 on the inputs of gate 1. This is the primary target. Assuming that all lines in the circuit are at state `X', we rst assign values to the inputs of gate 1 as speci ed by the target. At this point, an error value is automatically placed on the output of gate 1 (D in Figure 1.). It is assumed that an error value is generated on the output of a cell or module if the states of its inputs match those speci ed in the test pro le. At this point, the standard decision making process of FAN takes over, and assigns a logic 1 to the currently unspeci ed input of gate 5 in order to propagate the error to a primary output, and then assigns a logic 0 to primary input 2, in order to justify the resulting bound line (See Figure 1.). These assignments result in a test for the primary target, and its removal from the global target list (01 from gate 1 and 11) from gate 5). At this point, the current values of all lines not at state `X' are \set in stone", and secondary targets are attempted one by one, in order to see if they can be covered by the current pattern. In this example, target 01 of gate 5 is an example of a target that is clearly incompatible with the current state of the circuit. On the other hand, target 10 of gate 2 is not seen to be incompatible, so this target is assigned and the error generated.

At this point, using the multiple backtrace procedure of FAN, it is decided to assign a logic 1 to primary input 7, resulting in the propagation of the error to a primary output, and subsequently, the removal of this secondary target from the global list, as shown in gure 2. After all possible secondary targets have been attempted, the next target not yet covered, in this case target 10 of gate 1, is taken as the next primary target, and the process repeats, until every target that needs it has been tried as a primary target. Table 1 shows the results for stuck-at faults from test generation runs. We also include the run results using Nemesis [16] to provide a basis of comparison. Jethro is comparable to Nemesis in all categories of comparisons. These test generation runs are performed on a Sun SPARC 5 with 85MHz system clock and 64MByte main memory. The CPU times for both Nemesis and Jethro are obtained from the same machine. The give-up's in Table 1 for the Nemesis are those failed-faults as in [16]. For Jethro, the column untestable records the number of local target tests that cannot be satis ed. The give-up column shows the number of targets that cannot be generated by the proposed program within a reasonable threshold. For the test generation runs listed in Table 1, the give-up threshold has been set at 100. That is, Jethro will give up a target after 100 backtraces.

1

Give-up

Test

Total Circuit

2

Untestable

Time (secs)

Coverage (%)

Targets

Faults

C432

417

524

70

40

0

6

4

12

12.1

1.70

99.2

95.7

C499

530

758

55

145

1

0

8

8

18.8

1.21

98.8

98.5

C880

934

942

67

35

0

0

0

0

15.2

0.91

100

100

C1355

1466

1574

98

104

0

2

8

8

41.1

12.51

99.5

99.3

C1908

1500

1879

134

140

0

4

9

7

74.7

16.22

99.5

99.3

C2670

2235

2747

135

100

0

25

117

90

113.5

44.06

95.7

94.9

C3540

3182

3428

199

125

0

1

137

153

263.5 159.53 96.0

95.2

C5315

4905

5350

187

77

0

0

59

59

111.7

23.32

98.9

98.9

C7552

6836

7550

286

117

0

54

131

81

302.3

49.25

98.3

98.0

ave

2446

2750

136

98

~0

10

53

46

105.9

34.30

98.4

97.8

Nemesis Proposed Nemesis Proposed Nemesis Proposed Nemesis Proposed Nemesis Proposed

1. The total number of local test targets handled by the proposed test generation program. 2. The number of total faults given by MCNC ISCAS85 benchmark.

Table 1: Test generation results for stuck-at faults Jethro is faster for all the circuits and produces a smaller test set for most of the cases (except C499, C1355 and C1908) than those by Nemesis. The fault coverage is only slightly less than those by Nemesis but it can be improved by increasing the backtraces threshold value.

2.4 Adaptation for SOP Faults

As we know, two test vectors are needed to detect a SOP fault. The rst one is used to initialize the gate and the second one is used to test the SOP fault. In other words, the second test vector should be applied right after the rst one. Therefore, we need to modify our test pro les in the way that the second test vector should immediately follow the initial vector. Jethro has been designed to recognize this special condition for SOP faults. In the above example, a target is pick up randomly from the list of targets until the list becomes empty; which means all the possible faults have been examined. However, for a SOP fault we have to add one restriction that the second vector should be generated immediately after the rst test vector has been generated. In this process of dynamic compaction, we also need to observe this restriction. When a global test is generated, we propagate forward

the logic values and compare them with the local test targets. If a match is found we have to make the following decisions: 1. If the local target is the rst vector in a two-vector test sequence, we mark the entry. 2. If the local target is the second vector in a twovector test sequence, we have the following two cases: a. If the rst vector has been marked, remove both entries; b. If the rst vector has not been marked, no entry will be removed. 3. If no match is found, remove all marks. The above procedure guarantees that proper local robust test sequences are generated. Of course, in a test pro le, the second vector for a SOP fault A1 may also be the rst vector of another SOP A2 fault. In this case, the above procedure remains unchanged except for 2.a. In that case, only the entry of the rst vector of A1 will be removed and the second vector of A1 or the rst vector of A2 will be marked.

Vdd

A

P1

B

P2

.i 2 .o 1 .t 4 C

N1

N2

00s 01s 00s 10

Gnd

a) Transistor level

b) Test profile

Figure 3: A two-input CMOS NOR gate.

3 Test Pro les for SOP Faults

In this section, we show how the robust test sequence can be generated to form the test pro le for a primitive CMOS gate and CMOS complex gate. Similar approaches can be used to form the pre-determined test pro les for all the other simplex CMOS gates (NAND, AND, OR, etc.) and CMOS complex gates.

3.1 Robust Test Sequence in Primitive CMOS Gates

Consider a two-input CMOS NOR gate shown in Figure 3. There are four stuck-open faults need to be considered in this gate which correspond the four transistors. Obviously, to detect all the stuck-open faults, the test sequences should be chosen from the set AB=f00, 01, 10, 11g, where each value represents the one assigned to the primitive input. Let us consider a stuck-open fault on transistor P1, as shown in Fig. 3. In order to detect this fault, proper initial test sets should be set up rst which force the output C=0. This means that the test sets need to be applied with AB=01, 10, or 11 since each of these three patterns can force the output to become 0, respectively. If the second test needs to be applied now with AB=00, then output C, with P1 open, will be 0, but would be 1 in a fault-free gate. Then the stuck-open fault on transistor P1 is detected. However, if the rst set was AB=00, whatever the second set was applied, the fault de nitely cannot be detected. Similarly, the stuck-open fault on transistor P2 can be detected by the same test sets used to detect SOP on P1 , as described above. Therefore, we say that the stuck-open

faults on transistors P1 and P2 are equivalent. In general, the stuck-open faults on the transistors that are connected in series could be equivalent. For example, three stuck-open faults on three p-type transistors in a three-input CMOS NAND gate are identical. This will lead to a more compact fault set. To detect SOP fault on transistor N1, the initial test set is AB=00, which, unlike that dealing with SOP on P1 and P2, is unique. This will force the output C=1. If the second test vector needs to be applied now with AB=01, then output C, with N1 open, will be 1, but would be 0 in a fault-free gate. Then the stuck-open fault on transistor N1 will be detected. Similarly, the stuck-open on transistor N2 can be detected by applying the test sequences AB=f00 ?! 10g. Note that the SOP faults on N1 and N2 are not equivalent since the test sequences are dierent. Generally, the stuck-open faults on the transistors which are connected in parallel are not equivalent. Although the initial test sets are the same, 00 for the NOR gate shown above, the second test sets are different. From the above analysis, we can conclude that four stuck-open faults in a CMOS NOR gate can be detected by three two-vector test sequences. Reorganizing and optimizing the test sequences, the nal test sequences to detect the SOP faults in CMOS NOR gate can be obtained: AB=f00 ?! 01 ?! 00 ?! 10g. These sequences of four test vectors include three twovector sequences, namely: f00 ?! 01g, f01 ?! 00g, and f00 ?! 10g. The \s" associated with the entries in the Test Pro le, as shown in Figure 3, denotes the beginning of a two-vector sequence. Obviously, they are the local robust tests since they do not get invalidated even in the presence of delays. It is easier to obtain the robust test sequences for the primitive CMOS gates than for the CMOS complex gates. In next subsection, we will discuss the generation of robust test sequences for a CMOS complex gate.

3.2 Robust Test Sequences in CMOS Complex Gates To illustrate the robust test sequences for a complex gate, we consider the CMOS complex gate shown in Fig. 4. There are six transistors in this gate. This means that there are six possible stuck-open faults. Actually, the stuck-open faults on transistors P1 and P2 are equivalent. Then the total number of stuckopen faults is only ve.

Vdd

A

P1

C

P2

B

P3

E A

B

N1 C

N2

N3 .i 3 .o 1 .t 6

Gnd

a) Transistor level

A C E

B

b) Gate level

001s 011s 010s 110 111s 101

lay. With help of the directed graph, the optimal test sequences are obtained by traversing the graph [13]. Figure 5 shows the directed graph of the test sequences for CMOS complex gate shown in Fig. 4. Each circle denotes a test set. We can start to traverse the graph either from ABC=001 or 100. If we pick 001, all the stuck-open faults except P3 can be detected by the following sequences: f001 ?! 011 ?! 010 ?! 110g. If we pick 100, the test sequences are: f100 ?! 110 ?! 010 ?! 011g. In order to detect stuck open fault on P3, sequence f111 ?! 101g should be added to the above sequences either at the beginning or at the end. Then there are four two-vector test sequences for detecting all the stuck-open faults in the complex gate. The test pro le of this complex gate is shown in Figure 4(c).

c) Test Profile

Figure 4: A CMOS Complex gate.

P1, P2 001

To detect the stuck-open fault on transistor N1, the initialization set is introduced to sensitize the fault which means that the output E can be pulled-up to logic 1. The set can be chosen from ABC=f000, 010, 101, 100, 001g. The second set of the test sequence can be chosen from ABC=f110g. Note that a total of ve test sequences can be obtained from the above analysis. However, not all these test sequences can be used to detect the stuck-open fault on transistor N1 because of the timing delay. A robust test sequence must be used to avoid the potential invalidation of the test due to the arbitrary delay. A robust test sequence is a sequence of two sets which are dierent from each other in only one bit position. In other words, the Hamming distance between the rst and the second test vectors is only one. Therefore, the robust test sequences to detect the stuck-open fault on transistor N1 are ABC=f010 ?!110g, or f100 ?! 110g. Other stuck-open faults are analyzed similarly. Table 2 shows the robust test sequences of the six SOP faults. It is interested to note that the test sequence ABC=f111 ?! 010g should also be used to detect the SOP faults on P1 and P2, although the Hamming distance of these sets are two. This means that this test sequence cannot be invalidated by the timing de-

N1, N3

N2, N3

N1, N3 011

010 N2, N3

110

100

P1, P2 N3

101

111 P3

Figure 5: Graph of test sequence for the CMOS complex gate shown in Figure 4.

3.3 Test Pro le

A test pro le of a gate or a VLSI cell has identical format as shown in Figure 3(b) and Figure 4(c). Information such as number of primary inputs, number of primary outputs, and number of test vectors are provided. In the case of SOP faults, a \s" is used to denote the rst vector of a two-vector test sequence. Of course, some second vectors may also serve as the rst vector of another two-vector test sequence. For this study, we use the MOSIS CMOSN 3.0 cell library as the standard cell library. As pointed out earlier, the Test Pro les contain local robust test sequence. This test pro les approach is similar to that of hierarchical test generation [17]. We may recursively use the proposed approach to generate test pro le for a fairly complex module, e.g. an n-bit binary adder. However, the goal of the proposed approach is to even-

SOP Faults P1, P2 P3 N1 N2

N3

Initialization Set (011,110,111) (011,110,111) (000, 010, 101, 100, 001) (000, 010,101, 100, 001)

Second Test (010) (101) (110) (011)

Robust Test Sequence (011?!010), (110?!010) (111?!101) (010 ?! 110), (100?!110) (010 ?! 011), (001 ?! 011) (010?! 011), (001?!011), (000, 101, 101, 100, 011) (011, 100, 111) (010?!110), (100?!110), (101?!111)

Table 2: Test sets for SOP faults in complex gate tually handle test generation for realistic defects. The analysis of a CMOS gate or cell with respect to realistic defects is manageable in size.

4 Experiment Results

The test generation results for stuck-open faults are shown in Table 3 in which all the categories are the same as in Table 1. We also include the results run on SOPRANO [13] to do the comparison. The giveup's and untestable's in Table 2 for SOPRANO are the aborted's and redundant's in [13] respectively. Here the give-up threshold has still be set to 100. From Table 3, it is noted that the results on c432 and c499 are not given in SOPRANO. The reason is that SOPRANO cannot handle a circuit which has XOR/XNOR gates since it is hard to get the potentially equivalent stuck-at faults for stuck-open faults in XOR/XNOR gates. This transformation of the dierent fault models is the basis of the methodology of SOPRANO. We generate the test pro les for XOR/XNOR gates based on the circuits simulation. Here XOR/XNOR gates are the basic cells of Mosis Cell library. As seen in Table 3, the test sizes of the proposed program for all of the circuits are smaller than those of SOPRANO which means we have a good dynamic compaction scheme. In SOPRANO, the forward and backward simulations were used to reduce the test size. The fault coverage of the proposed program is the same as that of SOPRANO on average. It is noted here that the fault coverage of the proposed program is the result of the sum of give-up's and untestable's targets over the total targets while the fault coverage of SOPRANO is the result of the sum of give-up's and untestable's faults over total faults. In SOPRANO,

the test generation is based on two steps: gate level test generation using FAN and a parallel pattern single fault simulation. The application of the fault simulation signi cantly reduces the whole test generation time. In proposed program, only the modi ed FAN is used to generate the test. Then there is no comparison with SOPRANO in test generation time.

5 Conclusions

In this paper, we have demonstrated that a previously proposed test generation program can be used to handle SOP faults with appropriate test pro les. The program is based on the strategy to generate the tests for CUT from optimal local test sets of gates or cells. We also demonstrate the construction of test pro les with local robust test sequences for the CMOS simplex and complex gates or cells. The experiment results are presented for ISCAS85 benchmark circuits. We note that the test program can be further adapted to include a more comprehensive fault and/or defect models by simply changing the test pro les of the gates or cells. Although each local target handled by the test generation program is robust, a completely robust global solution for the CUT is not guaranteed. In the future, we will generate the global robust test by modifying the program with restriction so that the timing skews/delay will not invalidate the test.

References

[1] J. Hammen, P. Song, and J.-C. Lo, \Test generation based on testing pro les," in 4th Annual Atlantic Test Workshop, 1995.

Test

Total

Give-up

Untestable

Time (secs)

Circuits Targets Faults

SOPRANO

proposed

SOPRANO

proposed SOPRANO

proposed

Coverage (%) SOPRANO proposed

c432 *

751

515

142

12

23

2.77

95.3

c499 *

872

714

212

2

6

2.07

99.1

c880

1569

1112

202

95

0

0

0

0

2.27

100

100

c1355

2120

1610

337

305

18

111

8

6

10.42

98.4

94.5

c1908

3013

2378

401

374

4

43

7

6

23.65

99.5

98.4

c2670

4223

3269

397

292

69

51

119

86

157.35

94.3

96.8

c3540

6059

4608

703

469

2

24

216

166

179.91

95.3

96.9

c5315

9145

6693

609

292

1

7

60

57

111.09

99.1

99.3

c7552

12378

9656

793

448

129

83

95

69

189.96

97.7

98.8

ave

4459

3395

492

292

32

37

71

47

75.49

97.7

97.7

* The experiment results of c432 and c499 are not given in SOPRANO.

Table 3: Test generation results for stuck-open faults [2] R. L. Wadsack, \Fault modeling and logic simulators of CMOS and MOS integrated circuits," Bell Syst. Tech. J., pp. 1449{1474, May-June 1978. [3] J. Galiay, Y. Crouzet, and M. Vergniault, \Physical versus logical fault models MOS LSI circuits: Impact on their testability," IEEE Trans. on Comput., pp. 527{531, June 1980. [4] Y. M. El-Ziq, \Automatic test generation for stuck-open faults in CMOS VLSI," in Proc. 18th Design Automation Conf., pp. 347{354, June 1981. [5] Y. M. El-Ziq and R. J. Cloutier, \Functionnallevel test generation for stuck-open faults in CMOS VLSI," in Proc. Int. Test Conf., pp. 536{ 546, Oct. 1981. [6] S. Jain and V. D. Agrawal, \Test generation for MOS circuits using D-algorithm," in 20th Design Automation Conference, pp. 64{70, 1983. [7] S. Reddy and M. Reddy, \Testing realizations for FET stuck-open faults in CMOS combinational logic circuits," IEEE Trans. Comput., pp. 742{ 754, Aug. 1986. [8] A. J. R. Rajsuman and Y. K. Malaiya, \CMOS open-fault detection in the presence of glitches and timing skews," IEEE J. Solid-State Circuits, pp. 1055{1066, Aug. 1989.

[9] S. M. Reddy, M. K. Reddy, and V. D. Agrawal, \Robusts tests for stuck-open faults in CMOS combinational logic circuits," in 14th FaultTolerant Comput., June 1984. [10] K.-W. Chiang and Z. G. Vranesic, \On fault detection in CMOS logic networks," in 20th Design Automation Conference, pp. 50{56, 1983. [11] M. K. Reddy, S. M. Reddy, and P. Agrawal, \Transistor level test generation for MOS circuits," in Proc. 22nd Design Automation Conf., pp. 825{828, June 1985. [12] H. Cox and J. Rajski, \Stuck-open and transition fault testing in CMOS complex gates," in Proc. 1988 Int. Test Conf., pp. 688{694, Sept. 1988. [13] H. K. Lee and D. S. Ha, \SOPRANO: An ecient automatic test pattern generator for stuckopen faults in CMOS combinational circuits," in Proc. 27th Design Automation Conf., pp. 660{ 666, 1990. [14] H. Fujiwara and T. Shimono, \On the acceleration of test generation algorithm," IEEE Trans. on Comput., pp. 1137{1144, Dec. 1983. [15] F. Brglez and H. Fujiwara, \A neutral netlist of 10 combinational benchmark circuits and target

translator in FORTRAN," in International Symposium on Circuits and System, IEEE, pp. 663{ 698, June 1985. [16] T. Larrabee, \Ecient generation of patters using Boolean Dierence," in Proc. Int'l Test Conf., pp. 795{801, Oct. 1989. [17] B. T. Murray and J. P. Hayes, \Hierachical test generation using precomputed tests for modules," in IEEE Int'l Test Conf., pp. 221{229, 1988.