grammable cores) to make the pass/fail decision. Due to its over-sampling nature, the delta-sigma modulator can tolerate relatively high process variations and ...
Testing and Characterization of the One-Bit First-Order Delta-Sigma Modulator for On-Chip Analog Signal Analysis Jiun-Lang Huang and Kwang-Ting (Tim) Cheng Department of Electrical and Computer Engineering University of California, Santa Barbara
Abstract Delta-sigma modulation has become popular in modern analog-to-digital (AD) modulator design due to their relatively high immunity from process variations. In this paper, we propose efficient characterization techniques to obtain the key performance parameters of the 1-bit firstorder delta-sigma modulator which is intended to be used as an on-chip analog signal digitizer for Built-In Self-Test (BIST) applications. Numerical simulations have been performed to validate the techniques and the results indicate that accurate estimation of the parameters can be obtained at the presence of noise.
1 Introduction For mixed-signal systems that integrate both analog and digital functional blocks onto the same chip, testing the analog/mixed-signal parts has become the bottleneck during production testing. Because most analog/mixedsignal circuits are functionally tested, analog/mixedsignal testing needs expensive automatic test equipment (ATE) for analog stimulus generation and response acquisition. One promising solution to this problem is BIST which utilizes on-chip resources (which could be either shared with functional blocks or dedicated BIST circuitry) to perform on-chip stimulus generation and response acquisition. Under the BIST approach, the requirement on the external test equipment is less stringent. Furthermore, stimulus generation and response acquisition is more immune from environmental noise during the test process. With the advent of CMOS technology, DSP-based BIST becomes a viable solution for analog/mixed-signal systems as the required signal processing to make the pass/fail decision can be realized in the digital domain with digital resources. In DSP-based BIST schemes [1, 2], on-chip DA and AD converters are used for stimulus generation and response acquisition, and DSP resources (like CPU or DSP cores) are used for the required signal
synthesis and response analysis. The DSP-based BIST scheme is attractive because of its flexibility—various tests can be performed by modifying the software routines without altering the hardware. However, on-chip AD and DA converters are not always available in mixed-signal SOC devices. It is thus essential to investigate simple yet efficient on-chip stimulus generation and response acquisition techniques for occasions when AD or DA converter is not available. In [3], an on-chip waveform extraction approach is reported. Digitization of the analog waveform is accomplished by comparing the sampled data points to voltage references provided externally. Utilizing the undersampling technique, high sampling rate can be realized with relatively low-speed circuitry. However, a precise external reference voltage source is needed. In [4], the authors propose to use the 1-bit first-order delta-sigma modulator as a dedicated BIST circuitry for on-chip response acquisition and DSP techniques (realized by on-chip programmable cores) to make the pass/fail decision. Due to its over-sampling nature, the delta-sigma modulator can tolerate relatively high process variations and match inaccuracy without causing functional failure, and is therefore particularly suitable for VLSI implementation. This solution is suitable for low to medium frequency applications, e.g., audio signal. The main contribution of this work is the development of efficient techniques to characterize the key performance parameters of the 1-bit first-order delta-sigma modulator which is intended to be used as an on-chip analog waveform digitizer for BIST applications (as discussed in [4]). Characterization of the modulator is necessary prior to testing the CUT (circuit under test) because the measurement accuracy is affected by process variations incurred in the modulator. The obtained performance parameters allow one to calibrate the measurement results, and to estimate the achievable measurement accuracy. During the characterization process, linear ramps gen-
Programmable core + memory
Signal Generation DAC
filter
sel
Digital signal processing
vref
DeMUX
CUT1 CUT2
1-bit modulator
+ Analog comparator
To programmable core
Response acquisition
MUX
Figure 1. The BIST structure. erated using on-chip DAC or the technique in [6] are applied to the non-ideal modulator. The main advantage of both techniques is that the same setup can generate the linear ramps for characterizing the modulator and other desired test stimuli for testing the CUT, too. The output bit stream of the modulator is then analyzed with simple DSP operations like integration and running sum to derive the modulator’s performance parameters. To validate our ideas, we perform numerical simulation using different combinations of modulator parameters. The results show that close approximation of the modulator’s parameters can be obtained by reducing the slope of the linear ramps, which effectively enhances the test accuracy and makes the characterization techniques less sensitive to external noise. In Section 2, we introduce the BIST setup which is one of the target applications of the proposed characterization techniques, and briefly review the delta-sigma modulation principle. In Section 3, we illustrate the methods for characterizing the 1-bit first-order modulator. Simulation results are shown in Section 4. Lastly, we conclude this paper in Section 5.
2 Preliminaries In this section, we will first show a BIST setup that utilizes the 1-bit first-order modulator, and briefly review the delta-sigma modulation principle.
2.1 The BIST structure In [4], the authors propose to use a 1-bit first-order delta-sigma modulator as a dedicated BIST circuitry for digitizing the analog CUT output responses when no onchip ADC is available. Shown in Fig. 1, the BIST structure consists of the following blocks: Programmable core + memory. The programmable core, such as a processor or DSP core which is usually available in an SOC device, is responsible for (1) converting the numerical representation of the desired test stimuli (including those for the CUT and the 1-bit firstorder delta-sigma modulator) into digital forms, and (2)
response analysis to make the pass/fail decision. When on-chip resources are insufficient for the needed DSP operations, external PC-based test equipment can be used instead. Signal Generation. This part of the BIST structure converts digitized waveforms into analog signals. On-chip DAC, if available, can be employed for the DA conversion. Otherwise, one can employ the technique in [6], which introduces hardware overhead of a 1-bit DA converter and low-pass filter. In this technique, the desired periodic band-limited analog signal (in its numerical representation) is converted into digital streams by a software delta-sigma modulator. A portion of the output of the software modulator, which is in general an integer number of signal periods, is extracted and stored in on-chip memory. To generate the actual signal, the stored digitized waveform is periodically applied to the 1-bit DA converter followed by a low-pass filter. This technique is favorable because the same setup can be reused to generate various band-limited signals without hardware modification. Analog Comparator. The analog comparator together with external voltage reference allows one to decide the DC offset and slope of the generated linear ramps. Since a linear ramp can be quantified with two measurements, only two reference voltage values are needed. We will give more details on this later. 1-bit ∆Σ modulator. The 1-bit first-order delta-sigma modulator converts the analog responses to 1-bit digital streams, and this work mainly discusses efficient ways to characterize it. MUX/DeMUX. “MUX” and “DeMUX” are switches that control the signal flow during the test mode. Notice that there is a bypass path for testing the BIST structure.
2.2 The 1-bit first-order delta-sigma modulator Over-sampling delta-sigma modulation has gained increasing popularity since it was introduced. Modulators based on this principle convert an analog input to a lowresolution digital representation at a very high sampling rate. AD converters based on this principle are particu-
Integrator
xi
+
ei
ui +1
-
Integrator
Quantization
ui
Delay
xi
Q
+
g
ui +1
-
Delay
Quantization
ui
Q'
p
Figure 2. The first-order ∆Σ modulator.
Figure 3. The non-ideal modulator.
larly suited to VLSI implementation—the analog circuitry required is simple and performance is robust against circuit imperfection and component matching inaccuracy. In this work, we are interested in the 1-bit firstorder configuration. Its sampled-data equivalent circuit is shown in Fig. 2, and can be described by the difference equations u i = e i ;1 + u i ;1 (1) ei = xi ; Q (ui )
and low-pass filters [5], or perform Fourier transform to derive the frequency spectrum. It is interesting to note that discrete Fourier transform on the one-bit stream can be realized without multiplication as the modulator only has two output levels.
where xi is the discrete time sample of the modulator input at sampling rate f s , and ui is the state of the integrator. The two-level quantizer Q can be described by
Q(ui ) =
ui 0 ui < 0
+1;
;1
;
(2)
Note that here the quantizer output levels are set to be 1 and symbolically represented by 1/0. The case of quantizer output ∆ is simply a scale change. One feature that distinguishes the delta-sigma modulation from traditional Nyquist conversion techniques is noise shaping which reduces the modulation noise at low frequencies but increases it at the high frequencies. This is accomplished by the feedback from the quantizer Q and effectively forces the average value of the quantized signal to track the average input. 2.2.1 Signal analysis Once the analog signal of interest is converted into one-bit digital stream, DSP techniques can be applied to derive the desired signal characteristics. For DC input signal v, its value can be estimated by averaging N samples of the quantizer output: vˆ =
∑i=1N Q (ui ) N
(3)
and the error is bounded by [7]
jv ; vˆj 2
=
N
(4)
which implies that the desired accuracy can be achieved by increasing N. For AC input signal, one can reconstruct the original waveform by a digital decoder consisting of decimators
2.2.2 The non-ideal modulator The integrator and the quantizer in the modulator are not ideal in practice. The model of a first-order system with imperfect integrator and quantizer is shown in Fig. 3 ([8, 9]). The non-ideal integrator is represented by ;
ui = pui;1 + g xi;1 ; Q0 (ui;1 )
(5)
where p < 1 represents the finite op-amp gain effect, and component mismatch causes g to differ from 1. The imperfect quantizer Q 0 is described by Q 0 (u i ) =
a; ui t b; u i < t
(6)
where t represents the threshold and a, b the output levels of Q0 . In the rest of this paper, we describe a systematic procedure to characterize the erroneous behavior of an imperfect modulator caused by the deviations of ( p; g; t ; a; b) from their ideal values in the context of BIST applications. Quantitative analysis on the behavior of the non-ideal modulator with DC input can be found in [8, 9]. Fig. 4 shows part of the DC I/O transfer curve of a non-ideal modulator with the following parameters: ( p; g; t ; a; b) = (0:9; 0:99; 0:01; 1:01; ;0:97). (The straight line corresponds to the ideal transfer curve.) The error between the input and the average output can be decomposed into three components—the DC offset, the divergence from unity gain, and the non-zero step width. The first two sources of error can be removed (or compensated) by introducing a gain, and DC offset to the decoder. No decoder, however, could remove the error due to non-zero step width, which is a highly non-linear function of the input. The non-zero step width is caused by the limit cycles. For an ideal modulator, its output bit stream with respect to a rational DC input value is a series of repetitive patterns. The base patterns are called the limit cycle. For
0.2
simple DSP techniques like integration and running sum to find the DC offset, gain, and the leak factor (p) of the non-ideal modulator. In the following, we will first introduce the characterization techniques assuming that the values of the linear ramps at any time are known or can be measured. Then, we will show how the linear ramps are generated and how to decide their values at the time point of interest. At the end, we will discuss the possible sources of errors.
0.15
0.1
output
0.05
0
-0.05
-0.1
-0.15
-0.2 -0.2
-0.15
-0.1
-0.05
0 input
0.05
0.1
0.15
0.2
Figure 4. Non-ideal DC I/O transfer curve. example, the outputs of an ideal modulator with respect to DC input 0 and 1=3 are: input input
= =
0 output 1=3 output
= =
01010101 011011011
where the corresponding limit cycle patterns are 01 and 011, respectively. For non-ideal modulators, it’s proven in [8] that each limit cycle that can appear at the output of the ideal modulator can appear at the output of a leaky system (p < 1) as well. The difference is that each limit cycle persists over a range of inputs in the non-ideal case, which appears in the non-ideal I/O transfer curve (Fig. 4) as non-zero width steps. For ease of description in the latter analysis, let’s define the input range of the limit cycle X of a non-ideal modulator M as the DC input range such that M will produce a series of pattern X. One can see from Fig. 4 that the input range of the 01 limit cycle is [;0:003; 0:007] within which the corresponding output is 0.
3 Characterizing the modulator When characterizing an imperfect modulator, we intend to find its DC offset, gain (the slope of the linearized non-ideal DC I/O transfer curve), and the leak factor p (Fig. 3). While the obtained DC offset and gain allow one to calibrate the measurements in the decoding stage, the leak factor p and the DC offset together enable one to derive the DC I/O transfer curve of the non-ideal modulator, which characterizes the non-ideal modulator’s behavior better than the differential/integral non-linearity (DNL/INL) does. Furthermore, the value of leak factor p, which leads to the non-linearity, can be used for diagnostic purpose. Since the delta-sigma modulator has a high sampling rate, one can approximate its DC I/O transfer curve with the I/O curve obtained by applying to its input with rising/falling linear ramps that have relatively low slopes. In this work, we use linear ramps as the test stimuli and
3.1 The DC offset Based on the analysis in [8, 9], the non-ideal I/O transfer curve is symmetric to the DC input value v 0 : v 0 = (1 ; p )
t a+b + g 2
(7)
This suggests that the integration of the non-ideal I/O transfer curve from DC input (v 0 ; v) to (v0 + v) is equal to zero. Accordingly, if one integrates the output of the non-ideal modulator with respect to a ramp input over a period when the ramp input varies from (v 0 ; v) to (v0 + v), the result will be zero. Thus, v 0 can be decided in the following way: 1. Apply a linear ramp to the modulator, and start an integration process (using the programmable core) over the modulator’s output when the value of the linear ramp reaches some pre-determined level, say v 1 . Since the modulator only has two output levels, the integration can be realized with an up/down counting process. 2. Record the value of the linear ramp, v 2 , when the result of the integration is zero again. 3. v0 can then be calculated by v 0 = (v1 + v2 ) =2. Although it is preferred to have v 1 close to 1 (to increase the duration of integration), we have to be careful not to make the corresponding v 2 beyond 1. Once the modulator gain m is derived (see next section), the DC offset is then ;mv0 . Two major sources that contribute to the inaccuracy of v0 are (1) the inherent finite resolution of the proposed procedure, and (2) noise. Since the delta-sigma modulator is a sampled-data system, v 1 and v2 are limited to sampled values, which leads to the finite resolution. In the above procedure, v 1 is the ramp value when we start the integration process and can be considered as correct. v 2 , however, may deviate from its expected value ; (2v 0 ; v1 ) because it must be a sampled value. Let r sec;1 be the slope of the linear ramp, and f s the sampling rate of the modulator. The maximum error of v 2 is jr= fs j which is the voltage increase/decrease per sampling period. Thus, the maximum error of v 0 due to this finite resolution is
range of the 01 limit cycle introduces no more information beyond v 0 , which has been derived in Section 3.1, for computing p.) To reduce the inaccuracy of p caused by the errors associated with the obtained input range, the limit cycle’s input range should be as large as possible. Thus, the 011 limit cycle is chosen since its input range is the second largest (exceeded only by the 01 limit cycle). + In addition to Eq. 7, v ; 011 and v011 , the lower and upper bounds of the 011 limit cycle’s input range, are given by [8, 9]:
output
ideal
non-ideal
A1 A2 v0
v v0+v
input
Figure 5. Gain estimation.
jr
2 fs )j. Clearly, this error can be effectively reduced by decreasing jrj. Note that even though increasing f s has the same effect, it’s preferred to characterize the modulator at its designed sampling rate.
v;
011 =
=(
3.2 The modulator gain In Fig. 5, the I/O curves of the ideal and the non-ideal modulator are plotted (the non-linear effect is not shown here for simplicity), and A 1 , A2 are the areas under the ideal curve from 0 to v and the non-ideal curve from v 0 to (v0 + v). The gain of the non-ideal modulator can then be approximated by the ratio of A 2 to A1 (assuming that the ideal modulator has unity gain). Assume that the slope of the linear ramp is r (sec ;1 ), and the sampling rate of the modulator is f s . The number of samples within the linear ramp period [0; v] is then jv fs =rj. Since the ideal modulator’s average output tracks its average input, S, the sum of its outputs in the [0; v] period (obtained with an integration process) will satisfy the equation: v S (8) = v fs = jrj 2 To derive m, the gain of the non-ideal modulator, one computes the sum S 0 of the non-ideal modulator’s output during the [v0 ; v0 + v] period. m can then be estimated by m=
S0 S
=S
0 2 jrj v2 f s
(9)
The sources of inaccuracies are similar to those described in the previous section. Note that it’s desirable to choose v such that (v 0 + v) does not fall in any major non-zero width steps in the non-ideal transfer curve: Consider the extreme case when (v 0 + v) is within the 01 limit cycle’s input range. Since the 01 limit cycle corresponds to zero average output, the resulting S 0 and accordingly m will be close to zero!
3.3 The integrator leak For the purpose of estimating p, we need to identify the input range of a limit cycle other than 01. (The input
and v+ 011 =
a;b 2
a;b 2
2 p
; p + 1 + v
p2 + p + 1
; p2 + p + 1 + v p2 + p + 1
(10)
0
0
(11)
respectively. We have shown how v 0 can be obtained in + Section 3.1. Once v ; 011 and v011 are known, p can be found by solving the following equation ;
2 v; ; v0 p ; p + 1 ; ; ; 011+ v011 + v011 ; 2v0 2
=0
(12)
Among the two solutions, one is greater and the other less than 0.5. In practice, p is close to 1, and the one greater than 0.5 is taken. Note that one does not have to solve Eq. 12 explicitly. Instead, one can compare the obtained + v; 011 and v011 to the pre-computed acceptable ranges (with respect to the desired test accuracy) to make the pass/fail decision. To find the input range of the 011 limit cycle, we apply a linear ramp to the modulator and compute the running sum S (n) (with window width N) of the modulator output stream. ; (13) S (n) = ∑ sign Q0 (ui ) i=nn+N ;1
where we use the “sign” operation because as seen by the running sum process, the quantizer’s outputs are 1, not a=b. Within the 011 limit cycle’s input range, the expected value of S (n) is N =3, and we approximate the input range with the period of the linear ramp when S (n) stays stable at N =3. The two main criteria for choosing N, the width of the running sum window, are:
N should be an integer multiples of 3 (length of the 011 pattern) to avoid rounding error. N must be smaller than the number of samples taken by the modulator when the ramp value is within the input range of the 011 limit cycle.
DC
vhigh
integrator state
v vlow
T0
Tlow
T
Thigh
ramp
1.5
1.5
1
1
0.5
0.5
0
0
time -0.5
-0.5
Figure 6. Quantifying the linear ramps. 10
Note that when N is increased, the output resolution of S (n) also increases. For example, the possible outcomes of the running sum S (n) with N = 3 and N = 6 are f;3; ;1; 1; 3g (4 levels only) and f6; 4; 2; 0; ;2; ;4; ;6g (7 levels), respectively. Therefore, without violating the two constraints, it is preferred to use a larger N because the better resolution in amplitude will make locating the limit cycle’s input range easier.
3.4 Deriving the I/O transfer curve Once v0 and m are derived, the modulator’s output can be calibrated using the following equation y=
x ; vo m
(14)
where x and y denote the measured and calibrated values, respectively. The integrator leak factor p and v 0 can be used to derive the input ranges for all the limit cycles (see [8, 9] for details), from which the I/O transfer curve can be constructed. The derived input ranges represent the part of measurement errors that cannot be removed, and limit the achievable test accuracy.
3.5 Quantifying the linear ramps When the linear rising/falling ramps are generated onchip, their DC offset and slope are affected by the process deviations incurred in the “Signal Generation” circuitry and can differ from the desired values. Thus, it is necessary to quantify the ramps’ DC offset and slope in advance. To quantify a linear rising ramp (the same technique can be applied to the falling ramp), we use the “Analog Comparator” (in Fig. 1) to determine the time Tlow and Thigh when the ramp’s value reaches v low and vhigh , respectively. This is illustrated in Fig. 6. Notice that
Both Tlow and Thigh are represented in terms of clock indices relative to T0 when the memory outputs the first pattern it stores. The systematic delay caused by the DAC and filter does not affect the following analysis. To compensate for the offset voltage of the analog comparator, one can introduce auto-zero circuitry,
20 30 time
40
10
(a) DC input
20 30 time
40
(b) ramp input
Figure 7. The state of the integrator with respect to DC and ramp inputs.
or take the average of two measurements made by swapping the inputs to the comparator. In the BIST structure, the two references v low and vhigh are from external reference source. Once Tlow and Thigh are known, the value v of the linear ramp at time T or the time T when the ramp’s value is v can be obtained by solving v ; vlow vhigh ; vlow
=
T ; Tlow Thigh ; Tlow
(15)
3.6 The modulator behavior with ramp input In this section, we discuss the errors of the estimated v 0 and m caused by approximating the DC I/O transfer curve of a non-ideal modulator with the I/O transfer curve obtained by applying linear ramps. We will illustrate that if we repeat the characterization procedures twice (one using a rising ramp and the other using a falling ramp) and then take the average of the results, the errors will be substantially reduced. Let’s first take a closer look at the behavior of the nonideal modulator with DC input v. When v is within the 011 limit cycle’s input range, the modulator will generate periodic output patterns 011, which corresponds to DC output value of 1=3. Furthermore, the corresponding integrator state is also periodic. This is shown in Fig. 7(a) where the DC input value is within the 011 limit cycle’s input range. Now, consider the case when a linear rising ramp is applied to the modulator. When the ramp’s value is within the 011 limit cycle’s input range, the integrator state, as shown in Fig. 7(b), is close to periodic with length 3 except that it has a global rising trend due to the rising input value. Eventually, the lowest state will be greater than 0, which results in an extra output of 1! In the case of the falling ramp, the integrator’s state will have a global falling trend, and there will be an extra 0. Assume that we use the rising ramp and start the integration process at v 1 < 0 when characterizing v 0 . Since the
tv10
realistic
tv0
tv2
(a)
(b)
tv
