The Implementation of a Low-Power Biomedical Signal ... - IEEE Xplore

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, VOL. 1, NO. 4, DECEMBER 2011

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The Implementation of a Low-Power Biomedical Signal Processor for Real-Time Epileptic Seizure Detection on Absence Animal Models Tsan-Jieh Chen, Herming Chiueh, Member, IEEE, Sheng-Fu Liang, Member, IEEE, Shun-Ting Chang, Chi Jeng, Yu-Cheng Hsu, and Tzu-Chieh Chien

Abstract—Epilepsy is one of the most common neurological disorders, with a worldwide prevalence of approximately 1%. A considerable portion of epilepsy patients cannot be treated sufficiently by today’s available therapies. Implantable closed-loop neurostimulation is an innovative and effective method for seizure control. A real-time seizure detector is the kernel of a closed-loop seizure controller. In this paper, a low-power biomedical signal processor based on reduced instruction set computer (RISC) architecture for real-time seizure detection is implemented to achieve low-power consumption and perform continuous and real-time processing. The low-power processor is implemented in a 0.18 m complementary–metal–oxide semiconductor technology to verify functionality and capability. The measurement results show the implemented processor can reduce over 90% power consumption compared with our previous prototype, which was implemented on an enhanced 8051 microprocessor. This seizure detector was applied to the continuous EEG signals of four Long–Evans rats with spontaneous absence seizures. It also processed 24 h long-term and uninterrupted EEG sequence. The developed seizure detector can be applied for online seizure monitoring and integrated with an electrical stimulator to perform a closed-loop seizure controller in the future. Index Terms—Electroencephalogram (EEG), epilepsy, reduced instruction set computer (RISC), seizure detection.

I. INTRODUCTION

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PILEPSY is one of the most common neurological disorders, in which around 1% of the people in the world are affected. Around one-third of the patients’ conditions cannot be controlled with today’s available antiepileptic drugs, but half of those may benefit from epilepsy surgery [1]. Unfortunately, 25% of the epilepsy patients cannot be treated sufficiently by any available therapy [2]. If seizures cannot be well controlled, Manuscript received June 23, 2011; revised October 12, 2011; accepted October 16, 2011. Date of publication November 15, 2011; date of current version February 01, 2012. This work was supported in part by the National Chip Implementation Center, Taiwan, National Science Council, Taiwan under Contract NSC 100-2220-E-009-018 and Contract NSC 100-2220-E-009-020 and in part by the MoE ATU Program of National Chiao Tung University, Taiwan. This work was recommended by Guest Editor M. Sawan. T.-J. Chen, H. Chiueh, S.-T. Chang, and C. Jeng are with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: [email protected]). S.-F. Liang, Y.-C Hsu, and Tzu-Chieh Chien are with the Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan 701, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JETCAS.2011.2174472

the patients experience major limitations in family, social, educational, and vocational activities. Recently, alternative techniques, such as the vagus nerve stimulation or deep brain stimulation [1], [2], have been proposed. Instead of an open-loop seizure controller, a real-time, closed-loop device is more capable for seizure control [2]–[4]. One essential technique required for the development of such a system is a robust online seizure detection method that can drive an antiepileptic device to suppress the seizure as early as possible when a seizure occurs. Recent research has proposed the implementation of hardware prototypes [5]–[11] and biomedical signal processors (BSPs) [12], [13] for epileptic seizure detection. Among these works, spectral analysis, wavelet analysis, and support vector machine technology are used to detect the seizure signals, and the response time for seizure detection is average greater than 8 s or often not mentioned. Several closed-loop seizure control systems relied on analog circuitries extracting seizure features [7]–[9], [14] to sustain high epileptic seizure detection accuracy. Some seizure detection algorithms [15]–[17] have been proposed to rely on powerful processing platform to keep short response time and high detection accuracy. Among most of the studies, the discontinuous EEG data fragment is often used to validate detection algorithm; however, it is insufficient to validate the robustness of detection algorithm. The seizure detection algorithm used in this work implied entropy coding and spectral analysis, which contain large portion of digital processing, to responsively detect the seizure EEG signals and keeps the highly successful detection rate. However, implementation [20] based on 8051-like micro controller [22] consumes more than 117 mW to achieve the real-time response. Therefore, in this study, a RISC-like processor to detect and suppress epileptic seizure based on proposed algorithm is implemented. The simplicity, flexibility, and fixed instruction format of RISC [21] provides implementation feasibility for high processing performance. A more complicate architecture that provides sufficient hardware performance is used for real-time seizure detection algorithm. However, a slower clock rate is provided to reduce the power and energy consumptions of the proposed system. The measurement results verified the proposed methodology by providing 90% power reduction compare with previous microcontroller implementation. Thus, the continuous EEG signals acquired from freely moving Long–Evans rats under spontaneous spike-wave discharges (SWDs) are recorded and running on the proposed biomedical

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signal processor. The results show the designed hardware is robustly processing 24 h long-term and uninterrupted EEG sequence. The development of proposed processor provides a platform to integrated analog front-end circuitries and other algorithm to provide a low-power system-on-a-chip design for neural prosthesis applications. The rest of this paper is organized as following: Section II describes the preparation of animal models used in this work. In Section III, the system architecture of proposed biomedical signal processor is described. Section IV demonstrates the epileptic seizure detection algorithm. Section V describes the design and implementation. In Section VI, the evaluation procedure and measurement results are presented. And the conclusion is followed. II. GENERAL ANIMAL PREPARATION Adult Long–Evans rats with spontaneous spike-and-wave discharges (SWDs) were used in the study. The genetic defect of Long–Evans rats causes spontaneous SWD. Unlike pentylenetetrazole (PTZ)-induced SWD, the EEG characteristic of spontaneous SWD is much more close to epileptic patients’ EEG in the clinical aspect. The animals were kept in a room under a 12:12-h light-dark cycle with food and water provided ad libitum. All surgical and experimental procedures were reviewed and approved by the Institutional Animal Care and Use Committee of the National Cheng Kung University. The rats were anesthetized with sodium pentobarbital (50 mg/kg, i.p.). Subsequently, it was placed in a standard stereotaxic apparatus. Screw electrodes were bilaterally implanted over the area of the frontal barrel cortex (anterior 2.0 mm, lateral 2.0 mm with regard to the bregma). A four-microwire bundle, each made of Teflon-insulated stainless steel microwires (#7079, A-M Systems), was used to stimulate the right-side zona incerta (ZI) (posterior 4.0 mm, lateral 2.5 mm, and depth 6.7–7.2 mm). A ground electrode was implanted 2 mm caudal to the lambda. Dental cement was applied to fasten the connection socket to the surface of the skull. Following suturing to complete the surgery, animals were given antibiotics and housed individually in cages for recovery. Two weeks after the surgery, each animal was placed in the recording environment at least two times (1 h/day) prior to testing to allow rats to habituate to the experimental apparatus. In this procedure, about 90% of Long–Evans rats show spontaneous SWDs, which were used for continuous EEG recording. Continuous EEGs from 5–24 h (contained one circadian cycle) were recorded and analyzed to assess our seizure detector in this study. III. SYSTEM ARCHITECTURE The closed-loop seizure control system consists of three modules: 1) an analog front end (AFE), 2) a biomedical signal processor (BSP), and 3) a stimulator. The seizure detection involves EEG data acquisition through an analog front end and digital signal processing on a BSP. Fig. 1 demonstrates the functional block diagram of the closed-loop epileptic seizure control system. The implemented algorithm is described in Section IV and firmware is described in Section V.

Fig. 1. Closed-loop epileptic seizure control system.

In this study, the seizure detection scheme is based on large portion of digital signal processing. Several technology can provide high digital processing capability, such as field-programmable gate array (FPGA), DSP, application-specific integrated circuit (ASIC), and RISC processor. Modern high-density FPGA can incorporate embedded processor and custom hardware accelerator to achieve very high performance; however, it consumes high static power (tens of milliwatts to hundreds of milliwatts) because of its advanced fabrication technology. ASIC is an integrated circuit which is highly specialized for a particular scenario or application. This solution is highly optimized in terms of area, power, and speed to perform its designated task but it is lack of flexibility. DSPs also have high processing capability but the large portion of power is consumed by other dedicated hardware accelerators, which is not required in our algorithm; therefore, general purpose processors are chosen in this research. In our previous implementation, a seizure controller [20] has been implemented with an enhanced 8051 microcontroller in freely moving rats. The closed-loop seizure controller was carried by each experimental subject, and a host computer for remote real-time monitoring of spontaneous brain activities, while they were communicated based on a wireless ZigBee protocol. The seizure controller consisted of signal conditioning, microcontroller, and the stimulator. The EEG signals were amplified and band-pass filtered by the signal conditioning block. Based on a single-channel, 200-Hz sampling rate, and 10-bit ADC resolution, the microcontroller and the signal conditioning circuit consumed 117.66 mW. The power consumption of such implementation is significant for implantable devices. However, modern 32-bit RISC processor has delivered better energy efficiency over the traditional 8-bit microcontrollers. Thus, a powerful 32-bit processor, OpenRISC 1200 (OR1200) [32], is modified and implemented for low-power epileptic seizure detection. It provides over one dhrystone 2.1 MIPS (DMIPS) per MHz and one DSP MAC 32 32 operations per MHz, which is 10 times faster than an enhanced 8051 microprocessor (about 0.1 DMIPS/MHz [33], [34]). For the biomedical application where low-power and low-energy operation is the major concern, the energy efficiency for a specific task is more important. Our experimental results show the energy per seizure event determination is about 1.15 mJ for OpenRISC and 18.8 mJ for enhanced 8051 microprocessor. The detail evaluation results are described in Section VI. The energy efficiency and flexibility enable OpenRISC to be used in not only epileptic seizure detection but the most biomedical application.

CHEN et al.: THE IMPLEMENTATION OF A LOW-POWER BIOMEDICAL SIGNAL PROCESSOR FOR REAL-TIME EPILEPTIC SEIZURE DETECTION

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Fig. 2. EEG examples during the wakefulness (WK), spike-wave discharge (SWD), slow-wave sleep (SWS), and movement artifact. Fig. 3. Identification of effective spectral indexes for seizure detection using correlations analysis between seizure event and a specific frequency band of spontaneous brain waves.

IV. EPILEPTIC SEIZURE DETECTION ALGORITHM This session will describe the algorithm [18], [19]. In order to achieve accurate online seizure detection, EEG data corresponding to various behavioral states were utilized for feature extraction and classifier training. Fig. 2 shows an example of EEG patterns corresponding to various behavioral states, including wakefulness (WK), SWD, slow-wave sleep (SWS), and movement artifact in a continuous recording of a Long–Evans rat. The time-domain and frequency-domain characteristics of EEG signals were integrated as the features and the linear least square model was utilized [23]–[26] to reduce the computational cost of seizure classifier implemented on portable systems. A. Data for Analysis and Training Two essential stages of EEG signal processing were performed in Long–Evans rats in this study. In the first stage, continuous EEG signals of each rat were recorded for feature extraction corresponding to seizures (SWD) and non-seizures (including WK, SWS, and artifact). These spontaneous events were used to train the seizure classifier program offline. While the parameters of a seizure detection model were determined, the parameters were downloaded to our processor to perform online seizure detection for the testing data. B. Feature Extraction Complexity analysis such as entropy can work well on distinguishing from EEG signals during wakefulness and seizures [27]. The frequency bands whose power changes are highly correlated with SWDs can perform as the complementary features of entropy to reduce false detections during SWS or the movements. 1) Complexity Analysis: Approximate entropy (ApEn), a measure that quantifies the regularity or predictability of a time series of signals [27], was utilized to analyze the complexity of EEG signals due to the fact that periodic signal components of seizures reduced complexity levels. In addition, to reduce the computational cost, the logarithmic likelihood calculation was simplified as

(1)

was the conditional probability [27] and in where our method [18], [19]. The complexity measurement, CM, was calculated by (2) 2) Spectral Analysis: EEG spectral analysis based on short-term Fourier transform shows that the absence seizure has large power at 7–9 Hz and the second harmonics (14–18 Hz). SWS state contains delta rhythms as well as some oscillations in higher frequencies. Grooming has large amplitude at low and some high frequency bands. Therefore, EEG band powers were combined to ApEn analysis to improve the performance of epileptic seizure detection [28]–[30]. The fast Fourier transform (FFT) was used to calculate powers of specific frequency bands of spontaneous brain waves because of its well-established implementation in various microprocessors. To determine spectral indexes for adequately extracting an SWD feature, seizure event (denominated as “1”) was correlated with powers of several specific frequency bands using the person correlation coefficient. Powers in two frequency bands that displayed highest correlations with SWDs were selected as spectral indexes. Fig. 3 depicts the mechanism of identification of effective spectral indexes for seizure detection using correlation analysis between seizure event and a specific frequency band. C. Classifier Three feature indexes (CM and powers of two specific frequency bands) were input into a classifier to verify seizure occurrences. In order to implement the proposed seizure detection method on an embedded system, a linear classifier called linear least squares (LLS) [31] was utilized. The LLS method finds a best fitting linear model that minimizes the mean square error between the system output and the desired output. Mathematically, it can be stated as finding an approximate solution to an overdetermined system of linear equations. Because the model output is only the weighted sum of the input features, it is suitable for implementation using processors without high computing power or for use in online processing. The th output

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Fig. 4. The block diagrams of (a) OR1200 processor and (b) the implemented low-power BSP.

of the LLS, as

, is the linear combination of the th feature vector

(3)

Fig. 5. The (a) chip layout and (b) die photo of the implemented low-power BSP.

TABLE I SUMMARY OF THE PROPOSED LOW-POWER BSP

is the where is the dimension of the feature vector and weight parameter corresponding to the th feature element. The can be determined by the following optimal weight vector matrix calculation: (4) where is the desired output vector. In this study, the target value was 0 for non-seizure segments, and 1 for seizure segments. The optimal parameters of the classifier were determined for each rat through an offline process and the parameters were downloaded to our BSP to perform online seizure detection experiments. V. DESIGN AND IMPLEMENTATION This session will present the design and implementation of the proposed low-power BSP, including hardware architecture and firmware. A. The Low-Power Biomedical Signal Processor Implementation The low-power BSP for epileptic seizure control is implemented based on the OR1200. OR1200 is a 32-bit scalar RISC with Harvard micro-architecture, five stage integer pipeline, virtual memory support (MMU), and basic DSP capabilities. Supplemental facilities include debug unit for real-time debugging, high resolution tick timer, programmable interrupt controller, and power management support. OR1200 is intended for embedded, portable, and networking applications. Fig. 4(a) shows the block diagrams of OR1200. Because the area is proportional with power consumption, the unnecessary interface and modules are removed to optimize power consumption. Some modules including the memory management units and the caches are removed. The external interfaces of the power management, debug module and interrupt controller are also removed. Furthermore, the instruction and data bus are controlled by an arbiter. Instruction bus has the highest bus access priority. Although the data bandwidth will be reduced if instruction and data bus are merged, the purpose

is to trade off power against execution time. Fig. 4(b) shows the block diagrams of the implemented low-power BSP for epileptic seizure control. The proposed BSP is implemented using cell-based design flow by TSMC 0.18 m complementary–metal–oxide semiconductor 1P6M process and ARM design kit. The chip layout and die photo are shown in Fig. 5. A total of 104 pads are utilized in this work, which are 71 input/output pads and 33 power pads. The core area is 1.0 1.0 mm and the chip area is 1.75 1.75 mm . The maximum operating clock rate is 110.0 MHz at 1.8 V core supply and 3.3 V input/output (I/O) pads supply. The power consumption of core and I/O pads is 0.23 mW/MHz and 0.26 mW/MHz, respectively. One vertical and two horizontal power strips are distributed on the core to reduce voltage drop. The summary of circuit characteristics is listed in Table I. B. Firmware Implementation The firmware on the low-power BSP performs the following: 1) the EEG data acquisition; 2) seizure detection; 3) stimulation pulse generation. Fig. 6 shows the flowchart of the main program including feature-related computation and two interrupt service routines (ISRs) for timers. 1) Data Acquisition: Data acquisition stage loads the digitized 8-bit EEG signals from SRAM on evaluation board for feature extraction. The acquisition rate is 200 Hz. ISR1 is configured as 5-ms period for the data acquisition. 2) Seizure Detection: After every 32 sampled data are buffered, they are used for digital signal processing (DSP) computation to calculate time-domain CM and frequency


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Fig. 6. Flowchart of data acquisition, stimulation, and seizure feature extraction.

domain FFT, and then classify the seizure states. In order not to interfere with the precise sampling time, the DSP computation is performed in the background with lower priority. The CM is and values are updated calculated based on (2) after the for the first sampled data. The FFT is accomplished by applying a fixed-radix FFT algorithm, radix-4. The seizure detection counter is incremented if a seizure occurrence is determined by the LLS calculation; otherwise, the counter is cleared. When the counter reaches “3,” the flag for the seizure suppression is set, and then generate stimulation pulses in ISR2. 3) Stimulation Pulse Generation: When classifier determines a seizure occurrence, the processor starts tick timer to generate 800-Hz, 40% duty cycle pulses for 0.5 s. ISR2 is set to a lower interrupt priority than ISR1, so the sampling time of EEG signal is guaranteed. By combining above low-power processor core, firmware implementation, the implementation of BSP for seizure detector is completed. In the following session, the evaluation based on our absent animal models is discussed.

Fig. 7. Experiment setup. (a) Functional block diagram and (b) the testing board of the proposed low-power BSP with FPGA-based evaluation platform.

VI. EVALUATION In order to verify the functionality and evaluate real-time performance of the implemented low-power BSP, a prototype system was implemented. Fig. 7(a) demonstrates the functional block diagrams of the experiment setup. In the prototype system, the implemented processor was connected with host computer via DE-2 70 FPGA-based evaluation board. The host computer was utilized for offline classifier training and Long Evan’s EEG signals source. The evaluation board plays a role of a debugger of the processor, which is able to upload instructions, start processor, halt processor, and download results, etc. The EEG dataset and the instructions of processor were stored in the 2 MB memory. The power of the processor was supplied by the Keithly 2400 digital source meter, which provided 100-nA resolution under 10-mA measurement range [35]. After the system started up, the host computer uploaded codes and EEG dataset into evaluation board and then enabled processor. The processor accessed EEG dataset and performed seizure detection algorithm continuously. As long as the EEG dataset was finished execution, the detection and suppression results were downloaded into the host computer for functional verification.

Fig. 8. Timing diagram of the seizure detection firmware.

A. Real-Time Seizure Detection Fig. 8 presents the timing diagram of the tasks used for seizure detection. The low-power BSP operated at 13.6 MHz clock rate for real-time seizure detection although the operating clock rate could be 110 MHz. The execution time was obtained by ticking timer at the start and the end of each task and then downloaded to host computer. When 32 sampled data is retrieved, the and parameters for CM computation are updated. The computation of CM, FFT, and LLS classification is finished in next

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Fig. 9. EEG signals and the detected seizure events by our low-power BSP. (a) SWD under WK state, (b) SWD under SWS state, (c) false detection under SWS state. Lower panels shown in (a)–(c) are seizure detection event.

32-sample cycle and then determine the seizure event. Though the DSP computation spans several sampling periods, sampled data collection performed with higher priority is not interfered. As shown in the figure, each time when 32 sampled data have been collected, about 38.8 ms latency is required to determine the seizure occurrence. The total computation time is 159.35 ms, which is less than a 32-sample cycle (160 ms). The timing diagram shows the seizure detection algorithm can be executed continuously in the implemented processor. To optimize power consumption, the assembly has been rescheduled to reduce data hazard and branch hazard [36], which results in slowing down operation frequency. A seizure occurrence is determined by three 32-sample cycles along with DSP computation duration (about five sampling periods) after the seizure onset; so, theoretically, it takes about 0.5 s to start the seizure suppression. When considering one 32-sample cycle for tolerance and the computation time (159.35 ms), the range of seizure determination delay is from 0.6–0.8 s. Fig. 9 presents the EEG signals with either accurate or false seizure detection. It shows that the seizure is detected in about 0.5–0.8 s after the seizure onset. B. Seizure Detection Accuracy Performance of the seizure detection algorithm applied on four adult male Long–Evans rats was assessed. All four rats were subjected to absence seizures. The training procedure described in Section III-A was executed in each individual rat, and

TABLE II OBSERVED SWD DURATION AND TWO SELECTED FREQUENCY BANDS

the parameters of a training model were then used for seizure detection. To evaluate the effectiveness of the algorithm, two rats were measured under a 5 h execution of the system; whereas the other two rat was measured under 24 h execution of the system to verify robustness. Table II shows the observed SWD duration, and the two selected frequency bands for each rat. Table III shows the results of the hybrid seizure detection algorithm. As shown in the table, the seizure detection accuracy is above 92%, demonstrating the functionality of the implemented processor and the effectiveness of the algorithm. The robustness of the algorithm was also verified by 24 h execution of the continuous absence rat’s EEG signals. The function of the seizure detection algorithm is demonstrated in Fig. 9. The SWD signals of subject #1 under WK state and its detection event are shown in Fig. 9(a). Fig. 9(b) shows a similar result for an absence seizure on subject #1 under SWS state. Fig. 9(c) shows a false detection happened on subject


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Fig. 10. EEG containing multiple absence seizure SWDs and detected seizure events by our low-power BSP.

TABLE III ACCURACY AND FALSE DETECTION OF THE EPILEPTIC SEIZURE DETECTION ALGORITHM

TABLE IV COMPARISON OF EPILEPTIC SEIZURE DETECTORS

C. Power Consumption Comparison The implemented processor operated at 13.6 MHz clock rate and consumed 6.66 mW for real-time seizure detection algorithm computation. The core and I/O power were 3.128 mW and 3.536 mW, respectively. The total power consumption including our low-noise preamplifier, filter [37], [38] (468 W), and 10-bit analog-to-digital converter (80 W) [39] was evaluated about 7.21 mW. Previous work [20] using enhanced 8051 microcontroller and a signal conditioning board consumed 117.66 mW. Energy per seizure event determination (32-sample window) was 1.15 mJ for this work and 18.8 mJ for enhanced 8051 prototype, respectively. Over 90% power reduction and energy saving were improved with previous microcontroller implementation. The evaluation results show that the overall system powered by a 3.7-V, 1100-mAh battery can be operated for 18.9 weeks. Moreover, the proposed BSP has passed the stress testing for two weeks to guarantee the stability. Verification under in vivo temperature (35 C to 45 C) condition has also been done for over six months. This session presented the evaluation of proposed low-power BSP. Based on the measurement results based on the EEG signals from four absent rats, the proposed BSP successfully detected the seizures using our test-vehicle with proposed algorithm and firmware.

VII. CONCLUSION #1 during sleep due to the wrong decision of the seizure detection algorithm regarding the EEG signals in SWS as SWDs. In Fig. 10, four SWDs were marked by neurologist during a 40-s period on subject #1. These SWDs were all detected by the proposed processor. One SWD marked by neurologist may contain more than one detected event based on 32-sample window. We counted these detected events within neurologist’s mark as same event; otherwise, we treated them as false detection. Although the theoretical seizure detection delay of the proposed algorithm was about 0.5–0.8 s, the delay would be slightly varied among subjects due to variation of EEG complexity and spectrum energy. Table III shows the detection delay was varied from 0.62 to 0.88 s and the average is 0.65 s.

This paper presents a processor core base on RISC technology that consumed only 6 mW but capable to process the real-time epileptic seizure detection algorithm. The measurement results yields 90% power reduction and energy saving compare with microcontroller implementation. The developed bio-signal processor, firmware and epileptic seizure detection algorithm is able to detect the seizure signals in 0.5–0.8 s with responding rate as higher as 92%. The measurement results are based on the EEG signals recorded on four free moving animal models. The successful of this research provides a solid base to integrate with analog front-end circuitries and stimulators to build up a system-on-a-chip solution for future implanted neural-prosthesis devices.

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ACKNOWLEDGMENT The authors would like to thank Dr. Y.-L. Hsin of Tzu Chi Medical Center, Taiwan, for interpreting epileptic seizure signals.

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Tsan-Jieh Chen was born in New Taipei City, Taiwan, in 1985. He received the B.S. degree in electrical engineering from the Ming Chi University of Technology, New Taipei City, Taiwan, in 2007. He is currently working toward the Ph.D. degree with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan. His research interests include digital circuit design and embedded systems for biomedical applications.


Herming Chiueh (M’90) received the B.S. degree in electrophysics from National Chiao Tung University, Hsinchu, Taiwan, and the M.S. and Ph.D. degrees in electrical engineering from University of Southern California, Los Angeles. From 1996 to 2002, he was with Information Sciences Institute, University of Southern California, Marina del Rey. He has participated the VLSI effort on several large projects in USC/ISI and most recently participated the development of a 55-million transistor processing-in-memory (PIM) chip. He currently serves as an Assistant Professor of the Department of Electrical Engineering and the Deputy Director of the Biomimetic Systems Research Center at National Chiao Tung University, Hsinchu, Taiwan. His research interests include system-on-chip design methodology, low-power integrated circuits, mixed-signal circuits and systems, neural interface circuits, and biomimetic systems.

Sheng-Fu Liang (M’09) was born in Tainan, Taiwan, in 1971. He received the B.S. and M.S. degrees in control engineering from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1994 and 1996, respectively, and the Ph.D. degree in electrical and control engineering from NCTU, in 2000. From 2001 to 2005, he was a Research Assistant Professor in Electrical and Control Engineering, NCTU. He joined the Department of Biological Science and Technology, NCTU, in 2005, and joined the Department of Computer Science and Information Engineering (CSIE) and Institute of Medical Informatics (IMI), National Cheng Kung University (NCKU), Tainan, Taiwan, in 2006. Currently, he is an Associate Professor in CSIE and IMI, NCKU. He is also a collaborative researcher of Brain Research Center (BRC) and Biomimatic Systems Research Center (BSRC), NCTU. His current research interests are biomedical engineering, biomedical signal/image processing, machine learning, and multimedia signal processing.

Shun-Ting Chang was born in Taoyuan, Taiwan, in 1987. She received the B.S. degree in electrical engineering from the National Chung Hsing University, Taichung, Taiwan, in 2009. She is currently working toward the M.S. degree with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan. Her research interests is embedded system implementation of a low-power real-time seizure detection algorithm.

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Chi Jeng was born in Hsinchu, Taiwan, in 1987. She received the B.S. degree in engineering science from the National Cheng Kung University, Tainan, Taiwan, in 2009. She is currently working toward the M.S. degree with the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan. Her research interest is hardware implementation of a low-power real-time seizure detection algorithm.

Yu-Cheng Hsu was born in Taichung, Taiwan, in 1986. He received the B.S. degree in electronic engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 2009. He is currently working toward the M.S. degree with the Department of Computer Science and Information Engineering, National Cheng Kung University, Tainan, Taiwan. His research interests are brain-computer interface, neural engineering-brain stimulation, and neurological disorders-epilepsy.

Tzu-Chieh Chien was born in Taichung, Taiwan, in 1987. He received the B.S. degree in computer science and information engineering, in 2010, from the National Cheng Kung University, Tainan, Taiwan, where he is currently working toward the M.S. degree. His research interests are biomedical signal processing, brain–computer interface, neural engineering-brain stimulation, and neurological disorders-epilepsy.