THE REAL-TIME IMPLEMENTATION OF MULTI-CHANNEL AMR CODEC USING TMS320C62xx DSP Hyung-Jung Kim*, Deock-Gu Jee*, Man-Ho Park*, Byung-Sik Yoon*, Song-In Choi* Mobile A/V Research Team Electronics and Telecommunications Research Institute (ETRI) 161 Gajeong-Dong, Yuseong-Gu, Daejeon 305-350, Korea Tel : +82-42-860-3811 Fax : +82-42-860-5452 E-mail :
[email protected]
Abstract ETRI adopt AMR codec for developing the 3GPP based IMT-2000 system. This paper presents the software and hardware implementation of multichannel AMR codec. The real-time implementation of AMR codec algorithm is achieved using TMS320C62xx DSP chip. We describe the efficient software scheme for implementing AMR codec and detailed hardware design. The multi-channel AMR codec is evaluated and confirmed in 3GPP test sequences, stand-alone test system and ETRI IMT2000 prototype system. Keywords : AMR codec, TMS320C62xx, Multichannel implementation, IMT-2000
Ⅰ. Introduction For demanding multimedia mobile communication and worldwide roaming services, the mobile telecommunication technology is rapidly moving from 2nd generation mobile system to 3rd generation mobile system like IMT-2000 (International Mobile Telecommunications–2000). The 3GPP (3rd Generation Project Plan) has developed and standardized the IMT2000 system. The 3GPP standardized AMR codec as mandatory speech codec for IMT-2000 narrow-band telephony service in Feb. 1999. The AMR codec consists of the multi-rate speech coder [1], a source controlled rate scheme [2] including a voice activity detection [3] and a comfort noise generation system [4], and an error concealment mechanism [5] to combat the effects of transmission errors and lost packets. The AMR speech coder is a single integrated speech codec with eight source rates from 4.75 kbit/s to 12.2 kbit/s, and a low rate background noise-encoding mode. The AMR codec is capable of
switching its bit-rate every 20 ms speech frame upon command. The AMR codec selects the optimum source-coding rate (or codec mode) and channel-coding rate to deliver the best combination of speech quality and system capacity. The network controls the overall operation of AMR codec, in terms of used codec modes as well as general adaptation behaviour. For downlink and uplink, quality information is derived by estimating the current channel state. Based on the channel state unit, and also taking into consideration possible constraints from network control, the codec mode control, which is located on the network side, selects the codec mode to be applied. In this paper we present software implementation based on 32-bit fixed-point TMS320C62xx DSP chip and whose hardware implementation for 3GPP-based IMT2000 TRAU (TRanscoder Adaptation Unit) system. The brief AMR codec algorithm and its properties are explained in section Ⅱ. Then, we explain the real-time implemented AMR codec scheme operating on TMS320C62xx chip and hardware scheme for AMR codec board for TRAU in section III and IV respectively. Finally we remark conclusions in section V.
II. AMR codec algorithm The AMR codec uses eight source-coding mode with bit rate 12.2, 10.2, 7.95, 7.4, 6.7, 5.9, 5.15, and 4.75 kbit/s and one DTX (Discrete Transmission) mode. 12.2 kbit/s codec is called as EFR-GSM (Enhanced Full RateGlobal System for Mobile communication) speech codec, which is currently used in GSM system. 7.4 kbit/s codec is standardized as IS-641 that is used in North America TDMA system. 6.7 kbit/s codec is used in PDC (Personal Digital Cellular) system in Japan. The AMR codec operates on 20 msec speech frames, each corresponding to 160 samples. In addition,
there is a look-ahead of 5 ms, resulting in a total algorithmic delay of 25 ms. All the codec modes are based on the CELP (code-excited linear prediction) coding model. A 10th order linear prediction (LP) is used. In this model, the excitation signal at the input of the short-term LP synthesis filter is constructed by adding two excitation vectors from adaptive and fixed codebooks. The speech is synthesized by feeding the two properly chosen vectors form these codebooks through the short-term synthesis filter. The optimum excitation vector in a codebook is chosen using an analysis-bysynthesis search procedure in which the error between the original and synthesized speech is minimized according to a perceptually weighted distortion measure. All of speech mode have similar encoding scheme except their bit frame. In each 20 ms speech frame, 95, 103, 118, 134, 148, 159, 204 or 244 bits are produced, corresponding to a bit-rate from 4.75 to 12.2 kbit/s.
The software implementation of multi-channel AMR codec is developed and evaluated using a PCI/C6202 EVM board with TMS320C6202 DSP, which is operated at 250 MHz with 128 K-word internal program memories and 64 K-word internal data memories. The PCI/C6202 EVM board also has a 16 Mword SDRAM and a 512 K-word Flash ROM. The TMS320C62xx DSP chip has two multipliers and six ALUs and can perform eight 32-bit instructions in parallel at every CPU clock. To reduce complexity, we should use its parallelism fully. After hardware booting operation, the softwarebooting and initialization module, which run firstly, downloads program and data from Flash-ROM to internal memory of TMS320C6202 DSP and initializes McBSP (Multi-channel Buffered Serial Port), DMA (Direct Memory Access) controller and internal data memory of TMS320C6202 DSP.
Ⅲ. Software scheme for real-time implementation To implement AMR codec using fixed-point DSP chip, first of all we should get the fixed-point C language source program [6]. The AMR codec fixed-point C source has been released by ETSI (European Telecommunication Standards Institute). In the second step, we design the function call-tree, which shows how many subroutines have been used and how much call depths are needed. In third step, we design the memory map for the real-time operation. It is possible that we estimate local memory usage and global memory usage. Local memory is used for locally used variables, while global memory for the variables with permanent and continually updated. Then, we program each subroutine. We perform fixed-point C optimization using TMS320C62xx compiler intrinsic for cross compile. We analyzed the efficiency of assembly code resulting from cross compile at each subroutine. We carried out linear assembly optimization for non-efficient subroutine and specially hand-coded assembly language optimization for high complexity subroutine. In hand-coded assembly optimization procedure, we focused on efficient instruction selection, paralleling, pipelining, and register allocation to reduce complexity. After finishing the each subroutine programming, we should make comparison between fixed-point C source result and developing program result. We merge all the subroutines and verify their performances with test sequence provided by ETSI [7]. At last, we add the interrupt service routine for PCM data control.
Command Handler
Host Processor Interface
Tx Frame
Encoder
Rx Frame
Decoder
PCM Interrupt Handler
ST-BUS Interface
Figure 1. Software architecture of AMR codec The architecture of the software, which includes real-time AMR codec program, is shown in Figure 1. The software for real-time operation consists of a main control module and three functional modules. The three functional modules are the AMR encoder, AMR decoder and interrupt handler. The interrupt handler module is divided PCM interrupt handling routine and external command handling routine. The PCM interrupt handler controls input/output of PCM data via ST-BUS and operation of encoder and decoder. The external command handler controls service to command that is sent by host processor and transfer of packet data [8]. Table 1 shows the results of the real-time implementation of AMR codec algorithm on PCI /C6202 EVM evaluation board. All the modes have been verified by 22 speech mode test sequences and 4 DTX mode test sequences provided by ETSI.
DMA of TMS320C6202 DSP chip and DPRAM are initialized. After initialization, the DSP wait for 20 msec interrupt. Whenever 20ms interrupt occurs, the interrupt handler receives/transmits packet data from/to DPRAM and starts an encoding routine. The decoding routine begins after the completion of an encoding routine. The real picture of AMR codec board is shown in figure 3. AMR codec board consist of four TMS320C6202 DSP chip and each DSP has the ability to process 8-channels. So, implemented AMR codec board has the capability of processing 32-channels.
Table 1. Result of real-time Implementation Item
Performance
Program Size
71 K-words
Data Size
52 K-words
Complexity
12.2 kbit/s
15 MHz
10.2 kbit/s
13 MHz
7.95 kbit/s
13 MHz
7.40 kbit/s
13 MHz
6.70 kbit/s
13 MHz
5.90 kbit/s
11 MHz
5.15 kbit/s
11 MHz
4.75 kbit/s
15 MHz
IV. Hardware scheme for AMR codec board AMR codec board, which is shown in Figure 2, is located in CNS (Core Network simulator), which constitutes ETRI IMT-2000 system. AMR codec board is designed as an add-on board style. This board briefly has four AMR codec blocks and a programmable EPLD (Electric Programmable Logic Device). Each AMR codec block consist of a TMS320C6202-250MHz DSP, a DPRAM (Dual Port RAM) and a Flash-ROM. DPRAM transmits and receives AMR coded packet data and external commands from host module. Flash-ROM is used for the purpose of self-booting. We use an EPLD for generating signal to control other devices. We use JTag port for debugging AMR codec.
TMS320 C6202
hM sO l F R
TMS320 C6202
M A R P D
M A R P D
hM sO l F R
TMS320 C6202
We also develop the stand-alone test system for operation verification of AMR codec. This test system, which includes TMS320C5410 DSP chip, performs the verification of implemented AMR codec software and hardware before real operation in ETRI IMT-2000 prototype system. This test system, which is shown in Figure 4, simulates all the operations, which is expected to occur in real system. In this test system, we simulate Land-to-Mobile call operation, Mobile-to-Land call operation and Mobile-to-Mobile operation.
2 r o t c e n n o C
M A R P D
hM sO l F R
TMS320 C6202
Figure 3. AMR codec board
M A R P D
hM sO l F R
1 r o t c e n n o C
Control Logic J-TAG
Figure 2. Block diagram of AMR codec board When power is on, the AMR codec program is downloaded to internal program memory of TMS320C6202 DSP chip from Flash-ROM in board. Then, internal register, internal data memory, McBSP,
Figure 4. Stand-alone test system.
The brief description of verification operation using AMR codec board and test system is followed. The speech signal from microphone or handy-set is converted into PCM data using codec in test sytem and sent to McBSP in TMS320C6202 DSP chip through ST-BUS. The PCM data is accumulated in the buffer by DMA controller. At encoder, the PCM data is converted to transmission parameter packet after the AMR encoding procedure. The PCM data is reconstructed from the transmitted parameter packet after decoding procedure. The analog speech signal is unquantized from PCM data by codec and transferred to speaker or handy-set.
V. Conclusions In this paper, we present the AMR codec software and hardware using TMS320C6202 DSP chip. We perform fixed-point C-code optimization, linear assembly optimization, and hand-coded assembly optimization for multi-channel real-time operation. The performance of implemented system shows 72 K-word program memories, 52 K-word data memories and reasonable complexity from 15 to 11 MHz clock cycle. We present an efficient software scheme for real-time implementation. We design and develop an AMR codec board. We also describe efforts for verifying its operation using our stand-alone test system. The AMR codec software and hardware have been evaluated in test sequence, this test system and ETRI IMT-2000 prototype system. The implemented AMR codec has the capability of processing 32-channels with four TMS320C6202 DSP chip. We note that the system shows good and convincible speech quality
References [1] [2] [3]
[4] [5] [6] [7]
3GPP, 3G TS 26.090 : “AMR Speech Codec; Transcoding function” 3GPP, 3G TS 26.093 : “AMR Speech Codec; Source Controlled Rate operation” 3GPP, 3G TS 26.094 : “AMR Speech Codec; ; Voice Activity Detector for AMR Speech Traffic Channels” 3GPP, 3G TS 26.092 : “AMR Speech Codec; comfort noise for AMR Speech Traffic Channels” 3GPP, 3G TS 26.091 : “AMR Speech Codec; Error Concealment of Lost Frames” 3GPP, 3G TS 26.073 : “AMR Speech Codec; Csource code” 3GPP, 3G TS 26.074 : “AMR Speech Codec; Test sequences”
[8]
B. Yoon, J. Kim, W. Lee, S. Jang, S.Choi and M. Lim, “Fixed Point Implementation of the QCELP Speech Coder,” ETRI Journal, volume 19, number 3, pp. 242-258, Oct. 1997
