the substrate noise detector for noise tolerant

THE SUBSTRATE NOISE DETECTOR FOR NOISE TOLERANT MIXED-SIGNAL IC Byung-tae Kang, N. Vijaykrishnan, M. J. Irwin,D. Duarte

Abstract—Substrate noise is an important parasitic of mixed-signal integrated circuits. The existing analysis tools of substrate noise provide accuracy but need complex calculation to model the substrate noise. Also the model can be used as a guidance for optimal placement and routing. In this paper, a new type of substrate noise detector is proposed. It is embedded in a mixed-signal IC and monitors the level of substrate noise. The voltage comparators are used to detect errors and a counter tracks the number of errors periodically. From the number of error, the level of substrate noise is estimated using the probabilistic approach. This type of detector is useful in that it monitors substrate noise in real-time. Using this, the various adaptive algorithms become feasible to reduce substrate noise. The details of detector circuits are given and adaptive analog-to-digital converter as an application is discussed in this paper. Index Terms—IC, mixed signals, sustrate noise, TIQ

A

I. INTRODUCTION

nalog circuits are being implemented by deep sub-micron CMOS technology and integrated with large digital circuits such as DSP cores. The high speed digital circuits generate substrate noise that is propagated to the analog circuit. Substrate noise can be categorized by intrinsic and switching noise. Intrinsic noise is due to the natural thermal noise. Switching noise is generated when the digital circuits are switching. Comparing the two noise sources, switching noise is quite dominant. Switching noise can be destructive in embedded analog circuits, dynamic logic and memory because it can be propagated to great distance and affect the capacitive coupling and body effect. Characterizing the substrate noise is not a simple problem in that the geometry and process variations of one chip can vary the noise distribution and pattern. Many papers have been recently published describing ways to overcome this problem. Among these papers, the analytical method was provided to solve the partial difference equation related to the charge transport mechanisms directly [1]. Other approaches to more quickly evaluate substrate noise at a global level have been proposed for substrate-aware optimization. In these approaches, substrate noise signature are dealt with. The switching noise injects a unique current waveform into the substrate. Such a

B. Kang is with the department of electrical engineering, Pennsylvania State University, University Park, PA 16802 USA (e-mail: bkang@ cse.psu.edu). N. Vijaykrishnan and M. J. Irwin are with the department of computer science and engineering, Pennsylvania State University, University Park, PA 16802 USA (e-mail: vijay@ cse.psu.edu and [email protected]) . D. Duarte is with Logic Technology Development, Intel Corp. Hillsboro OR 97124 USA (e-mail: [email protected]).

waveform is known as the ‘substrate noise signature’. And it is dependent on the technology, the circuits and the input vector. Early models were proposed by a Gaussian white or pink noise model that are commonly used in probabilistic approaches. Recently SUBWAVE has been proposed to extract more accurate substrate noise signatures [2]. SUBWAVE combines the characteristics of all cells given library and the switching activity. Various options have been proposed to deal with the substrate noise problem. For example, a substrate-aware placement methodology has been implemented [3]. This optimization also can be performed in floorplanning, routing and compaction process. Moreover M. Badaroglu et al. proposed the state-of-the-art techniques such as a supply-current waveform-shaping technique based on a clock tree with latency, on-chip decoupling, and so on [4]. Thus the development of analysis tools have made a great progress but optimization problems have still many issues to be solved. In this paper, a new type of substrate noise detector is proposed. It is embedded in the mixed-signal IC and monitors the level of substrate noise. Voltage comparators are used to detect errors and a digital counter counts the number of errors periodically. From the number of errors, the level of substrate noise is estimated using the probabilistic approach. This type of detector is useful in that it monitors substrate noise in real-time. Using this, various adaptive algorithms become feasible to reduce the substrate noise. The rest of this paper is organized into three major parts. In section II, detail design steps of proposed circuit are explained in an analytical way. Section III presents the experimental results. Also an adaptive analog-to-digital converter is discussed as a case study. Finally, we provide concluding remarks in Section IV. II. DESIGN OF SUBSTRATE NOISE DETECTOR A. Voltage comparator The first step of designing the substrate noise detector starts with explaining the voltage comparator of the Analog-to-Digital Converter (ADC). The voltage comparator plays a key role in the substrate noise detector. The voltage comparator compares the difference between input voltage and a reference voltage and propagates the result to the encoder part. Voltage comparators are usually categorized into two types, amplifier-type and latch type. Amplifier-type comparators are a natural choice in that a small voltage at the input is amplified to a value large enough to be detected by later stages of digital logic circuits. For a fast ADC, latch-type comparators are widely used. A quite different type of voltage comparator that

is known as the Threshold Inverter Quantization (TIQ) was proposed in [5]. The TIQ comparator uses two cascaded CMOS inverters as a comparator for implementing a high-speed flash ADC. The principle of this comparator is related to the inverter threshold voltage denoted to Vm and defined as the Vin=Vout point in the VTC of an inverter. It is defined by Eq-1 mathematically. Vm =

r (VDD − VTp ) + VTn 1+ r

with

r=

kp

µp

Vin

and

µn

+ + -

∞

VSB = ∑ An ⋅ sin(ω n ⋅ t + ϕ )

- Eq-1

kn

where VTp and VTn represent the threshold voltages of the PMOS and NMOS respectively. In Fig-1, Vm plays the same role as the threshold voltage of the differential amplifier (Fig-1(a)). Also Vm is adjusted by changing the ratio of (W/L)p and (W/N)n that are the ratio of gate width and length. Because kp and kn are a function of these ratios. Using Eq-2, the threshold of comparators is determined. So, there is no need for additional reference voltage circuits such as resistor ladder that is commonly used in flash type ADC. µ pW p - Eq-2 r= µ nWn (where

vulnerable to substrate noise and easier to estimate its operation analytically. The second step of designing the substrate noise detector is the analytical estimation of TIQ voltage comparator. Before simulating the variance of Vm, the substrate noise should be modeled. Eq-4 shows the VSB model[6]. - Eq-4

n =1

We define An as a random variable for the magnitude of VSB. It has an uniform distribution. Here ωn is the harmonic of digital switching frequency. φ is a random variable for the phase shift and uniformly distributed from 0 to 2π. The mean and variance of Vm are simulated by Eq-1 and Eq-4. In this simulation, 0.25 micron technology [8] parameters are used and supply voltage is assumed to be 2.5V. We simulate it for 10 usec (10000 samples) at 1GHz sampling. Fig-2 shows the distribution of Vm along with various substrate noise. All magnitudes of substrate noise are root mean square values. Table-1 summarized the mean and variance values.

are hole and electron mobility)

Vout Vin

Vref

Vout

Vout

Vout

Fig-2 The distribution of Vm (the rms value of VSB is 98.6mV) Vref

Vin

Vm

Vin

Table-1 The mean and variance of Vm along with VSB 22.9mV 32.6mV 65.2mV 98.6mV rms of VSB

a) Conventional Comaprator b) TIQ Comaprator Fig-1 VTC characteristics

Mean Var.

B. Probability of Error Approach Vm can fluctuate when the threshold voltage of PMOS or NMOS changes. In general, the threshold voltage is determined by Eq-3

VT = VT 0 + γ ( φ + VSB − φ )

- Eq-3

( γ : body-effect coefficient, φ : the surface inversion potential, VT0: substrate voltage and VT0: the threshold voltage for VSB =0V) VT is a function of VSB because other parameters are mainly determined by the semiconductor technology. As explained, the substrate voltage is generated by abrupt draining of substrate current when digital circuits are switching. The substrate voltage makes the threshold voltage fluctuate, as a consequence, Vm changes as a result of the variation. Thus the variation of Vm is directly related to the substrate noise. Using these properties, a TIQ based comparator is used for designing the substrate noise detector. The TIQ based comparator is

0.757159 0.000038

0.757239 0.000077

0.756715 0.000312

0.755619 0.000733

From the results, the mean is decreasing moderately and the variance is increasing as VSB is increasing. It implies that the larger VSB generates the larger error. The distributions is approximately same as Gaussian distribution. For simplicity, we assume the distribution of Vm as Gaussian distribution and each comparator’s distributions are independent (In reality, this is not true. It will be discussed later). Fig-3 shows the distributions of three comparators in ADC. Vm(i-1) is the lowest and Vm(i+1) is the highest bit among three comparators. Three comparators’ Vm are changing with substrate noise independently as Gaussian distribution. Assume that the input voltage, Vin is less than Vm(i-1) and very close to Vm(i-1). When Vm(i) is in the region 1 and Vm(i-1) is in the region 2, ith comparator produces output 1 and i-1th comparator produces output 0. This is obviously an error and called as monotonic error. In this case, the probability of monotonic error is determined by Eq-5.

Pe = Pe (region1) ⋅ Pe (region2) =

C. Proposed Circuit

1 mean(Vm(i )) − mean(Vm(i − 1)) ⋅ (0.5(1 − erf ( )) 2 Var (Vm(i )

where erf ( x ) = 2 ⋅ ∞ exp( − t 2 ) dt π ∫0

TIQ comparator

- Eq-5 Vin

1

1

2

2

Gain Booster

Error Counter Counter Enable

Region 2

Vin

Counter Clock Sampling Clock

20

Reset

Fig-5 The substrate noise detector

Region 1

Vm(i-1)

Region 3

Vm(i)

Vm(i+1)

Region 4

Fig-3 The monotonic error region

The proposed circuit is consisted of three blocks, TIQ comparator, gain booster and error counter. TIQ comparator has two pairs of inverter that have different channel length and width. Each comparator’s parameters are summarized in Table-2. The values of Vm are measured by HSPICE using 0.25 micron technology[8]. The measured value is close to the calculated value using Eq-1(The calculated value is 0.757V. The error is approximately 1%). Table-2 The specification of inverters comparator Width PMOS 2.37u 1 NMOS 9.70u PMOS 2.00u 2 NMOS 10.05u

Fig-4 The probability of monotonous error (6 bit TIQ ADC) Fig-4 shows the probability of error defined by Eq-5 in 6 bit TIQ ADC. We simulated 32 comparators in 6-bits TIQ flash ADC from LSB. When comparator is close to LSB, error is growing. The comparator used for LSB should detect low input voltage near 0.7V that is close to the threshold voltage. So, this comparator is the most vulnerable to substrate noise. It can be clearly seen that the larger substrate noise, the more probability of error. To detect the substrate noise more sensitively, the comparator used for LSB can be used. As mentioned before, the distribution of each comparators’ Vm is not independent in reality. Because the same amount of substrate noise is applied to every comparator at the same time. Even there are some different propagation delays for geometric reason, they cannot guarantee the independency between each comparators. In other words, Vm(i-1), Vm(i) and Vm(i+1) are shifted to the same direction at the same time. For this reason, monotonous errors will not take place much as expected. But this dependency can be obtained by slight modification to design the substrate noise detector. This idea is explained in next section.

Length 0.24u 0.24u 0.24u 0.24u

Vm 0.79V 0.75V

As mentioned earlier, two comparators are dependent on the substrate noise level. If the positive noise is asserted, the Vm of two comparators will be increased at the same time, and vice versa. In Fig-3, we calculated the probability of error assuming that two comparators are independent on substrate noise. To emulate the independency, Vm(i) in Fig-3 is replaced by a constant voltage source from outside of chip that has the mid-value between Vm(i-1) and Vm(i+1) (0.77V in this case). Then other comparators, Vm(i-1) and Vm(i+1) are independent with Vm(i) and remain dependent with each other. In this case, the probability of error is determined by Eq-6 (in Fig-3) - Eq-6 Pe = Pe (region3) + Pe (region4) When the noise does not exist, the output of the comparator 1 should be zero and the output of the comparator 2 should be one. But the noise makes Vm value of both comparators increase or decrease at the same time. When the Vm value of comparator 2 is over 0.77V, its output will be zero. This case is the monotonous error. Conversely, the negative noise makes Vm value of two comparators decreasing. Then the output of comparator 1 can be under 0.77V and makes the monotonous error. The constant voltage source can have the variation due to the fluctuation of supply voltage. When this fluctuation is under 1% that is nominal specification of common mixed signal IC, this does not affect much on our circuit, because this variance is smaller than the variance of Vm. The gain booster is used to guarantee the full digital output voltage swing and improve the transition slope of comparator output. The minimal size of transistors in the given technology are used [5]. When the output of the comparator 1 is one or the

output of the comparator 2 is zero, the monotonous error takes place. Each error is accumulated by the error counter. As we estimated the probability of error with 106 samples in chapter 2, 20-bits counter that operates at 1GHz clock is used. After 1msec, the result of counter is latched to register and this counter is cleared. Based on the result of counter, we can measure the probability of error during 1msec. III. EXPERIMENTAL RESULTS AND CASE STUDY

and power-efficient system can be designed. Its block diagram is shown in Fig-7. The noise detector is embedded in ADC to estimate the noise asserted to ADC. The noise level is checked by QoS control. The existing QoS control has the information about the requirement of resolution according to the channel condition. In Fig-7, the information about the reduction of ENOB is added to QoS control to decide whether the reduction of ENOB due to the substrate noise satisfies the specified transmission rate. When the reduction is more than that, we reduce the transmission rate. Thus we can adapt the transmission rate according to the substrate noise level.

Adapative Pipelined ADC

a) noise

b) Error Counter Enable

Noise Detector

Digital Part (Processor Core, Baseband Modem)

QoS Control

c) The output of Comparator 1

Fig-7 The example of the noise detector usage IV. CONCLUSION

d) The output of Comparator 2 Fig-6. Simulation results of substrate noise detector Fig-6 shows the simulation result of proposed circuit using HSPICE. The input volage is 0.77V and noise’s peak is varying from 0V to 120mv. The first half of noise waveform is the positive noise and the second half of noise waveform is the negative noise. From Fig-6 (c), we can see that Vm value of comparator 1 is decreased in the negative noise region (especially noise peak is under –80mV). From Fig-6 (d), we can see that Vm value of comparator 2 is increased in the positive noise region (especially noise peak is over 80mV). The negative and positive noise is detected by error counter enable. The counter enable accumulates the number of errors within a specified time (1msec in this case). Using this value, Eq-6 and analytically pre-calcualted values in Table-1, we can estimate the r.m.s. value of substrate noise. This detector’s usages are various with the respect to software and hardware. In this paper, adaptive ADC as a hardware application is dealt with. In [6], Y. Zinzius et al. show that the performance of ADC is effected by substrate noise. It degrades the effective number of bits(ENOB) by 20%. It means that this ADC cannot guarantee the specified resolution due to the input of substrate noise. In [7], the adaptive pipelined ADC is proposed to save the power and guarantee the quality of service (QOS). The resolution of ADC is adaptively adjusted according to the channel condition. Having a higher resolution allows transmission at higher rates. Using this ADC and the noise detector that is proposed in this paper, a noise-tolerant

A new type of substrate noise detector is proposed and its design steps are explained. It is analytically analyzed, implemented using 0.25 micron technology and tested. It is composed of simple circuits and detects the substrate noise sensitively. Due to the simplicity, it can be embedded to mixed-signal IC without much overhead. As illustrated by an ADC example, this type of detector is useful in that it monitors substrate noise in real-time. REFERENCES [1] [2]

[3] [4]

[5] [6]

[7]

[8]

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