Towards Robust Implementation of Memristor Crossbar Logic Circuits Lei Xie
Delft University of Technology, Delft, the Netherlands Email:
[email protected] Abstract—Memristor crossbar is a promising technology for future VLSI circuits due to its scalability, non-volatility, high integration density, etc. However, sneak path currents in the crossbar pose major robustness challenges. One proposed solution is applying half-select voltages to floating nanowires (which are not involved in logic operations). This paper analyzes the sneak path issue after applying half-select voltages, and then uses this analysis to derive a set of realization parameter constraints for robustness. In addition, the constraints are used to estimate maximal crossbar size of logic circuits. As a case study, a one-bit full adder is implemented and verified with SPICE simulations; the results show that the proposed approach accurately predicts the impact of sneak path currents with a maximal error of 0.06V.
such work is reported. This paper contributes: • Analytical formulation of the impact of sneak path currents and dynamic switching process on crossbar logic. • Constraints of implementation parameters for robustness. • Maximal crossbar size estimation for a given technology. The remainder of this paper is organized as follows. Section II describes the fundamentals of Snider Boolean logic which is used as an example for our methodology. Section III presents the proposed methodology. Section IV verifies our approach using SPICE. Finally, section V concludes the paper. II. S NIDER B OOLEAN L OGIC
I. I NTRODUCTION Novel technologies (e.g., memristors, nanotube, graphene transistors, etc. [1,2]) are being investigated for future VLSI circuits. Memristor is a promising candidate due to its high integration density, and compatibility with CMOS process. Massive memristors can be mapped on the crossbar architecture; each one is located at the crosspoint of a horizontal and vertical nanowires [2]. Based on memristor crossbar, implication [3,4] and Boolean [5] logic have been proposed. However, sneak path currents (SPCs) are a major issue for crossbar-based logic as it leads to unexpected switching, or even erroneous functions [3]. To alleviate the impact of SPCs, three approaches have been proposed [2,6]: (i) using additional selectors, or (ii) complementary resistive switches (CRS) and (iii) applying half-select voltage (HSV). Extra selectors (e.g., transistors or diodes) are used to prevent SPCs by breaking current paths; CRS represents data using the polarity of the memristors and always come in a high resistance; HSV fixes the voltages of floating nanowires that are not part of the computation. Among them, HSV is compatible with logic circuits using high and low resistance to represent logic states without adding any extra devices. However, HSV is only a partial solution to SPCs as it only minimizes the SPCs instead of eliminating them. As a result, logic circuits may still fail due to improper implementation parameters (e.g, OFF/ON ratio). To address this issue, we propose a generic methodology that can be applied to both Boolean and implication logic. The impact of SPCs are first formulated. Its result is used to derive a set of parameters constraints for robust implementation by combining switching conditions of both selected and unselected memristors. Meanwhile, the impact of dynamic switching process is also formulated. To our knowledge, no
This section first describes the ideal memristor model, and then presents the fundamentals of Snider Boolean logic (SBL). A. Memristor Model Fig. 1(a) shows the I-V relation of the ideal memristor used in SBL [5], which has a high (RH ) and low (RL ) resistance. The memristor switches from one resistive state to another once the absolute value of the voltage across the device is greater than its threshold voltages. Otherwise, it stays in its current resistive state. A memristor typically requires two different threshold voltages for SET (Vts ) and RESET (Vtr ) operations, and Vtr
