Unity Power Factor Control for Three-Phase Three-Level Rectifiers ...

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 43, NO. 5, SEPTEMBER/OCTOBER 2007

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Unity Power Factor Control for Three-Phase Three-Level Rectifiers Without Current Sensors Bingsen Wang, Member, IEEE, Giri Venkataramanan, Member, IEEE, and Ashish Bendre, Member, IEEE

Abstract—Three-level rectifiers with reduced number of switches (such as the Vienna Rectifier) to improve the input power quality of rectifier systems have been receiving wide interest in the past years. In this paper, a new carrier-based pulsewidthmodulation control algorithm is proposed for such converters to eliminate the low-frequency harmonics in the line current while achieving unity power factor at the rectifier input terminals. The operating constraints of the Vienna Rectifier with the carrierbased modulation strategy are examined carefully, and the proposed control algorithm ensures that appropriate voltage/current directional constraints are met. A promising cost-reduction opportunity can be seen with the elimination of input current sensing to operate the Vienna Rectifier. The control algorithm is verified via Saber simulation and experimental results. Index Terms—Carrier-based pulsewidth modulation (PWM), phase-angle control, unity power factor, Vienna Rectifier.

I. I NTRODUCTION

N

EW GENERATIONS of adjustable-speed drive and power supply producers are increasingly incorporating input power factor and waveform control to comply with the various regulatory standards [1]. From time to time, specific applications such as aerospace power require careful regulation of the power converter front-end line current harmonics to minimize undesired interaction among the equipment connected to the same utility grid. A slew of new topologies including the ones based on three-level power conversion have been proposed to realize high-quality input waveforms [2]–[6]. Among these, the topology proposed by Kolar in 1994, which is called the Paper IPCSD-07-033, presented at the 2005 Industry Applications Society Annual Meeting, Hong Kong, October 2–6, and approved for publication in the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. Manuscript submitted for review October 31, 2005 and released for publication April 5, 2007. This work was supported in part by The Boeing Company and in part by the Wisconsin Electric Machines and Power Electronics Consortium (WEMPEC) at the University of Wisconsin, Madison. This work made use of ERC-shared facilities supported by the National Science Foundation (NSF) under Award EEC-9731677. B. Wang is with the General Electric Global Research Center, Niskayuna, NY 12309 USA (e-mail: [email protected]). G. Venkataramanan is with the Department of Electrical and Computer Engineering, University of Wisconsin, Madison, WI 53706 USA (e-mail: giri@ engr.wisc.edu). A. Bendre is with the Advanced Development Group, DRS Power and Control Technologies, Milwaukee, WI 53216 USA (e-mail: ashishrbendre@ drs-pct.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIA.2007.904433

Vienna Rectifier, has the additional benefits of reduced controlled switch count in addition to the general benefits of a three-level converter. Thus, due to the opportunities of competitive cost reduction, the Vienna Rectifier is generally considered attractive [5], [6]. Several control approaches have been proposed for the Vienna Rectifier. The initial application proposed the use of a hysteresis current controller. The switching signals are generated by comparison of the reference current template (sinusoidal) and the measured main currents [4]. Although this approach is easy to implement, the switching frequency is not constant, which is not desired for some applications because of interharmonics. The ramp comparison current control presented in [6] derives the duty cycle by comparison of the current error and the fixed-frequency carrier signal. The ripple current in the input inductor makes the current error noisy although synchronization is carefully considered. Another approach that features constant switching frequency was proposed based on integration control. The input voltage sensors were eliminated in the integration control. However, significant low-frequency distortion can be observed in the input currents [7]. Space vector modulation was analyzed in [3] with recognition of the constraints imposed by the unidirectional nature of the rectifier. For all the approaches mentioned above, the measurement of input currents is necessary. In this paper, a new pulsewidth-modulation (PWM) control algorithm without input current sensing is proposed. Compared to the phase angle control [8] used in the active rectifier, the proposed approach controls both the phase angle and the amplitude of the synthesized voltage to result in the high-quality input current. Reactive component design considerations of three-level converters are presented in Section II. In Section III, the operating limitations of the Vienna Rectifier are examined under reduced switch realization. In Section IV, the state space averaged model for the Vienna Rectifier is developed. Then, the proposed control algorithm and the controller design suitable for the Vienna Rectifier are presented in Section V. Computer simulation results verifying the proposed approach are presented in Section VI and backed up by experimental results in Section VII. Section VIII presents a summary of this paper. II. R EACTIVE -E LEMENT D ESIGN C ONSIDERATIONS A general three-phase three-level rectifier using ideal singlepole triple-throw (SPTT) switches is illustrated in Fig. 1.

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Fig. 1. Schematic of the three-phase three-level rectifier using ideal SPTT.

The realization of the SPTT switch will be discussed in the subsequent section. Appropriate sizing of the reactive elements is crucial to fulfill the purpose of this active front end instead of the passive diode bridge, which is typically to meet the line current harmonic requirement prescribed by regulation standards or certain applications. The sizing of the input inductors for three-level converters is very similar to the two-level converter case. With proper modulation, the harmonics of pole voltages are pushed close to the switching frequency and higher. For the same converter rating and harmonic specifications, the threelevel converter input inductor is smaller since the peak-to-peak ripple voltage seen by the inductor is only half of the dc-bus voltage. However, the dc-link capacitor sizing is quite different due to the third harmonic current flowing to the dc bus neutral point. For typical modulation schemes, the switch in each phase leg will be modulated between the top throw and the midpoint for a half cycle, while in the other half cycle, the switch will be toggled between the bottom throw and the neutral point. Thus, during any interval of π/3, the charging current to the top dc capacitor will be from either one phase leg or two phase legs. The dc-link neutral current contains low-frequency third harmonics due to the inherent feature of three-level converters, which will usually increase the necessary dc link capacitor sizing unless special modulation function is applied [2]. The typical neutral current and its spectrum from sinusoidal PWM modulation are shown in Fig. 2. The resulting size of the capacitor is generally bigger than the critical minimum value considered from the dynamic interaction between the dc link capacitor and the input inductors [9]. This is in contrast with two-level converters, in which case all three phase legs supply the dc link current during each switching period. Thus, the dc bus neutral point sees no low-frequency harmonics. III. S WITCH R EALIZATION C ONSTRAINTS The ideal SPTT switch can be realized using different combinations of controlled switches and diodes. One of the realizations is the unidirectional topology with reduced count of controlled switches, i.e., the Vienna Rectifier, as shown in Fig. 3. In each phase leg, only one controlled switch is used. With the assumption of a continuous conduction mode (CCM), the rectifier pole voltages (van , vbn , and vcn ) have a definite state determined by the ON/OFF states of controlled switches and the polarity of line currents at any instant of operation.

Fig. 2. Waveform of the neutral point current and its spectrum for sinusoidal modulation.

Fig. 3.

Schematic of the power circuit of the Vienna Rectifier.

For instance, if the line current ia is positive, and the controlled switch Qa is off, the voltage between the converter pole A and the dc-bus midpoint N (i.e., vAN ) is Vdc /2. The conduction path for this case is illustrated in Fig. 4(a). If the line current ia is positive, and the controlled switch Qa is on, the voltage vAN is 0, in which case the conduction path is illustrated in Fig. 4(b). Similarly, if the line current ia is negative, the voltage vAN can be either −Vdc /2 if the switch Qa is off or zero if the switch Qa is on, as illustrated in Fig. 4(c) and (d), respectively. This operating principle also applies to phase legs B and C. To avoid low-frequency (lower than the switching frequency) harmonics in line currents, the rectifier phase voltages must be free of low-frequency harmonics except for triplen harmonics, which may be present on the modulation signals to increase the fundamental component without invoking overmodulation. Under CCM, an important operating constraint can be recognized. If continuous sinusoidal PWM is used, the polarity of

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where 

0  0  0 A =  ma1  

Cdc ma2 Cdc 1 La

u = [ van

Fig. 4. Conduction paths for phase-leg A when: (a) the line current is positive, and the controlled switch is off; (b) the line current is positive, and the controlled switch is on; (c) the line current is negative, and the controlled switch is off; and (d) the line current is negative, and the controlled switch is on.

the line currents and the polarity of the imposed line-to-neutral voltage from the switching devices have to be identical. In the past, this has been referred to as the pulse polarity consistency rule [10]. Thus, on an averaged basis, the line currents have to be in phase with the corresponding pole-to-neutral voltages. Otherwise, low-frequency harmonic distortion will occur in both line currents and pole voltages. This requirement is equivalent to the unity power factor at the rectifier poles (not at the source voltages). On the other hand, under space vector modulation mode, the input power factor angle at the rectifier input terminals may lie between (−π/6, π/6) [11]. Although this appears to be a drawback, a realistic value of input inductors leads to a power factor at the line terminals that is greater than 0.98 for typical cases. IV. S TATE -S PACE A VERAGED M ODEL With CCM, the SPTT in each phase leg can be replaced by the averaged model, and the resulting equivalent circuit is shown in Fig. 5. In this model, the harmonics close to the switching frequency are neglected, and the pole voltages only contain the fundamental component and possible third harmonics coming from the modulation signals. However, the third harmonics do not have an effect on the line currents for a three-wire configuration. So, in the subsequent analysis, only the fundamental component of the pole voltages is considered. The state-space model for the averaged system can be described by dx = Ax + Bu dt

(1)

0 0 0

mb1 Cdc mb2 Cdc

mc1 Cdc mc2 Cdc

0

 0  B =  0  0 0 x = [ ia

0 0 0

1 Lb

0 0 0 ib

− mLa1 a − mLb1 b − mLc1 c

−1 RL Cdc 1 RL Cdc

 0 0   1  Lc  0 

 − mLa2 a  − mLb2 b   − mLc2 c  1  RL Cdc −1 RL Cdc

0 ic

vbn

vc1

vc2 ]T

vcn ]T .

With assumptions of La = Lb = Lc = L, and vc1 = vc2 = Vdc /2, transforming the three-phase abc quantities into a synchronous reference frame in polar coordinates results in  a  I d  Lθ  IL dt Vdc    θ  Vdc a   1 a −IL − 2 M cos M θ − ILθ L Vs cos   θ  Vdc a  a  1 −IL − 2 M sin M θ − ILθ − ωe =LILa Vs sin  (2)

 2Vdc  θ 3 a 1 a θ − I M cos M − I L C 2 L RL where ILa and ILθ are the amplitude and phase angle input current vector (also called dynamic phasor), respectively [12]. Similarly, M a and M θ are the amplitude and phase angle of the modulation index space vector, respectively. Here, the phase of the three-phase ac source voltage is chosen as reference. This dynamic model has been shown to be convenient for regulator design based on phase angle coordinates. Under steady state, the dynamic model (2) reduces to a set of phasor relations visualized in Fig. 6. Due to the operating constraints imposed by a particular switch realization, the line currents are in phase with the rectifier pole voltages. The phase angle between the source and pole voltages is determined by the phase angle of modulation functions. It may be noticed that if the pole voltage is modulated such that it stays on the trajectory indicated by the dotted half circle, then the line current is forced to be in phase with the pole voltage. Furthermore, the phase angle between the source and pole voltages determines the active power flow, as is classically formulated in ac power systems theory. For a balanced operation, the power flow to the rectifier is given by P =−

3Vsa Vdc M a sin(M θ ) . 2ωe L

(3)

Notice that the maximum power transfer occurs when M θ = π/4, i.e., Pmax = −

3 (Vsa )2 . 2ωe L

(4)

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Fig. 5. State-space average model of the Vienna Rectifier.

To design the PI regulator, the transfer function between the phase angle M θ and Vdc is derived from the state-space averaged model formulated in dynamic phasors. The model described in (2) is nonlinear with respect to the control input M θ . By linearizing the system at the nominal operating point, a small-signal model is obtained, i.e., dˆ x = Aˆ x + Bu ˆ dt Fig. 6. Phasor diagram of unity-power-factor constraint at the rectifier input.

where 

The maximum power point typically corresponds to unpractical large input current, which would not be suitable for practical applications.

0  − ωe A =  ILA

ILA ωe 0



0 

3 MA 2 C

 A −M 2L 0   − RL2 C

0 Vdc M A  B =  − 2I AL L 0  A iL  x ˆ =  iΘ L vdc

V. P ROPOSED C ONTROLLER The common practice of controlling the three-phase boost rectifier, either two-level or three-level topology, resorts to multiloop control [9], [13], [14]. Typically, the dc-link voltage reference is compared against the feedback voltage, and the error is fed to a proportional and integral (PI) regulator. The output of the PI regulator becomes the current reference. The inner current loop uses a proportional gain to calculate the required pole voltage reference. Due to the bandwidth limitation of the inner current loop, the controller is preferred to be implemented in the synchronous reference frame, which is complicated. In regard to the Vienna Rectifier, the controller is even more complicated due to switch realization. Space vector modulation is often the choice to stay within the constraints. A new control algorithm is proposed based on phase angle control, as shown in Fig. 7. Only a voltage loop is used to regulate the dc bus voltage. No current sensing/estimation is needed in this algorithm. The error between the dc voltage reference and the dc voltage feedback is processed by the PI regulator. The output of the PI regulator becomes the phase angle difference between the source and pole voltages. The phase angle difference is also used to calculate the modulation index space vector. Typically, the phase angle of the modulation index space vector is small. The amplitude of the modulation index vector varies only by a small amount during normal operation. So the power flow is mainly controlled by the phase angle M θ , although the proper amplitude M a is critical to ensure the unity power factor at the rectifier poles to achieve good quality of the input current waveforms.

(5)

u ˆ = mΘ . The small-signal transfer function between mΘ and vdc may be determined to be G(s) =

vdc = G0 · mΘ 1+

1



s ωr

1+

1 s Qc ωc

+

s2 ωc2



(6)

where ωr =

1 RC 2

+

 ωc =

2R 3MA 8ω22 L

ωe2 +

3 MA2 4 LC

1

Qc =

ωc ωr

Go =

−3Vdc MA2 · R . 8ωe L

ωc2 ωr2

−1

It is interesting that the control transfer function of a threephase boost-derived Vienna Rectifier features a third-order system with a real pole and a pair of complex poles under

WANG et al.: UNITY POWER FACTOR CONTROL FOR THREE-LEVEL RECTIFIERS WITHOUT CURRENT SENSORS

Fig. 7.

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Block diagram of the proposed controller. TABLE I SALIENT PARAMETERS USED IN SIMULATION

A PI regulator is designed to stabilize the system by shaping the loop gain transfer function with adequate phase margin and gain margin. The compensated loop gain transfer function is plotted in Fig. 8. The loop gain gives about 60◦ phase margin and 10-dB gain margin. The bandwidth of the closed-loop system is about 20 Hz. VI. S IMULATION R ESULTS

Fig. 8.

Bode plot of the loop gain transfer function with a PI regulator.

angle control. This is in stark contrast to more classical control approaches exhibiting a right-half plane zero in their dynamics.

A detailed Saber model has been built to verify the control algorithm. The salient parameters used in the small-scale simulation model are listed in Table I. Under steady-state operation, the sinusoidal line-to-line source voltage Vab and the modulated pole-to-pole voltage VAB are shown in the top panel of Fig. 9. It is observed that the pole voltage at the rectifier slightly lags the source voltage. The small phase angle difference between the source voltage and the pole voltage results in an appropriate power flow to

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Fig. 9. Steady-state simulation results of salient quantities with the proposed control algorithm. The top two traces are the sinusoidal line-to-line source voltage Vab and the modulated pole-to-pole voltage VAB . The bottom two traces are the sinusoidal line current ia and the modulated pole-to-neutral voltage VAN .

Fig. 11. Simulation of the dynamic response of the pole-to-pole voltage vAB (upper panel), ac line current ia , and dc bus voltage Vdc (lower panel) to a load step change. (a) Load step up. (b) Load step down.

the line current off-tune but return to normal waveforms after the dc-link voltage transient dies out and the rectifier settles to a new operating point. Fig. 10. Simulation of line current ia and pole voltage VAN for (upper panel) case (a) when the magnitude of the modulation index is not controlled properly and (lower panel) case (b) with proper control of modulation index.

regulate the dc bus voltage. The sinusoidal line current ia and the modulated pole-to-neutral voltage VAN are exactly in phase, as shown in the lower panel of Fig. 9. It is critical to satisfy the phasor relation defined by the diagram in Fig. 6. Otherwise, the reduced switch realization of the converter results in lowfrequency distortion. To illustrate this point, the distorted line current and pole voltage due to violation of the necessary phasor relation are shown in the top panel of Fig. 10 compared to the proper line current and pole voltage shown in the lower panel of the same figure. In addition, the dc-link voltage has more ripple voltage not shown in the figure. The transient response of the pole-to-pole voltage vAB , input current ia , and dc-bus voltage Vdc to a step-up and step-down change of the output load is shown in Fig. 11(a) and (b), respectively. During the transients, both the pole-to-pole voltage and

VII. E XPERIMENTAL R ESULTS In order to verify the proposed controller and simulations, experiments have been conducted on a laboratory-scale prototype. The steady-state measurements are recorded in Fig. 12, which shows the line-to-line voltage vab and pole-to-pole voltage vAB in the upper panel, and the line current ia and pole-to-neutral voltage VAN in the lower panel. Similar to the simulation results, a leading phase angle of the source voltage with respect to the pole voltage and in phase between the line current and the pole voltage has been observed. In the experiment, the identified operation constraints are deliberately violated, and the ac line current distortion is obvious, as shown in the upper panel of Fig. 13. Even the pole-to-neutral voltage is distorted due to the distorted zero crossing of the line current. The transient response of the controller has been tested against the step changes in load. The pole-to-pole voltage vAB , input current ia , and dc bus voltage Vdc to a step-up and stepdown change of the output load are shown in Fig. 14(a) and (b),

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Fig. 12. Steady-state experimental results of salient quantities with the proposed control algorithm. The top two traces are the sinusoidal line-to-line source voltage Vab and the modulated pole-to-pole voltage VAB . The bottom two traces are the sinusoidal line current ia and the modulated pole-to-neutral voltage VAN .

Fig. 14. Experimental results of the dynamic response of the pole-to-pole voltage vAB (upper panel), ac line current ia , and dc bus voltage Vdc (lower panel) to a load step change. (a) Load step up. (b) Load step down.

Fig. 13. Experimental measurement of line current ia and pole voltage VAN for (upper panel) case (a) when the magnitude of the modulation index is not controlled properly and (lower panel) case (b) with proper control of modulation index.

respectively. During the transient, both the pole-to-pole voltage and the line current are off-tune but return to normal waveforms after the dc link voltage transient dies out and the rectifier settles to a new operating point. The strong agreement between the experimental results and the simulation results is readily evident from the figures. VIII. C ONCLUSION This paper has presented design-oriented analytical solutions that address the application of three-level rectifiers with particular focus on the Vienna Rectifier. The harmonic loading

on the dc bus capacitor due to circulating neutral currents has been identified as an issue to be considered in sizing the dc bus capacitor. The operating constraint introduced by the reduced switch realization, i.e., unity power factor at the rectifier poles as opposed to source terminals, is identified under typical carrier-based PWM mode control. Although the phase angle difference between the source and pole voltages is small (less than a few degrees) for typical inductor values, a unity power factor at pole voltages is critical in ensuring optimal ac line current quality. For a particular design, the phase angle difference may be so small that the current distortion may not be obvious with unity power factor at ac sources. A new PWM control algorithm based on phase angle control is proposed to ensure that the operating constraints of the reduced switch realization are met. The system is modeled using dynamic phasor, and the controller is designed based on that model. The proposed control algorithm is verified by Saber simulation and laboratory experiment. The match between the

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simulation and experimental results validates the modeling and the controller design. This new control algorithm is relatively simple compared to an inner-current–outer-voltage multiloop controller. The constant switching frequency provides a better line current spectrum compared to the hysteresis current controller. Furthermore, this controller offers a promising cost-reduction opportunity by eliminating the line current sensors, which accordingly eliminates the analog-to-digital conversion channels associated with the typical digital implementation of the controller. The protection against overcurrent can be realized using much more cost-competitive current-limiting schemes. R EFERENCES [1] T. S. Key and J. S. Lai, “Comparison of standards and power supply design options for limiting harmonic distortion in power systems,” IEEE Trans. Ind. Appl., vol. 29, no. 4, pp. 688–695, Jul./Aug. 1993. [2] A. Bendre and G. Venkataramanan, “Modeling and design of a neutral point regulator for a three level diode clamped rectifier,” in Conf. Rec. IEEE Ind. Appl. Soc. Annu. Meeting, Salt Lake City, UT, 2003, pp. 1758–1765. [3] J. W. Kolar and U. Drofenik, “A new switching loss reduced discontinuous PWM scheme for a unidirectional three-phase/switch/level boosttype PWM (VIENNA) rectifier,” in Proc. 21st INTELEC, Copenhagen, Denmark, 1999, Paper 29-2. [4] J. W. Kolar and F. C. Zach, “A novel three-phase utility interface minimizing line current harmonics of high-power telecommunications rectifier modules,” in Proc. 16th INTELEC, 1994, pp. 367–374. [5] N. B. H. Youssef, F. Fnaiech, and K. Al-Haddad, “Small signal modeling and control design of a three-phase AC/DC Vienna converter,” in Proc. 29th Annu IEEE IECON, Roanoke, VA, 2003, pp. 656–661. [6] U. Drofenik and J. W. Kolar, “Comparison of not synchronized sawtooth carrier and synchronized triangular carrier phase current control for the VIENNA rectifier I,” in Proc. IEEE ISIE, Bled, Slovenia, 1999, p. 13. [7] C. Qiao and K. M. Smedley, “Three-phase unity-power-factor starconnected switch (VIENNA) rectifier with unified constant-frequency integration control,” IEEE Trans. Power Electron., vol. 18, no. 4, pp. 952– 957, Jul. 2003. [8] N. R. Zargari and G. Joos, “A near unity power factor input stage with minimum control requirements for AC drive applications,” IEEE Trans. Ind. Appl., vol. 31, no. 5, pp. 1129–1135, Sep./Oct. 1995. [9] B. Shi, G. Venkataramanan, and N. Sharma, “Design considerations for reactive elements and control parameters for three phase boost rectifiers,” in Proc. Int. Elect. Machines Drives Conf., San Antonio, TX, 2005, pp. 1757–1764. [10] J. Zubek, A. Abbondanti, and C. J. Norby, “Pulsewidth modulated inverter motor drives with improved modulation,” IEEE Trans. Ind. Appl., vol. IA-11, no. 6, pp. 695–703, Nov./Dec. 1975. [11] Y. Zhao, Y. Li, and T. A. Lipo, “Force commutated three level boost type rectifier,” IEEE Trans. Ind. Appl., vol. 31, no. 1, pp. 155–161, Jan./Feb. 1995. [12] G. Venkataramanan and B. Wang, “Dynamic modeling and control of three phase pulse width modulated power converters using phasors,” in Proc. 35th Annu. IEEE Power Electron. Spec. Conf., Aachen, Germany, 2004, p. 2822. [13] M. Malinowski, M. Jasinski, and M. P. Kazmierkowski, “Simple direct power control of three-phase PWM rectifier using space-vector modulation (DPC-SVM),” IEEE Trans. Ind. Electron., vol. 51, no. 2, pp. 447– 454, Apr. 2004. [14] P. Barrass and M. Cade, “PWM rectifier using indirect voltage sensing,” Proc. Inst. Electr. Eng.—Electr. Power Appl., vol. 146, no. 5, pp. 539–544, Sep. 1999.

Bingsen Wang (S’01–M’06) is a native of China. He received the M.S. degree in electrical engineering from Shanghai Jiao Tong University, Shanghai, China, in 1997, the M.S. degree in electrical engineering from the University of Kentucky, Lexington, in 2002, and the Ph.D. degree in electrical engineering from the University of Wisconsin, Madison, in 2006. From 1997 to 2000, he was an Electrical Engineer with the Carrier Air Conditioning Equipment Company, Shanghai, China. Since 2006, he has been a Power Electronics Engineer with the General Electric Global Research Center, Niskayuna, NY. He is currently engaged in various research activities in power electronics, mainly in the high-power area. He has authored or coauthored more than ten technical articles in peer-reviewed conference proceedings and refereed journals. He is the holder of one Chinese patent. His research interests include power converter topologies, in particular, multilevel converters and matrix converters, dynamic modeling and control of power electronics systems, application of power electronics to power quality problems, FACTS, and electric drives. Dr. Wang received the Best Paper Award from the Industrial Power Converter Committee (IPCC) of the IEEE Industry Applications Society in 2005.

Giri Venkataramanan (M’92) received the B.E. degree in electrical engineering from the Government College of Technology, Coimbatore, India, in 1986, the M.S. degree from the California Institute of Technology, Pasadena, in 1987, and the Ph.D. degree from the University of Wisconsin, Madison, in 1992. After teaching electrical engineering at Montana State University, Bozeman, he returned to the University of Wisconsin as a faculty member in 1999, where he continues to direct research in various areas of electronic power conversion as an Associate Director of the Wisconsin Electric Machines and Power Electronics Consortium (WEMPEC). He has published a number of technical papers. He is the holder of five US patents. His interests are in the areas of microgrids, distributed generation, renewable energy systems, matrix and multilevel power converters, and ac power flow control.

Ashish Bendre (S’01–M’03) received the B.Tech. degree in electrical engineering from the Indian Institute of Technology, Bombay, India, in 1990, and the M.S. and Ph.D. degrees in electrical engineering from the University of Wisconsin, Madison, in 1992 and 2003, respectively. He is currently working toward the M.B.A. degree at the University of Chicago, Chicago, IL. He has over 12 years of industrial power converter design and development experience, primarily with Pillar Technologies and SoftSwitching Technologies. He is currently the Director of research and development with DRS Power and Control Technologies, Milwaukee WI, where he manages and conducts research focused on naval power conversion. His primary areas of interest include power electronics and control design for multilevel converters, dc–dc converters, and power quality devices.