Visual Assessment of a Real-Time System Design: A ... - CiteSeerX

Proceedings, IEEE Real-Time Systems Symposium, December 1996

Visual Assessment of a Real-Time System Design: A Case Study on a CNC Controller Namyun Kimy, Minsoo Ryuz, Seongsoo Hongz, Manas Saksenax, Chong-Ho Choiz and Heonshik Shiny .

Abstract

In this paper we describe our experiments on a realtime system design, focusing on design alternatives such as scheduling jitter, sensor-to-output latency, intertask communication schemes and the system utilization. The prime objective of these experiments was to evaluate a real-time design produced using the period calibration method [2] and thus identify the limitations of the method. We chose a computerized numerical control (CNC) machine as our target real-time system and built a realistic controller and a plant simulator. Our results were extracted from a controlled series of more than hundred test controllers obtained by varying four test variables. This study unveils many interesting facts: (1) average sensor-to-output latency is one of the most dominating factors in determining control quality; (2) the eect of scheduling jitter appears only when the average sensor-to-output latency is suciently small; and (3) loop processing periods are another dominating factor of performance. Based on these results, we propose a new communication scheme and a new objective function for the period calibration method.

The work reported in this paper was supported in part by Engineering Research Center for Advanced Control and Instrumentation (ERC-ACI) under Grant 96K3-0707-02-06-1, by KOSEF under Grant 96-2037, and by NSERC Operating Grant OGP0170345. y Dept. of Computer Engineering, Seoul National University, Seoul 151-742, Korea. z School of Electrical Engineering and ERC-ACI, Seoul National University, Seoul 151-742, Korea. ([email protected]) x Dept. of Computer Science, Concordia University, Montreal, PQ H3G 1M8, Canada.

1 Introduction With the maturity of real-time system technologies, embedded digital controllers are increasingly substituting analog controllers in many control systems. Examples of such systems include computerized numerical control (CNC) machines, avionics y-by-wire systems, automotive control systems, etc. As the application areas diversify and the controlled systems become more complex, the accompanying real-time systems are anticipated to carry out intricate control algorithms. Such systems must necessarily be built using a multitasking design with dierent tasks running at dierent rates sharing data resulting in many interacting and overlapping data paths from sensors to actuators. The design of a digital controller involves many steps starting from a conceptual schematic diagram of the controller, and ending in a set of schedulable periodic tasks. During this process various design decisions are taken, such as mapping the controller block diagram into a task graph structure, selection of synchronization and communication primitives, choosing task periods and deadlines, selecting a scheduling strategy, etc. These design decisions are often taken in an ad-hoc way, albeit guided by engineering intuition, partly due to lack of information available at the design stage, and partly due to lack of tools available to help evaluate those design decisions. For example, a control engineer would select sampling periods based on controller performance requirements, largely ignoring the impact of the decision on schedulability. Likewise, the communication structure of a task graph design has serious implications on sensor-to-actuator latencies, and hence on controller performance and schedulability, but no tools are available to a design engineer to analyze and evaluate the consequences of a particular design. As a result, it becomes extremely dicult, if not impossible, to reach the \right" system design, as the controller structure moves towards higher complexity. In recent work [2], we have proposed a design


methodology that partially addresses this problem by postponing assignment of task periods and deadlines. Instead, the design of a system uses timing constraints speci cation on \end-to-end" computations rather than individual tasks. These constraints include: (1) maximum end-to-end latency from a sensor to an actuator, (2) maximum time skew between multiple sensor input readings needed for an actuator output, (3) minimum and maximum output jitter, and (4) maximum activation period for a computation, etc. Such constraints are more natural to specify for a control engineer, and allow the nal assignment of task periods and deadlines to be determined based on schedulability concerns. This was achieved by expressing the end-to-end requirements as intermediate constraints on task attributes, namely periods and deadlines, and then solving the intermediate constraints using schedulability as an optimization criterion. As a result, the methodology permits traceability of timing requirements, quick identi cation of schedulability bottlenecks in design, and tool support to converge quickly to a design in which the timing constraints satisfaction is a priori guaranteed. In order to eciently support the translation of end-to-end constraints to task attributes, we had to incorporate several design decisions into the method. We assumed that the real-time system design could be expressed as a task graph, with producer-consumer relationships between tasks for data communication. A key ingredient of our design scheme was the communication between producer-consumer pairs, which allowed purely asynchronous communication between producer-consumer tasks, but still permitted (1) low end-to-end latencies, (2) a simple and ecient scheme to achieve input synchronization, and (3) avoided unnecessarily high execution rates. This was achieved through harmonicity constraints on periods which restricted the consumer to execute with a period which was an integral multiple of the producer's period; this simple restriction allowed the two tasks to stay \inphase," yielding the above bene ts. The heart of our approach was in the assignment of periods to tasks, and hence we call this methodology a period calibration method. In this paper, we report a case study of applying the period calibration method to a CNC (computerized numerical control) controller design. The major objective of this study is to identify the limitations of the period calibration method so that we will be able to extend it as an essential tool to streamline real-time system design. A secondary objective of this work is to develop a workbench on which we can visualize the interplay between a variety of design alternatives for real-time systems. To meet these objectives, we have

constructed a complete, operating workbench consisting of two Pentium PCs communication via a dual port memory module. One PC is used to model the plant behavior, while the other PC is used to run the controller on top of Mircotech's VRTX real-time operating system [5]. To conduct our experiments, we developed the software for the controller algorithms, as well as the simulation programs modeling the CNC plant. The end-to-end timing constraints were derived using the mathematical simulation package MATLAB [6]. We used our period-calibration tool to assign periods and deadlines to tasks, scheduled them using earliest deadline scheduling, and nally created a cyclic executive structure for run-time dispatching. In our experiments, we wanted to study the impact of design and scheduling artifacts on the controller's performance. These included the sensor-to-actuator latencies, output jitter, task periods, etc., since these are the nal artifacts of all design decisions taken during a controller development. In this way, we hoped to understand the impact of decisions taken into our period calibration method, and thereby guide ourselves to potential limitations of the methodology. To achieve this objective, we derived many dierent test cases by manipulating the period calibration method, the cyclic executive scheduling method, etc. 1.1

Preview of the Experimental Results

Our experiments validate the usefulness and practicality of our approach. We successfully managed to use the period calibration tool to design our controller. Moreover, we were able to quickly generate a number of prototype controllers, and test their performance. Here we brie y preview the experimental results and the utility of the experimental workbench. Our experiments suggest that the control quality signi cantly depends on the end-to-end constraints used by our tool, and that their relative impact on the performance varies. We summarize the facts we found during the experiments. (1) Sensor-to-output latency was one of the factors which dominated control quality. (2) The periods of output tasks were another critical factor; larger periods produced larger errors. On the other hand, the system utilization did not possess a strong relationship with control quality. Note that for a given utilization value, we can create various period assignments such that output tasks have dierent periods. (3) Contrary to our original expectation, output jitter did not make a noticeable dierence when sensorto-output latencies were large. The sensor-to-


output latencies played a larger role than output jitter. In addition, we showed that our experimental workbench as well as the period calibration tool was a valuable aid in reducing the number of iterations between controller design and implementation. This is clear from the current control engineering practice. Control engineers design digital controllers in a rather idealized manner: they { also many commercial simulation tools such as MATLAB { assume that control tasks execute instantaneously. Thus, the end-to-end constraints of a controller is determined solely by the control laws, not by implementation-level constraints such as CPU utilization. Thus it is likely that control engineers need to repeat the controller tuning, after the controller is fully implemented and information on the realized controller is available. On the other hand, our simulation workbench could be used before the implementation as a tuning environment. In fact, our workbench is much more realistic than many of the control simulation packages, since it explicitly accounts for controller scheduling delays. We can further reduce the system development time using the period calibration as a rapid prototyping tool. 1.2

Remainder of the Paper

The rest of the paper is organized as follows. Section 2 presents the design of the experimental CNC workbench, and an overview of the CNC controller used for our experiments. In Section 3, we show how the end-to-end constraints are derived from the given performance requirements, and show the application of the period calibration method on the CNC controller. Section 4 gives the design of our experimental test cases, and in Section 5 we present the results of our experiments, and analyze the results. Finally, in Section 6 we conclude the paper with a summary of our contributions and future research directions.

2 The Experimental CNC Workbench In this section, we present the design of the CNC workbench giving a brief overview of CNC machines, the hardware and software organization, and the CNC controller software. 2.1

CNC Machines

A CNC machine is an automatic machining tool which is used to produce user-designed workpieces. As its name implies, it is equipped with a computer-based digital control system, and oers consistent, accurate,

and exible production of machine workpieces. Nowadays CNC machines are found almost everywhere from a small rural job shop to a large manufacturing cell [4]. The most basic function of a CNC machine is motion control. A CNC machine controls several directions of motion, called axes. The CNC motion control subsystem should be able to position the cutter precisely and automatically along the reference trajectory of the machined workpiece. The major components of the CNC motion control subsystem are controllers, servopacks, and servo motors. Of these, the controller component is the heart of a CNC machine. The controller periodically reads from multiple inputs, computes its algorithms, and updates control commands for the plant. As plants need multiple control variables and have a high degree of performance and robustness requirements, associated control algorithms tend to be complex. Moreover, a CNC controller possesses very stringent hard real-time requirements: the sampling frequencies are very high and missed deadlines may cause over-cutting of a workpiece [4]. CNC machines have been traditionally implemented with a dedicated DSP (digital signal processing) board for the motion control subsystem. The controller is designed in a very simple fashion; a single scanning task is created which does all input readings, control law execution, and output updates in one scan. Since such an implementation involves multiple heterogeneous processors, it incurs hardware complexity, cost, and high communication overhead. With modern microprocessors oering high performance computing support at a very low cost, it becomes viable to realize the multiple functionalities of a CNC machine such as spindle control, digital I/O processing, and man-machine interface all in a single high performance microprocessor system. However, this requires abandoning the simple controller design for a multi-rate, multi-tasking system making it a good candidate to apply our period calibration method. In the following subsections, we present an overview of the CNC workbench and the controller software that we have implemented. 2.2

Hardware and Software Overview

The CNC workbench was implemented using two PCs, one running the controller software, and the other used as a plant simulator. The plant simulator was implemented as an in nite loop and models the servopacks and servo motors. The controller software runs on top of the VRTX real-time operating system [5], and was developed using VRTX cross-development tools. We implemented two I/O boards, one for each PC, for communication between the plant and the controller.


Hardware Pentium 60MHz (256K cache, 32M RAM) Pentium 100MHz (256K cache, 16M RAM) Timing Measurement Board (10MHz oscillator) IO Board (4K DPRAM) Software VRTX-PC/8086 version 2.1 Borland C++ 3.1

over-cutting state.

X Position Reference

PD Controller

Disturbance Estimation System Monitoring

Y Position Reference

PD Controller

Servopack

Servo Motor

X Position

Servo Motor

Y Position

Disturbance

Servopack

Table 1: Hardware and software speci cations of the simulation workbench. Finally, we built a timing measurement board, which was plugged into an I/O slot, for accurate measurement of execution times for controller tasks. The timing board consisted of an independent clock source and a counter register. Task timings were taken by clearing the counter at the beginning of execution and reading the counter at the end of the task execution. The timer board had a resolution of 100ns. The hardware and software organization is shown in Figure 1, and their speci cation is presented in Table 1. CNC Controller

Plant Simulator

VRTX OS

MS−DOS x_pos, y_pos

Timer Board

IO Board

IO Board

Timer Board

xctrl_com, yctrl_com, sys_stts

Pentium PC (60MHz)

Pentium PC (100MHz)

Figure 1: Hardware and software components of the simulation workbench. 2.3

The CNC Controller Software

In this case study we implemented a multi-tasking CNC controller, and used it for an elliptical reference trajectory with a major radius (X-axis) of 15mm, and a minor radius (Y-axis) of 10mm. The block diagram of the control system is shown in Figure 2. Our implementation of the controller and the plant was based on the mathematical models developed in [4]. As shown in the gure, there are two inputs into the controller for each of the axes. These correspond to the elliptic reference position, and the actual cutter location which is sampled from the motors. The motion control is eected by a controller for each of the axes. In addition, there is a disturbance estimation and monitoring subsystem, which issues a signal to the plant when the machine enters into either a large external torque or an

Figure 2: The block diagram of the CNC machine. We represent a controller design using a graph model as described in [2]. In this model, the tasks and the data items passed between tasks are represented as vertices, while the edges correspond to read/write operations. Figure 3 (A) shows the task graph derived from the schematic diagram of Figure 2. In the gure, tasks are represented as oval shaded objects, while the rectangular objects correspond to data items. Roughly speaking, each box in the schematic diagram corresponds to a task in the task graph. The plant is also drawn inside a box to show the connection between the controller software and the plant simulator. The design consists of the following elements: x pos and y pos denote the sampled cutter location of each axis. Tasks xsmpl and ysmpl denote the sampling tasks reading them. x vel and y vel are the velocities of the X axis and the Y axis motors. Task calv computes these values using x pos and y pos. x ref and y ref denote the reference position. These are computed by tasks xref and yref . x dist and y dist are disturbance estimated from the current position and velocities of the motors. Task dist computes them. Task stts monitors the state of the plant. It issues a signal to the plant when the machine enters into either a large external torque or an over-cutting state. xctrl and yctrl are the controller tasks. They compute the control laws and update the controller outputs.

3 Period Calibration Methodology In this section we give an overview of our period calibration methodology and illustrate its application to the CNC controller software design. We rst derive the end-to-end timing constraints, and then brie y present

Proceedings, IEEE Real-Time Systems Symposium, December 1996 x_pos

y_pos

x_pos

y_pos

xsmpl ysmpl

xref

calv

x_ref

x_pos

yref xref y_ref

calv

x_ref

y_ref

x_pos y_pos x_vel y_vel

x_pos y_pos x_dist y_dist

x_pos y_pos x_dist y_dist

xctrl_com

dist

stts

yctrl xctrl

sys_stts

yctrl_com

Servopack of X axis Motor of X axis

yref

x_pos y_pos

x_pos y_pos x_vel y_vel

dist

xctrl

y_pos

smpl

Servopack of Y axis PLANT

(A)

Motor of Y axis

xctrl_com

stts

yctrl

sys_stts

yctrl_com

Servopack of X axis Motor of X axis

Servopack of Y axis PLANT

Motor of Y axis

(B)

Figure 3: (A) Task graph of the CNC control system; and (B) its transformed task graph. the communication strategy used for period calibration. Subsequently, we give a brief overview of the period calibration method and show how the task attributes are derived using it. We then present a simple cyclic executive scheduling scheme which was used to schedule the controller tasks on our workbench. 3.1

End-to-End Timing Constraints

Following [2], we rst proceed with the derivation of end-to-end timing constraints for our controller design. This step was done with the help of MATLAB [6] tools. We used three types of constraints as follows: (1) Synchronization constraint: When sampled data from multiple sensors are used to compute a controller output, a synchronization constraint restricts the time skew between those samples. In our system two sampled data x pos and y pos are used together in task dist to produce the correct output sys stts. Let t1 and t2 be the times when tasks xsmpl and ysmpl read the cutter location of each axis, respectively. Then the synchronization constraint denoted by Sync(x pos; y posjjsys stts) dictates

jt1 ? t2 j Sync(x pos; y posjjsys stts): In our experiment, we restricted the synchronization constraint to 200s which is sucient for the task stts to produce a reliable sys stts. As shown in [2], the synchronization constraint is easily guaranteed by transforming the task graph such that the synchronized inputs are read to-

gether by a common sampling server task. The transformed task graph is shown in Figure 3 (B). (2) Maximum allowable validity time (MAVT): This constraint bounds the end-to-end propagation delay from a sensor to an output. Consider a path from x pos to xctrl com in the task graph. The maximum allowable validity time denoted M(x posjjxctrl com) dictates that the propagation delay from x pos to xctrl com should be no greater than M(x posjjxctrl com). This constraint guarantees that sampled inputs will be used before they lose their freshness. (3) Maximum loop processing period (MLPP): The maximum loop processing period ensures that a control loop is executed often enough to maintain eective control. In our system, we have three interacting control loops: two loops for motion control of the x and y axes, and one loop for the disturbance and system monitoring. The MLPP of these loops are denoted by P(x posjjxctrl com), P(y posjjyctrl com), and P(x pos; y posjjsys stts). For our experiments, we derived MLPP and MAVT values for motion control loops through MATLAB simulations in such a way that the average contour error was under 70 units, where 1 unit of error represents 1/2400 mm. Control engineers normally use MLPP = MAVT, and use it to determine a suitable value which meets the error requirements. In fact, one could choose any value of MAVT, and then nd an MLPP corresponding to it. We have chosen a value of M(x posjjxctrl com) = M(y posjjyctrl com) = 4000s, and then obtained the corresponding MLPPs of X and Y axis as 16200s and 12500s, respectively. The rationale behind this choice will become clear in Section 4 when we explain our experiment design. For the disturbance loop, we chose M(x pos; y posjjsys stts) = P(x pos; y posjjsys stts) = 6000s to ensure that the cutter is stopped quickly enough when the disturbance is high. 3.2

Communication Strategy using Harmonicity Constraints

In multi-rate systems data communication gets complicated between tasks running at dierent rates. Under such circumstances, task executions may get out of phase resulting in large latencies in communication. In order to achieve low latency communication, while still allowing tasks to run at dierent rates, we introduced a harmonicity constraint between the periods of any producer/consumer pair in the task graph [2]. The

Proceedings, IEEE Real-Time Systems Symposium, December 1996 Sync. Constraint MLPP

Sync(x pos; y pos sys stts) 200 s P (x pos xctrl com) 16200 s P (y pos yctrl com) 12500 s P (x pos; y pos sys stts) 6000 s M (x pos xctrl com) 4000 s M (y pos yctrl com) 4000 s M (x pos; y pos sys stts) 6000 s

p 50

jj

jj

0 1 2

jj

jj

MAVT

jj

150 1

jj

jj

Table 2: The end-to-end constraints of the CNC controller. harmonicity constraint requires that the period of the consumer be an integral multiple of the period of the producer task. This ensures that the two tasks stay \inphase," thus reducing communication latencies. The harmonicity requirement also permitted us to achieve tight synchronization among input samples through the use of virtual sequence numbers, and a buer management scheme using circular queues, which we refer to as a harmonic queue scheme. We brie y review the construction of a harmonic queue, and then present an alternative implementation scheme which can reduce latencies at the cost of losing tight input synchronization.

Harmonic Queues versus Single-Slot Queues.

Consider a single producer task p , producing data which is consumed by n consumers i :: 1 i n. The shared data buer b is implemented as a circular queue with s slots, where s = (LCM1in(Ti ))=Tp . The producer p writes into one slot in each execution in a circular fashion. A consumer i reads circularly from slots (i TTi mod s) for i 0. As an example, we show a harmonic queue with three tasks p ; 1 and 2 in Figure 4. The periods of the tasks are annotated next to the nodes. The two consumer tasks 1 and 2 run with periods 150 and 50, respectively, and the producer task with period 50. The buer requires 3 (= LCM(150; 50)=50) slots. As a result, task 1 reads from only slot (0), while task 2 reads from slots (0,1,2). Under the harmonic queue scheme, a consumer task reads an input which was produced rst within its period. In the above example, p produces three inputs within a period of 1. Among them, task 1 uses the rst data, regardless of when it is scheduled to run. While this allows a task to easily collect all synchronized data, this leads to large sensor-to-output latency. If we can ignore synchronization constraints, we can easily reduce sensor-to-output latency using a singleslot queue. A single-slot queue is essentially the same as a harmonic queue, except that it holds only a sin-

2 50

Figure 4: Harmonic queue communication scheme. gle slot. As in the harmonic queue scheme, a producer task writes into a single-slot queue, independently of its consumers and a consumer reads from it in the same manner. 3.3

Overview of Period Calibration Method

The period calibration method derives task attributes from a given task graph design of a system and the speci ed end-to-end constraints. The tasks are implemented as periodic tasks which are invoked and executed repeatedly at a xed rate. A periodic task i has two timing attributes, namely a period and a deadline which are denoted Ti and Di , respectively.

Steps for the Period Calibration Method. For a given task graph possessing n tasks f 1 ; 2 ; : : :; n g and the end-to-end requirements on inputs and outputs, the period calibration method derives Ti and Di in two steps, as below. (Step 1) It derives a set of nonlinear constraints on task attributes Ti and Di such that the derived constraints imply the original end-to-end constraints. (Step 2) It solves the derived nonlinear constraints such that chances of obtaining a schedulable task set are maximized. The execution time of a task i is denoted ei . We use the following objective functions. Xn min(U = Tei ) and 8i; 1 i n; max(Di ) i=1 i Step 2 involves solving a nonlinear optimization prob-

lem which is conjectured to be an NP-hard problem. In order to reduce the amount of computation needed for the optimization problem, we changed it into a decision problem in that users provide a cuto utilization and our algorithm tries to quickly nd a rst feasible solution whose utilization is no greater than the cuto value [2]. For the CNC controller, we chose a cut-o


Task Exec. Time Period Deadline smpl 35s 2400s 2400s calv 40s 2400s 2400s dist 180s 4800s 4800s stts 720s 4800s 4800s xref 165s 2400s 2400s yref 165s 2400s 2400s xctrl 570s 9600s 4000s yctrl 570s 7800s 4000s Table 3: The measured execution times and derived periods of the CNC controller tasks. utilization of 0.65 for period calibration. The results of applying the period calibration on our controller task set are presented in Table 3. The task execution times were determined through a timing measurement board having an independent clock source.

Cyclic Executive Scheduling. An implication of harmonicity requirements on periods is that it makes cyclic executive scheduling [1] very attractive, thus incurring low run-time scheduling overheads. Cyclic executive scheduling divides the in nite timeline into uniform intervals called major cycles, and then sub-divides a major cycle into several minor cycles. A schedule is formed by scheduling tasks in each minor cycle; the schedule repeats at the end of a major cycle. Thus, a major cycle completely de nes task scheduling. Minor cycles are used for timing enforcement. An interval timer is set to issue interrupts at minor cycle boundaries, and timing enforcement and house-keeping functions are invoked in response to such interrupts. There are many possible ways to determine major and minor cycles. In general it is desirable to have a small major cycle to reduce memory requirements, and large minor cycles to reduce run-time overheads. We use a simple rule to determine the cycle sizes which works well thanks to the harmonicity property. For a given set of tasks f 1 ; 2 ; : : :; ng, the major cycle denoted TM is the least common multiple of the task periods, i.e., TM = LCM(T1 ; T2; : : :; Tn), and the minor cycle denoted Tm is the greatest common divisor of task periods, i.e., Tm = GCD(T1 ; T2; : : :; Tn). From the periods shown in Table 3, the major and minor cycles are determined to be 28800s and 2400s, respectively. After major and minor cycles are determined, a cyclic schedule is created in such a way that all task deadlines are satis ed. We scheduled our task set within the major cycle using the earliest deadline rst strategy [3]. It leads to an optimal task schedule, since our tasks were made mutually independent. At run-time, the cyclic executive implementation

consists of three major components, namely, (1) a master dispatcher, (2) minor cycle queues, and (3) an interval timer. The ith minor cycle queue holds the sequence of tasks scheduled within the ith minor cycle. Figure 5 shows minor cycle queues in association with the minor cycles. The interval timer regularly issues interrupts at minor cycle boundaries. The master dispatcher switches the minor cycle queue of the last minor cycle with that of the current one. Then it picks the task at the head of the queue and dispatches it. After the task nishes, it voluntarily yields the CPU so that its successor in the queue will be dispatched next. We implemented the master dispatcher on top of VRTX. Since the VRTX kernel is an event driven, xed priority kernel, we implemented a cyclic executive such that the master dispatcher has the highest priority and is periodically activated by the interval timer. All other tasks are created and stored into corresponding frame queues when the controller is initialized. Minor cycle 0Minor cycle 1Minor cycle 2 0

50 1 2 3 4 5

100

150

1 5

.. .

Figure 5: The run-time structure of cyclic executive.

4 Experiment Design For our experiments we wanted to study the impact of the design and scheduling artifacts on the controller's performance. However, this led to a problem since the result of our period calibration method is a complete design. Therefore, for the experiments we did not strictly follow the results of our tool; instead we derived many dierent designs with the help of our tool as will become clear in a short while. In the rest of the subsection, we give details of our design setup including the performance metric, the test variables, and the test cases. 4.1

Performance Metric

We rst had to choose a suitable metric to quantitatively measure the performance of a controller. We use an error metric based on contour error, which is


E=

r Pm

i=1 ci

2

m

We have used 1/2400 mm as the unit to measure the errors. Cutter Trajectory

250 200 150 100 Error

the Euclidean distance1 between a cutter location and its corresponding reference point. Figure 6 visualizes the de nition of the contour error. For a given cutter location P, the corresponding reference point R is determined in such a way that the line between points P and R is a straight line normal to the reference contour. The Euclidean distance between P and R is the contour error. Figure 7 shows the contour errors during an entire machining cycle. The negative values in the plot indicate that the machine over-cut the workpiece. Roughly, a machining cycle is subdivided into two stages. Initially, in the transient stage, the motors undergo abrupt and instantaneous change in inputs since their initial velocity is zero. Since a CNC machine makes only gradual state changes, it cannot react fast enough, thus resulting in large contour errors in the transient stage. After the transient stage, the machine approaches a steady state, where it makes close approximations to the desired responses resulting in much smaller errors. From Figure 7, it is observed that the two stages yield two dierent types of errors. In the transient stage, the maximum overshoot { de ned as the peak, or maximum error { is critical, while in the steady stage, the average error is more important. Considering these two errors together, we adopted the root mean square as a metric for error evaluation in the overall interval. Given m cutter locations fp1; p2; : : :; pm g, let fc1 ; c2; : : :; cm g be the corresponding contour errors. The average contour error E is de ned as below.

50 0 -50 -100 -150 0

4.2

1 On a two dimensional plane, Euclidean distance between two points (x1 ; y1 ) and (x2 ; y2 ) is de ned as (x1 ? x2 )2 + (y1 ? y2 )2 .

200

250

Test Variables

In our experiments, we wanted to measure the impact of various design and scheduling decisions on the controller performance. We de ne the following test variables which are used to build the dierent test cases. Consider a CNC controller implemented with a set ? of n periodic tasks f 1 ; 2 ; : : :; n g. It reads from input sensors fs1 ; s2; : : :; sns g and updates outputs fa1 ; a2; : : :; ana g. Let Ti and ei denote the period and the execution time of task i respectively, and let H = LCM(T1 ; T2; : : :; Tn). A task is called an output task if it generates a controller output. The three test variables are de ned as below. (1) Output Jitter: For controller output ak of task i , let h = THi and O be a set of h consecutive interoutput times of ak . As an example, Figure 8 pictorially depicts oi 2 O where H = 6 and Ti = 2. Jitter of ak (denoted Ji (ak )) is de ned as below.

Ji (ak ) =

s Ph

j =1 (E(O) ? oj )2

h where oj 2 O and E(O) is a mean of O. LCM(?) ak

R

Figure 6: De nition of contour error.

150

Figure 7: Time versus contour errors.

ak

Origin

100 Time

Desired Trajectory

P

p

50

o1

ak o2

ak o3

Ti

Figure 8: Inter-output times of controller output ak . (2) Average sensor-to-output latency: For an output task i, let sl denote a sensor input that i depends on to generate its controller output ak . Let h = THi and L(sl kak ) be a set of sl -to-ak latencies which are obtained from h consecutive instances of i . The average sl -to-ak latency (denoted L(sl kak )) is de ned


as below.

L(sl kak ) =

X lj h

j =1

h

where lj 2 L(sl kak ). (3) Utilization: The system utilization is given as below. Xn U = Tei i=1 i

4.3

Experiment Test Cases

We were concerned with four design factors, namely scheduling jitter, average latency, communication schemes, and utilization. Since utilization is determined solely by task periods and independent of scheduling jitter and average latency, we have two variable spaces as follows: Communication Jitter Latency Communication Utilization

where Communication = fH; S g denotes the communication scheme used. Here \H" is the harmonic queue scheme and \S" the single-slot queue scheme. Instead of measuring exact output generation times, we only considered timing for jitter J and latency L in units of minor frame sizes, which is 2:4ms; this helped us construct a nite number of test cases. In order to denote a test case, we use a label of the form \C=J =L" and \C=U." For example, H=2:4=4:8 denotes a controller with harmonicity queues, with scheduling jitter and average latency being 2.4 and 4.8, respectively. Our experiments were performed on three test cases: (1) H=J =L, (2) S=J =2:4ms, and (3) S=U, which are described in more detail below: (1) H=J =L case: This corresponds to a standard real-time system design that the period calibration tool generates. With this test case, we intended to observe the interplay between jitter and average sensor-to-output latency, and the impact of harmonic queues on the control. In order to reduce the variable space, we conducted our experiments only on the X-axis control output xctrl com which task xctrl produces. The task periods for this test case were the ones derived by our period calibration tool and presented earlier in Table 3. Recall that Txctrl = 9600s, the major cycle is 28800s, and the minor cycle is 2400s. Therefore, we have 3 periods of xctrl in each major cycle, and within each period there are four minor cycles. Depending on which minor frame produces the output xctrl com, we

have 43 dierent combinations within the major schedule. Thus we had 64 cyclic schedules with dierent output jitter and latency values. As explained in Section 3, for the purpose of experiment, we intentionally chose a tight MAVT of 4:0ms for both X and Y axis control loops. As a result, the two motion control loops had relatively large MLPPs, and thus MAVTs had ranges as large as associated MLPPs. (Note that MAVT MLPP.) During the experiment, we compromised xctrl 's deadline which was assigned due to the tight MAVT of 4:0ms, and generated a series of dierent jitter and latency values by scheduling xctrl in dierent minor cycles. (2) S=J =2:4ms case: This denotes a CNC controller whose intertask communications are realized with single-slot queues. Under the single-slot communication scheme, the maximum sensor-to-output latency is bounded below by the minor frame size 2:4ms, since inputs are read in every minor frame and an output task always reads the latest inputs. Therefore, the only variable quantity was the jitter in this case. (3) S=U case: This case represents a collection of CNC controllers with distinct utilization values. In order to observe the pure eect of utilization, we needed to suppress the jitter and latency eects. Since the harmonic queue scheme tends to produce large latencies, we experimented with the singleslot queue scheme only.

5 Experimental Results We extracted the experimental results from a controlled series of more than one hundred test controllers obtained by varying the four test variables. In this section we present these results with illustrative plots and give our analysis on them. Finally, we discuss the lessons learned through the experiment, and suggest design changes for our original period calibration method. 5.1

Harmonic Queue Case

We rst experimented with test controllers with harmonic queues. This test case corresponds to the H=J =L case, hence the test controllers had dierent jitter and latency values. The experimental results are given below. (1) Output Jitter versus Errors. We analyzed the experimental results to derive a relationship between output jitter and errors. Contrary to our thoughts we


originally conceived in [2], output jitter has virtually no impact on the errors. (See Figure 9.) This is mainly because the impact of the average sensor-to-output latency prevails over output jitter in producing errors. Since the inter-task communication based on harmonic queues tends to produce large sensor-to-output latencies, the pure eect of output jitter is not observable under the harmonic queue scheme.

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Figure 11: Case H=J =L: Output jitter/average latency versus errors.

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Figure 9: Case H=J =L: Output jitter versus errors. 700 600

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Figure 10: Case H=J =L: Average sensor-to-latency versus errors.

this, we experimented with the single-slot queue case which reduces the end-to-end latency. Under this communication scheme, the maximum sensor-to-output latency equals to the minor frame size, since sampled input x pos is updated in every minor frame. Thus this test case is labeled as S=J =2:4ms. This also allowed us to isolate the eect of jitter and establish a relationship between jitter and errors.

(1) Output Jitter versus Errors. With relatively small latencies, output jitter becomes a dominating factor in determining errors. Figure 12 shows that the magnitude of the errors is loosely proportional to output jitter. We also note that the errors are relatively much smaller in absolute terms. To illustrate this, in Figure 13 we have plotted the results of this experiment along with the one for the harmonic communication scheme on the same plane, clearly depicting the relative error magnitudes. 23 22

(2) Average Latency versus Errors. We drew a

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dierent graph to nd a relationship between the average sensor-to-output latency and errors. From Figure 10, it is observed that the magnitude of errors rapidly grows as the average sensor-to-output latency increases.

(3) Output Jitter and Average Latency versus Errors. We re-drew from the same experimental results a plot on a three dimensional plane to visualize the relationship between output jitter/average latency and errors. Figure 11 veri es that the impact of the average sensor-to-output latency prevails over the eect of output jitter.

5.2

Single-Slot Queue Case

The rst set of experiments with the harmonic queue suggests that the average sensor-to-output latency plays a large role on nal errors. To further test

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Figure 12: Case S=J =2:4ms: Output jitter versus errors. 5.3

Utilization versus Errors

We obtained six controllers after running the period calibration tool with dierent cuto utilization values. With this experiment, we intended to extract the relationship between the system utilization and errors. Figure 14 shows a tendency that the system utilization is inversely proportional to the errors. On the other


Latencies and harmonic queue scheme: The ex-

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Figure 13: Case S=J =2:4ms: Comparison with H=J =L scheme. hand, there are points where the smaller utilization causes the greater errors. In such cases, the controller with larger utilization had larger loop processing periods than the one with smaller utilization. Figure 15 attests to the fact that the periods of output tasks are more directly related to control quality than utilization. 50 45 40

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Figure 14: Case S=U: Utilization versus errors. Error 50 45 40 35 30 25 20 15 10

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Figure 15: Case S=U: X and Y axis loop periods versus errors. 5.4

Result Analysis and Lessons Learned

We analyze the results obtained from our experiments and the implications of those results for our period calibration tool so as to provide improvements on the existing tool.

perimental results strongly indicate that latency plays a signi cant role, and large latencies result in large errors. As a result, it suggests the use of single slot queues. However, the harmonic queue has a reason for its use: its main motivation in our period calibration tool was that it allows tight input synchronization. Unfortunately, in our experiments, the eects that synchronization constraints have on control quality were not studied. However, we expect that such eects are highly application dependent, and that it will be dicult to provide a general guideline. Thus, we suggest a mixed communication scheme where only tasks which need synchronized inputs use harmonic queues, while other tasks can always use the latest inputs. For example, in our CNC controller, xctrl and yctrl can always read the latest values of the cutter positions since they do not need synchronized inputs. On the other hand, stts which has a synchronization constraint needs to get the synchronized inputs through the sampler task. Jitter control: In our experiments the eect of jitter was relatively small. However, this is not generalizable to all control systems, and it may be large in some systems. Thus, it will be necessary to carefully assess the impact of scheduling jitter on the controller's performance. Note that jitter control requires short deadlines, and sometimes large osets, as discussed in [2]. This may well lead to reduced schedulability. Where it is important to minimize output jitter for control quality, we can also tighten up the task period. This scheme also has its down side, i.e., increased utilization. In our experiment, the eect of output jitter was small and did not need special treatment. Utilization-directed period assignment: The period calibration method derives task periods such that the overall utilization is minimized. The rationale behind this is that it allows us to maximize the chances of obtaining the schedulable task set. However, Figure 14 suggests that utilization (or schedulability) should not be an objective, but a constraint. In our case, the real objective should be the minimization of contour errors. It is necessary that the period calibration method make a compromise between schedulability and performance. Thus the period assignment problem should be re-stated as below. For a given cuto utilization, the period calibration method assigns each task a period such that the output tasks have the tightest periods and the system uti-


lization is no greater than the cuto utilization. This in turn requires a new optimization algorithm for the period assignment problem.

6 Conclusion In this paper we reported the experiments on a CNC controller which we implemented using the period calibration method. Our experiments revealed that average sensor-to-output latency and loop processing periods were the two most dominating factors on control quality. Based on our analysis, we proposed the mixed communication scheme for intertask communication, and suggested a new objective function of minimizing loop processing periods for period assignment. There are many future research directions. First, the impact of input synchronization need to be investigated. In this experiment, we did not take into consideration input synchronization, though this was the very timing constraint that had forced us to use the harmonic queue scheme. We are currently extending the controller software so that synchronization constraints can play an important role in determining control quality. We will then proceed to study the interplay between sampling time skew and sensor-to-output latency. During the experiment, we witnessed that the derivation of end-to-end timing constraints itself involved making choices which had an impact on the nal schedulability. Thus we intend to push the period calibration method further so that the end-to-end constraints also can be derived from the given quality of control. To do so, we are working on the generalization of our CNC experiments. Finally, we are investigating new overload scheduling techniques in order to use it along with our period calibration tool. The harmonicity requirement of the period calibration tool leads to a real-time design in which tasks are executed in a phase-locked fashion. Consequently, a transient overload may make tasks out of phase seriously damaging the system. During the development of such overload scheduling techniques, our simulation workbench will provide a useful testbed where we can conduct various experiments simulating transient overloads and the scheduler's responses.

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[2] R. Gerber, S. Hong, and M. Saksena. Guaranteeing real-time requirements with resource-based calibration of periodic processes. IEEE Transactions on Software Engineering, 21(7):579{592, July 1995. [3] C. Liu and J. Layland. Scheduling algorithm for multiprogramming in a hard real-time environment. Journal of the ACM, 20(1):46{61, January 1973. [4] I. Na. Contour error analysis and gain tuning of position feedback controller for a CNC machining center. Master's thesis, Department of Control and Instrumentation Engineering, Seoul National University, February 1996. [5] J. Ready. VRTX: A real-time operating system for embedded microprocessor applications. IEEE Micro, 6(4):8{17, August 1986. [6] The Math Works, Inc. MATLAB User's Guide. The Math Works, Inc., August 1992.