Visualization of Fluid/Structure Interaction in IC ...

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 8, AUGUST 2012

1239

Visualization of Fluid/Structure Interaction in IC Encapsulation Chu Yee Khor, Mohd Zulkifly Abdullah, and Wei Chiat Leong

Abstract— This paper presents the visualization of the fluid/structure interaction (FSI) in molded integrated-circuit (IC) packaging. The complexity and high cost of the experimental setup in the molded packaging make the FSI visualization difficult during the encapsulation process, particularly for tiny and thinned chips in IC packages. To address this problem, we fabricated a scaled-up transparent molded package, and the encapsulation process was experimentally performed to visualize the FSI phenomenon. Two scaled-up (single- and stacked-chip) IC packages were considered in the experiment to investigate the FSI, flow front advancement, and void formation. The void formation mechanisms for both imitated IC packages were also studied. Moreover, finite-volume and finite-element codes, via the mesh-based parallel code coupling interface method, were used to describe the physics of FSI during the encapsulation. The predicted flow front advancement, flow profiles, and chip deformation were validated with the experimental results. Hence, this paper is expected to provide a better understanding of the FSI phenomenon during the IC encapsulation. Index Terms— Finite element (FE), finite volume (FV), fluid/structure interaction (FSI), integrated-circuit (IC) packaging.

I. I NTRODUCTION

T

HE RAPID development of recently introduced portable electronic devices, such as the iPad and iPhone 4S, has improved communication, internet surfing, and entertainment. Moreover, this development has resulted in the miniaturization and diversification of the integrated-circuit (IC) packaging technology. The high performance and compact design of IC packages have continued to challenge the engineer and package designer in maintaining the quality and reliability of the product. 3-D IC packaging [1] and integration [2] technologies have facilitated the development and design of IC packages to achieve miniaturization and high performance. Moreover, the application of thinned silicon and ultrathin chips [3] in 3-D packaging and integration has allowed designers to build compact and tiny packages. However, the reliability of the thinned chip may be reduced because of sequential processes, such as thinning and assembly. Thus,

Manuscript received November 23, 2011; accepted May 4, 2012. Date of publication June 14, 2012; date of current version July 31, 2012. This work was supported in part by the Ministry of Higher Education of Malaysia, and the My Brain 15 Ph.D. Scholarship Program. Recommended for publication by Associate Editor S. Ankireddi upon evaluation of reviewers’ comments. The authors are with the School of Mechanical Engineering, Universiti Sains Malaysia, Minden 14300, Malaysia (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TCPMT.2012.2199117

proper processing and packaging design, as well as efforts in maintaining the reliability of IC packages, are essential in the microelectronic industry. The IC encapsulation technology is widely used in the microelectronic industry for various types of IC packages, such as thin quad flat package [4], [5], thin-profile small outline package (54 L lead on chip) [6], [7], stacked-chip scale package [8], mold array package [9], molded underfill [10], and flip-chip underfill encapsulation [11]. During the encapsulation, the epoxy-molding compound (EMC) is transferred into the mold cavity using the transfer molding technique to protect the structures (silicon chip, solder bumps, lead frame, and wire bonding) from the hazardous environment (mechanical, chemical, thermal, etc.). The interaction of the EMC flow and structures occurs in this process, where the EMC fills the mold cavity containing the IC package. This occurrence may induce unintended defects and overstress the structures, thus diminishing the package reliability, particularly for thinned silicon chip applications. The fluid/structure interaction (FSI) phenomenon was also extensively reported in the encapsulation of the wire bonding IC package. The deformation of the wire bonding [12] and lead frame or paddle shift [13] causes the diminution of reliability. Therefore, the fundamental understanding of the FSI during molded packaging is important for the engineers and package designers. The visualization of the phenomenon occurring in the IC encapsulation process is difficult because of the expensive experimental setup. Generally, trial-and-error investigations are also costly and time consuming. With the rapid development of commercial software, engineers and package designers scrutinize the IC encapsulation process through virtual modeling. Thus, the phenomenon during the IC encapsulation process can be visualized, and the understanding of the packaging process can be improved. Virtual modeling tools, such as PLICE-CAD [4], FLUENT [14], C-MOLD [7], [15], Moldex3D [16], and Autodesk Moldflow Insight [17], have been utilized for various IC encapsulation processes to simulate the fluid flow. Moreover, computer-aided engineering software programs assist the predictions and improvements of the interaction between the wire bond [12], paddle shift [13], and EMC during the packaging process. Thus, the enhancement of IC packages can be achieved through virtual modeling, providing a better understanding of the physics of fluid flow in encapsulation. The FSI phenomenon during encapsulation is complicated, and the visualization in the actual packaging process is difficult and expensive due to several limitations, such as the

2156–3950/$31.00 © 2012 IEEE

1240

Fig. 1.

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 8, AUGUST 2012

Scaled-up model for stacked-chip package.

nontransparent mold, miniature package size, lack of advanced visualization equipment, and complex experimental setup even in the microelectronic industry. Therefore, the experiment and FSI simulation of scaled-up IC packages were conducted in this paper. Two imitated IC packages with single and stacking chips were considered to visualize the FSI phenomenon in the encapsulation process. The FSI occurrences were recorded. Furthermore, the virtual modeling technique was implemented to describe the physics of FSI for a single-chip package and to validate the results. In FSI modeling, finite-volume (FV) and finite-element (FE) codes were employed to simulate the fluid and structural analyses through the online coupling method via the mesh-based parallel code coupling interface (MpCCI) program [18], [19]. The fluid flow in the encapsulation was simulated using FLUENT 6.3.26. The forces induced from the fluid were sent to ABAQUS 6.9 for the instantaneous structural analysis. The present experiment and FSI simulation should provide the fundamental understanding and realistic predictions of the IC encapsulation process.

(a)

(b)

Fig. 2.

Experimental setup [19]. (a) Actual. (b) Schematic diagram.

Fig. 3.

Exploded view of the transparent mold [19].

II. P ROBLEM D ESCRIPTION The FSI in the encapsulation process may induce unintended features to the IC package and reduce the reliability. In addition, the limitations of IC packages, such as tiny package sizes, nontransparent molds, and costly experimental setup, complicate the FSI visualization during the encapsulation process. Therefore, a scaled-up transparent molded package was fabricated in this paper to enable a clear FSI visualization during the packaging process. Two types of imitated (single- and stacking-chip) IC packages were considered in the present experiment for a better visualization of the fluid-flow mechanism, FSI, and void formation. Fig. 1 illustrates the scaled-up IC package with an imitated stacking chip. Moreover, the FSI modeling was performed for the single-chip package to study the physics of FSI and validate the results. FV-based (FLUENT) and FE-based (ABAQUS) software programs were employed as the fluid and structural solvers and interfaced by the MpCCI program. III. E XPERIMENTAL S ETUP Fig. 2 shows the photograph and schematic of the experimental setup [19] reported in our previous work. As an extension of our previous work, the imitated single- and stacking-chip IC packages were considered in the present investigation, focusing on the FSI phenomenon during the encapsulation. A test fluid with constant viscosity of 4 Pa-s and density of 1067 kg/m3 was fed into the mold cavity

using the plunger system illustrated in Fig. 2. The system was set to obtain a constant pressure of 161.14 kPa for transferring the fluid into the cavity. The filling process of the mold cavity was recorded using a camera located in front of the transparent mold and was processed by a computer. The mold was fabricated from seven layers of transparent Perspex for better visualization. The exploded views of the mold are clearly depicted in Fig. 3. The scaled-up model of the IC package consists of an imitated chip, bump, and substrate properly located at the mold cavity. A thin plastic sheet was utilized as the material for the imitated single- and stacking-chip packages. As shown in Fig. 4, the scaled-up package is located at the cavity with 9 × 4.5 × 1.5 cm dimensions. The dimensions of the imitated chip were 7 × 3.5 × 0.02 cm, and the thickness of the imitated substrate was 0.5 cm. The diameter of the imitated bump was 0.4 cm, and the gap height was 0.3 cm. The imitated bumps were positioned in perimeter arrangement, as shown in Fig. 4. The experiment was focused on the FSI. Thus, the temperature effect was disregarded in the molding process. IV. G OVERNING E QUATIONS In the present FSI modeling, FV-based (FLUENT) and FE-based (ABAQUS) programs were utilized as solvers for the fluid and structural analyses. The basic idea of the FV analysis is through a control volume of the fluid domain

KHOR et al.: VISUALIZATION OF FLUID/STRUCTURE INTERACTION IN IC ENCAPSULATION

1241

the air phase decreases. Over time, the equation of the melt front is governed by the following transport equation:  2  ∂F ∂F ∂F ∂ F ∂2 F ∂2 F dF ∂F = +u +v +w − =0 + + dt ∂t ∂t ∂t ∂t ∂ x 2 ∂y 2 ∂z 2 (6) where F takes the value of 1 (F = 1) in cells containing only resin, 0 (F = 0) in cells void of resin, and a value between 0 and 1 (0 < F < 1) in “interface” cells (referred to as the resin melt front). Furthermore, the following momentum equation was used in ABAQUS to solve the structural deformation:  → → ∂u → → ↔ + u .∇ u = −∇ σ +ρs g (7) ρs ∂t

(a)

(b) Fig. 4. Detailed view of the imitated (a) single- and (b) stacked-chip IC packages.

defined as the mold cavity in the present modeling. During the encapsulation, the fluid flow in the mold cavity is described using 3-D incompressible flow transport equations, namely, mass conservation and Navier–Stokes, energy, and Newtonian fluid equations, which are given as follows. Continuity equation ∂v ∂w ∂u + + = 0. ∂x ∂y ∂z Navier-Stokes equation x-direction ∂u ∂u ∂u 1 ∂p ∂u +u +v +w =− ∂t ∂x ∂y ∂z ρ ∂x        ∂u ∂ ∂u ∂ ∂u ∂ η + η + η + ∂x ∂x ∂y ∂y ∂z ∂z

(1)

(2)

y-direction ∂v ∂v ∂v ∂v 1 ∂p +u +v +w =− ∂t ∂x ∂y ∂z ρ ∂y        ∂ ∂v ∂ ∂v ∂ ∂v + η + η + η ∂x ∂x ∂y ∂y ∂z ∂z z-direction ∂w ∂w ∂w 1 ∂p ∂w +u +v +w =− ∂t ∂x ∂y ∂z ρ ∂w        ∂ ∂w ∂ ∂w ∂ ∂w + η + η + η . ∂x ∂x ∂y ∂y ∂z ∂z

(3)

(4)

Newtonian fluid equation η=

τ γ˙

(5)

where τ is the shear stress and γ˙ is the strain rate. Moreover, the volume-of-fluid (VOF) model was used to track the flow front during encapsulation. In the modeling, the VOF treats air and fluid as two distinct phases and calculates the interface tracking of the fluid/air interface in the analysis. The computational domain consists of both fluid and air regions. As time increases, the fluid phase also increases and

→

where ρ s is the density of solid, u is the velocity of solid in → ↔ x-, y-, and z-axes, σ denotes the recoverable stresses, and g is the gravitational acceleration. V. FSI S IMULATION M ODELING The general idea of the FSI modeling is to simulate the interaction between the fluid and the structure or vice versa. In encapsulation, the flow of fluid into the cavity induced the forces acting on the structures located in the mold cavity. The FSI caused the deformation and stresses on the structures. Overstress and high structural deformation may initiate unintended defects to the sequential processes in IC packaging. In the present model, the fluid analysis was handled by FLUENT. However, the structural analysis was solved by ABAQUS. The structures (imitated chip, bump, and substrate) were defined as a coupling region for both solvers. During the simulation, MpCCI was used to couple the FLUENT and ABAQUS codes. The forces (pressure and shear forces) from FLUENT were transferred immediately to ABAQUS for analysis and vice versa. Further discussion on the FSI modeling is presented in the following sections. A. FLUENT Modeling The fluid domain of the mold cavity was created according to the dimension of the scaled-up package, as illustrated in Fig. 5. The boundary conditions are labeled in Fig. 5. The wall boundaries under no-slip condition were defined on the mold surface, substrate, chip, and bumps. The 3-D meshed model was generated using GAMBIT with 243 000 tetrahedral elements. The isothermal condition was assumed in the simulation, whereas the temperature effect was not considered in the experiment. Thus, the temperature of the model was set at room temperature. Moreover, this paper focuses on the FSI phenomenon until the final stage before the plunger is retracted from the fluid cylinder [18]. The boundary and initial conditions are defined as follows: 1) on the wall: u = v = w = 0; T = Tw , ∂p ∂n = 0; ∂v ∂w ∂T = = = = 0; 2) on center line: ∂u ∂z ∂z ∂z ∂z 3) on the melt front: p = 0; 4) at the inlet: p = pin (x, y, z) ; T = Tin .

1242

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 8, AUGUST 2012

TABLE I M ECHANICAL P ROPERTIES OF I MITATED C HIP, B UMP, AND S UBSTRATE Parameter

Fig. 5.

Boundary conditions and meshed model.

Fig. 6.

Detailed view of structural meshed model.

The VOF model was enabled in the fluid analysis to solve the air and fluid phases in the mold cavity. The VOF model solved a set of single-momentum equations that was shared by the fluid and the volume fractions of each of the fluids in the computational cell tracked throughout the domain [20]. A second-order upwind scheme was applied to resolve the momentum and volume-fraction equations. Furthermore, a SIMPLE algorithm was applied for pressure–velocity calculation. Implicit solution and time-dependent formulation were considered for the volume fraction in each time step. The optimum time step size of 0.001 was used in the analysis. The simulation took around 16 h to complete a case on an Intel Core i3 processor with i3-540, 3.07 GHz, and 3.24 GB of RAM. B. ABAQUS Modeling As mentioned earlier in this section, the coupling region was the imitated chip, bump, and substrate. Thus, the structures were created in actual dimensions and meshed using ABAQUS. The mesh of the structural model was generated using hexahedral elements via the sweep method, as shown in Fig. 6. The structures were defined as deformable in the consideration of mechanical aspects. In the modeling, some assumptions were considered depending on the experimental condition. The scaled-up IC package was properly located in the mold cavity in the experiment. Thus, the fixed-boundary condition was set at the bottom surface of the imitated substrate, as depicted in the front and side views. In addition, the basic assumptions in the FE analysis [21] were made for simplification purposes. Homogeneous and isotropic elastic behaviors [22], [23] were observed on the structures of the chip and bump, respectively. In the experiment, the bump and chip were perfectly bonded. The solder pad effect was neglected, and the solder pad was not considered in the scaled-up model. In the fluid analysis, no temperature effect was included in the experiment. Therefore, a thermal effect on the creep and

Elastic modulus, E (GPa) Poisson ratio, ν Solid density, ρ s (kg/m3 )

Fig. 7.

Imitated chip

Imitated bump

Imitated substrate

1.571

213

2.7

0.37

0.29

0.375

1180

7710

1170

Comparison between experimental and FLUENT results.

fracture behavior was disregarded in the present modeling [19]. The mechanical properties of the emulated chip, bump, and substrate are summarized in Table I. VI. R ESULTS AND D ISCUSSION A. Model Validation Fig. 7 depicts the comparison of the experimental and simulation results of the flow front advancement and flow profiles at various filling times. The FSI simulation results are substantiated by the experimental results, and the flow profiles and flow-front advancement agreed for both results. In addition, the predicted chip deformation is compared with the maximum deformation, as shown in Fig. 8. The filling at various stages and the deformation of the chip are compared in Fig. 9. The experimental and simulation results show that the chip deformation profiles are nearly identical in shape. The deformation in the middle region of the imitated chip, which is not supported by the bump, was evaluated, as shown in Fig. 9(b). The average discrepancies found are only 1.87% and 0.65% for the fluid and structural analyses, respectively. Therefore, the present modeling yields realistic predictions to tackle the FSI problems of the IC packaging. B. FSI 1) Single-Chip Package: The FSI phenomenon during the encapsulation process was investigated through the current experiment. The entire process was recorded and processed using a computer, as presented in Figs. 10–12. In the encapsulation process, the FSI causes the deformation of the imitated chip. Fig. 10(a) and (c) demonstrates the initial condition

KHOR et al.: VISUALIZATION OF FLUID/STRUCTURE INTERACTION IN IC ENCAPSULATION

1243

(a)

(b)

(c)

(d)

Fig. 10. Initial condition and deformed chip. (a) Initial condition. (b) Deformation of imitated chip (almost 70% covered by fluid). (c) Detailed view of initial condition. (d) Detailed view of deformed chip.

Fig. 8.

Deformation of imitated chip in experimental and predicted results. (a)

(b)

(c)

(d)

100

Time (%)

80 60

Experiment FLUENT

40

Fig. 11. Detailed view of deformed chip at different filling stage in encapsulation. (a) Deformation of chip (nearly 90% covered by fluid). (b) Deformed chip when fluid totally filled the cavity. (c) Detailed view of deformed chip (nearly 90% covered by fluid). (d) Detailed view of deformed chip (cavity filled).

20 0

0

2

4

6

8

10

Flow front advancement (cm)

(a) 2.5

Deformation (mm)

2.0 Experiment ABAQUS

1.5 1.0 0.5

Fig. 12. Initial condition and upward deformation of imitated chip edge when chip was nearly covered by fluid (90%).

0.0 -10

0

10

20 30 40 Position (mm)

50

60

70

(b) Fig. 9. Comparison of experimental and FSI simulation results. (a) Fluid analysis. (b) Structural analysis.

and the detailed view of the scaled-up package, where the chip is positioned properly without any initial deformation. However, the feeding of the test fluid caused the deformation of the imitated chip, as depicted in Fig. 10(b) and (d). Obvious deformation was found at almost 70% of chip covered by the fluid. The chip deformation was concentrated at the no-bumpsupported region, as shown in Fig. 10(d). The unbalanced filling process occurred, whereas the flow front above the top of the chip (upper stream) moved faster than the flow beneath the chip (lower stream). This situation is attributed to the design of the gap height between the chip and the substrate or the bump standoff height. As a result, the unstable flow front caused the pressure difference and unbalanced forces acting on the imitated chip and, thus, deformation. The downwardly deformed chip is shown in Fig. 11(a) and (c) when nearly 90% of the chip is covered by fluid.

The narrow space underneath the chip resists the fluid flow, as compared with the wide space at the top of the chip. Moreover, the chip deformation reduced the gap height. This incident increased the resistance to the lower stream. The slower flow front is shown in Fig. 11(c). Fig. 11(d) shows that the mold cavity is approximately filled. Meanwhile, an incomplete filling is observed beneath the chip. The unfilled region contributed to the deformation of chip even though the cavity was almost filled with fluid. Furthermore, an upward deformation was observed in the chip edge nearer to the inlet gate, as shown in Fig. 12. This deformation is attributed to the continuous flow from the inlet gate and perhaps the reaction of the chip structure where the deformation is spotted somewhere in the middle region. 2) Stacked-Chip Package: The investigation of the encapsulation was extended to the scaled-up stacking-chip package illustrated in Fig. 4. Fig. 13 shows the flow-front advancement during the feeding process. At the initial stage, the stacking chip was located properly in the mold cavity, as depicted in Fig. 13(a). The fluid flow into the cavity initiates the FSI around the chip edge [Fig. 13(b)]. In Fig. 13(c)–(f), the fastest flow front is observed at the upper stream, followed

1244

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 8, AUGUST 2012

(a)

(b)

(c)

(d)

Fig. 15. Deformation of imitated chip in middle and edge regions. (a) Deformation of chip (nearly 90% covered by fluid). (b) Deformed chip edge (cavity totally filled). (c) Detailed view of deformed chip. (d) Detailed view of slightly deformed chip edge. Fig. 13. Encapsulation process of stacking chip. (a) Initial condition. (b)–(g) Feeding of fluid into the cavity. (h) Cavity completely filled.

(a)

(b)

(c)

(d)

Fig. 14. Initial view and deformed chip. (a) Initial condition. (b) Deformed imitated chip (nearly 50% of cavity filled). (c) Detailed view of initial condition. (d) Detailed view of deformed chip.

by middle and lower streams. This phenomenon is attributed to the intermediate spaces between the chip and the substrate. The fluid more freely flows through the free space at the upper stream than those at the other two streams. The comparison of the initial view and chip deformation is presented in Fig. 14. The details of the downward deformation of the chip are shown in Fig. 14(d), when almost 50% of the chip is covered by the fluid. According to the investigation, the deformation is found in the middle region of the chip that is not supported by the bump. When the upper stream flow front covered 90% of the chip, the deformation was still concentrated in the middle region, as shown in Fig. 15(a) and (c). A deformation due to the unstable flow front is observed, as discussed in Section VI-B1. Meanwhile, only a small downward deformation is found at the edge of the chip, which is closer to the outlet [Fig. 15(d)] when the stacking chip is totally covered by the fluid. The increase in the number of bumps can effectively reduce the chip deformation around the middle region [24]. Therefore, a proper IC package design could maintain the package reliability and minimize the unintended defects during the encapsulation process. 3) Physics of FSI for Single-Chip Package: The present FSI modeling was substantiated with the experimental results, as previously discussed in this section. In this section, the predicted FSI result is discussed in terms of fluid-flow advancement, deformation profile, and stress distribution during the encapsulation process. Fig. 16 illustrates the simulation results of the FLUENT and ABAQUS solvers at various stages, whereas the flow-front advancement and deformation profile are presented in different columns. The filled and unfilled

Fig. 16.

Predicted FSI results for single-chip package.

regions of flow-front advancement are labeled in the FLUENT result. The top and side views of the deformation of the imitated chip are also shown. The initial interaction was identified when the fluid interacted with the imitated chip (at 32.3% of the time) and caused the sudden deformation around the edge of the chip. The continuous feeding from the inlet gate enabled the fluid flow to be distributed in the cavity. As the flow-front advancement increased, the chip structure deformed, as shown in the stages at 48.4% and 64.5%. The fluid caused the forces (pressure and shear forces) to act upon the structures, subsequently causing the deformation. In addition, factors, such as the unstable flow front, also contributed to the unbalanced forces that were distributed on the single chip’s structure, as mentioned in Section VI-B1. However, in the actual molded packaging, the deformations of the chip were also correlated with the inlet pressure [18], gap height or bump standoff height [19], and solder bump shape design and number of bumps [24]. Moreover, the unbalanced forces also subjected the structures to stress during the encapsulation process. The stress distribution on

KHOR et al.: VISUALIZATION OF FLUID/STRUCTURE INTERACTION IN IC ENCAPSULATION

1245

(a)

(b) (a)

(b) (c)

(d) (c)

(d)

Fig. 17. Stress distribution on the imitated chip during encapsulation process varied with percentage of filling time (a) 32.3, (b) 48.4, (c) 64.5, and (d) 80.6.

(a)

(b)

(c)

(d) Fig. 18. Void formation in imitated single-chip package. (a) Faster flow front at upper stream. (b) Fluid totally covered imitated chip. (c) Flow front almost filled the cavity. (d) Air traps below the imitated chip.

the imitated chip is shown in Fig. 17. The stress distribution on the structure corresponded to the flow-front advancement. The stress was concentrated on the chip region supported by the bump because of the compression force acting on the chip’s structure. Furthermore, the overstress [18] on the IC structure may induce the initial defects on the successive manufacturing processes. Thus, the proper process control of the encapsulation process is necessary to minimize the deformation and stress concentration, particularly on thinnedchip applications in IC packaging. C. Void Formation The void formation on the IC package could cause the diminution of package reliability. Several factors, such as air traps and moisture content and high viscosity of EMC, cause void formation. A void initiates the delamination [25], which propagates from the small void at the interface of the IC package. In the actual IC packaging, the void formation is normally identified through the inspection process. Void formation during the process is difficult to visualize because of several limitations, such as miniature size of the IC package,

Fig. 19. Air traps in stacking-chip package. (a) Faster flow front at upper stream. (b) Fluid almost covered upper imitated chip. (c) Middle and lower streams still unfilled. (d) Air traps in middle and lower streams.

nontransparent molding, and expensive experimental setup. Hence, a scaled-up and transparent mold is necessary to visualize the mechanism of void formation. Figs. 18 and 19 demonstrate the void formation during the scaled-up encapsulation process for the single- and stackingchip packages, respectively. From the experimental result, an unstable flow front during the encapsulation caused the air traps beneath the chip, whereas a faster flow front is observed at the upper stream for the single-chip package. A similar phenomenon was also observed for the stackingchip package, as shown in Fig. 19. In addition, the effect of obvious chip deformation on the single-chip package to the flow-front advancement was studied. The chip deformation in the middle region caused a resistance of the fluid flow underneath the chip. This incident caused the incomplete filling, as shown in Fig. 18(d). Moreover, a larger void was found in the stacking-chip package, which was caused by the unstable flow front in the upper, middle, and lower streams during the filling process. Thus, applications of multi-inlet [5] and optimized inlet positions [10] could effectively eliminate the void formation in actual IC packaging. VII. C ONCLUSION Studies on FSI visualization during molded packaging processes were carried out for the scaled-up single- and stacking-chip packages. The experiment was undertaken to investigate the FSI phenomenon, flow-front advancement, and void formation during the IC encapsulation. The obvious deformation in the single-chip package was mainly attributed to the unstable filling, and the deformation caused the resistance to the flow, resulting in the void formation at the bottom of the imitated chip. Moreover, the middle region of the chip, which was not supported by the bump, experienced a downward deformation. Meanwhile, the edge of the chip closer to the inlet gate was deformed upwardly. A slight deformation was identified for the stacking-chip package. The results showed that the stacking-chip package had a larger void formation due to the unbalanced filling in the streams during encapsulation. The unstable filling in the packaging induced the differences in the forces acting on the chip and caused the

1246

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING AND MANUFACTURING TECHNOLOGY, VOL. 2, NO. 8, AUGUST 2012

deformation for both experiments. The present experimental studies provided a better understanding of the visualization of FSI and void formation during the encapsulation process. Furthermore, the physics of the FSI was described using the MpCCI coupling method for FV and FE codes. The predicted flow-front advancement, flow profiles, and chip deformation matched well with the experimental results. Hence, the modeling technique yielded reliable predictions in solving the complex FSI during IC encapsulation. ACKNOWLEDGMENT The authors would like to thank D. Ramdan for the technical support. R EFERENCES [1] K. N. Tu, “Reliability challenges in 3D IC packaging technology,” Microelectron. Rel., vol. 51, no. 3, pp. 517–523, 2010. [2] J. H. Lau, “TSV manufacturing yield and hidden costs for 3D IC integration,” in Proc. 60th Electron. Compon. Technol. Conf., Las Vegas, NV, Jun. 2010, pp. 1031–1042. [3] J. N. Burghartz, W. Appel, C. Harendt, H. Rempp, H. Richter, and M. Zimmermann, “Ultrathin chip technology and applications, a new paradigm in silicon technology,” Solid-State Electron., vol. 54, no. 9, pp. 818–829, 2010. [4] L. Nguyen, C. Quentin, W. Lee, S. Bayyuk, S. A. Bidstrup-Allen, and S.T. Wang, “Computational modeling and validation of the encapsulation of plastic packages by transfer molding,” J. Electron. Packag., vol. 122, no. 2, pp. 138–146, 2000. [5] C. Y. Khor, M. Z. Abdullah, M. K. Abdullah, M. A. Mujeebu, D. Ramdan, M. F. M. A. Majid, Z. M. Ariff, and M. R. A. Rahman, “Numerical analysis on the effects of different inlet gates and gap heights in TQFP encapsulation process,” Int. J. Heat Mass Transf., vol. 54, nos. 9–10, pp. 1861–1870, 2011. [6] R. Y. Chang, W. H. Yang, E. Chen, C. Lin, and C. H. Hsu, “On the dynamics of air-trap in the encapsulation process of microelectronic package,” in Proc. Annu. Tech. Conf., Apr. 1998, pp. 1178–1180. [7] R. Y. Chang, W. H. Yang, S. J. Hwang, and F. Su, “Three-dimensional modelling of mold filling in microelectronics encapsulation process,” IEEE Trans. Compon. Packag. Technol., vol. 27, no. 1, pp. 200–209, Mar. 2004. [8] C. Y. Khor, M. K. Abdullah, M. Z. Abdullah, M. A. Mujeebu, D. Ramdan, M. F. M. A. Majid, and Z. M. Ariff, “Effect of vertical stacking dies on flow behavior of epoxy molding compound during encapsulation of stacked-chip scale packages,” Heat Mass Transf., vol. 46, nos. 11–12, pp. 1315–1325, 2010. [9] T. Schreier-Alt, F. Rehme, F. Ansorge, and H. Reichi, “Simulation and experimental analysis of large area substrate overmolding with epoxy molding compounds,” Microelectron. Rel., vol. 51, no. 3, pp. 668–675, 2011. [10] M. W. Lee, W. K. Jung, E. S. Sohn, J. Y. Lee, C. H. Hwang, and C. H. Lee, “A study on the rheological characterization and flow modelling of molded underfill (MUF) for optimized void elimination design,” in Proc. Electron. Compon. Technol. Conf., May 2008, pp. 382–388. [11] C. Y. Khor, M. Z. Abdullah, M. A. Mujeebu, and F. C. Ani, “Finite volume based CFD simulation of pressurized flip-chip underfill encapsulation process,” Microelectron. Rel., vol. 50, no. 1, pp. 98–105, 2010. [12] W. R. Jong, Y. R. Chen, and T. H. Kuo, “Wire density in CAE analysis of high pin-count IC packages: Simulation and verification,” Int. Commun. Heat Mass Transf., vol. 32, no. 10, pp. 1350–1359, 2005. [13] S.-Y. Teng and S.-J. Hwang, “Simulations and experiments of threedimensional paddle shift for IC packaging,” Microelectron. Eng., vol. 85, no. 1, pp. 115–125, 2008. [14] C. Y. Khor, M. Z. Abdullah, M. A. Mujeebu, and F. C. Ani, “FVM based numerical study on the effect of solder bump arrangement on capillary driven flip chip underfill process,” Int. Commun. Heat Mass Transf., vol. 37, no. 3, pp. 281–286, 2010. [15] D. H. Bae, M. C. Lee, E. S. Lee, H. C. Yun, J. C. Lim, and I. B. Kim, “Simulation of encapsulation process for BGA type semi-conducting microchip,” J. Ind. Eng. Chem., vol. 9, no. 2, pp. 188–192, 2003.

[16] H. Wang, H. Zhou, Y. Zhang, and D. Li, “Stabilized filling simulation of microchip encapsulation process,” Microelectron. Eng., vol. 87, no. 12, pp. 2602–2609, 2010. [17] H. Wang, H. Zhou, Y. Zhang, D. Li, and K. Xu, “Three-dimensional simulation of underfill process in flip-chip encapsulation,” Comput. Fluids, vol. 44, no. 1, pp. 187–201, 2011. [18] C. Y. Khor, M. Z. Abdullah, and F. C. Ani, “Study on the fluid/structure interaction at different inlet pressures in molded packaging,” Microelectron. Eng., vol. 88, no. 10, pp. 3182–3194, 2011. [19] C. Y. Khor, M. Z. Abdullah, H. J. T. Tan, W. C. Leong, and D. Ramdan, “Investigation of the fluid/structure interaction phenomenon in IC packaging,” Microelectron. Rel., vol. 52, no. 1, pp. 241–252, 2012. [20] Modelling Multiphase Flow. Lebanon, NH: Fluent Inc., Sep. 2006, ch. 23. [21] R. S. Chen, S. C. Tseng, and C. S. Wan, “Effects of solder joint structure and shape on thermal reliability of plastic ball grid array package,” Int. J. Adv. Manuf. Technol., vol. 27, nos. 7–8, pp. 677–687, 2006. [22] P. J. G. Schreurs, “Fatigue damage in solder joints,” in Proc. 5th World Congr. Comput. Mech., Vienna, Austria, Jul. 2002, pp. 1–10. [23] J.-W. Kim, D.-G. Kim, and S.-B. Jung, “Investigations of the test parameters and bump structures in the shear test of flip chip solder bump,” Thin Solid Films, vol. 50, nos. 1–2, pp. 4405–4409, 2006. [24] C. Y. Khor, M. Z. Abdullah, and W. C. Leong, “Fluid/structure interaction analysis of the effects of solder bump shapes and input/output counts on moulded packaging,” IEEE Trans. Compon., Packag. Manuf. Technol., vol. 2, no. 4, pp. 604–616, Apr. 2012. [25] A. A. O. Tay and T. Y. Lin, “Influence of temperature, humidity and defect location on delamination in plastics IC packages,” IEEE Trans. Compon. Packag. Manuf. Technol. A, vol. 22, no. 4, pp. 512–518, Dec. 1999.

Chu Yee Khor received the Bachelors degree in mechanical engineering and the Masters degree in computational fluid dynamics, specializing in integrated-circuit packaging from Universiti Sains Malaysia, Minden, Malaysia, in 2008 and 2010, respectively. He is currently pursuing the Ph.D. degree from the Universiti Sains Malaysia, in advanced packaging in microelectronics. His current research interests include electronics packaging, fluid/structure interaction, fluid mechanics, dynamics, polymer rheology, and heat and mass transfer.

Mohd Zulkifly Abdullah received the Bachelor’s degree in mechanical engineering from the University of Wales, Swansea, U.K., and the M.Sc. and Ph.D. degrees in fluid dynamics from the University of Strathclyde, Glasgow, U.K. He has been a Professor of mechanical engineering with Universiti Sains Malaysia, Minden, Malaysia, since 2010. He has published numerous papers in international journals and conference proceedings. His current research interests include computational fluid dynamics, heat transfer, electronics packaging, and electronics cooling.

Wei Chiat Leong received the Bachelors degree in mechanical engineering (First Class Hons.) from Universiti Sains Malaysia, Minden, Malaysia, in 2010, where he is currently pursuing the Ph.D. degree in electronic packaging, specializing in the area of flexible printed circuit boards. His current research interests include fluid mechanics, computational fluid dynamics, structural analysis, finite element methods, fluid and structure interactions, and electronics packaging. Mr. Leong is an Active Member of the Institution of Engineers Malaysia. He is registered under the Board of Engineers Malaysia.