VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark Sudip Ghosh1, Somsubhra Talapatra1, Debasish Mondal1, Navonil Chatterjee1, Hafizur Rahaman1, and Santi P. Maity2 1
School of VLSI Technology, Bengal Engineering and Science University, Shibpur, India {sudip_etc,rahaman_h}@yahoo.co.in, {s_talapatra,mondal_debasish86}@rediffmail.com,
[email protected] 2 Department of Information Technology, Bengal Engineering and Science University, Shibpur, India
[email protected]
Abstract. In this paper we propose a spatial domain Spread Spectrum (SS) watermarking scheme which effectively eliminates security problem while increasing robustness and enhancing perceptual quality of watermarked image. VLSI implementation using Field Programmable Gate Array (FPGA) has been developed for the algorithm. Keywords: VLSI, FPGA, Spread Spectrum, Digital Watermarking.
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Introduction
The objective of this paper is to design VLSI architecture for the given image watermarking algorithm that caters to the need of media authentication as well as secure transfer of image [2]. In this paper, the architecture that has been created for the given Spread Spectrum watermarking algorithm [1], enables watermarking to be implemented instantaneously at the time of capturing the image rather than using a software procedure that calls for greater execution time.
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Proposed Method
The following subsection describes different steps in watermark embedding process respectively. Here, grey-scale watermark is embedded directly to the pixel values of each block of the cover image using SS modulation [3]. 1. The cover image is taken as F, where F = {Fij, 1≤ i ≤Flength, 1≤ j ≤ Fwidth}, while Fij ∈ {0, 1,..,255},where Flength= image length and Fwidth=image width. 2. The watermark image is taken as W, where W = {Wij, 1≤ i ≤Wlength, 1≤ j ≤ Wwidth}, while Wij ∈ {0,1,..,15}, where Wlength= length and Wwidth = width. 3. The partitioning of the cover and watermark image into NxN non overlapping blocks where N = 2,4,8,16 etc. H. Rahaman et al. (Eds.): VDAT 2012, LNCS 7373, pp. 375–376, 2012. © Springer-Verlag Berlin Heidelberg 2012
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4. The PN (Pseudo Noise) sequence generated S = {s1, s2,…..,sLxL}, si ∈ {0, 1}. 5. The embedding rule is given as: Fe = F + KS Fe = F - KS
if bj = ‘0’ if bj = ‘1’
The architecture of the proposed watermark algorithm is shown in figure below.
Fig. 1. Datapath of the Embedding Unit
We consider a 4 bits/pixel of size (64 x 64) and 8bits/pixel of size (256 x 256) grayscale images as watermark and the cover image respectively for experiment purpose. The cover image is partitioned in (8 x 8) non-overlapping blocks and the watermark image is partitioned in (2 x 2) non-overlapping blocks. The synthesis of the watermark embedding have been implemented on Xilinx (ISE version8.1) based FPGA. We have chosen Virtex series of FPGA to fit the complexities of the design. The device used is xc2vp30-7ff896 for the implementation and the language used is VHDL. The behavioral simulation was done with Synopsys VCSMX to verify the functionality of the design. The power consumption is 650 mw and the maximum frequency is 82.204 MHz.
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Conclusion
The algorithm is simple with low computation cost and can be easily implemented in hardware. Digital design of the proposed algorithm using FPGA is also developed and thus makes it suitable for real time authentication as well as secured communication.
References 1. Ghosh, S., Ray, P., Maity, S.P., Rahaman, H.: Spread Spectrum Image Watermarking with Digital Design. In: IEEE International Advance Computing Conference (IACC 2009), pp. 868–873 (2009) 2. Mohanty, S.P.: A secure digital camera architecture for integrated real-time digital rights managements. Journal of Systems Architecture: the EUROMICRO Journal Archive 55(1012) (October 2009) 3. Cox, I.J., Kilian, J., Leighton, F.T., Shamoon, T.: Secure spread spectrum watermarking for multimedia. IEEE Transactions on Image Processing 6(12), 1673–1687
