An Efficient VLSI Architecture for Fingerprint

An Efficient VLSI Architecture for Fingerprint Recognition using O2D-DWT Architecture and Modified CORDIC-FFT Satish S Bhairannawar1, Sayantam Sarkar2, Raja K B3 and Venugopal K R4 1,2

Department of Electronics and Communication Engineering, Dayananda Sagar College of Engineering, Bangalore, India 3 Department of Electronics and Communication Engineering, UVCE, Bangalore, India 4 Principal, University Visvesvaraya College of Engineering, Bangalore University, Bangalore, India 1 [email protected],[email protected]

Abstract— The real time biometric systems are used to authenticate persons for various applications. In this paper, we propose an efficient VLSI architecture for fingerprint recognition using O2D-DWT architecture and modified CORDIC-FFT. The O2D-DWT architecture is designed using only adders and shifters for high speed operation and is applied on fingerprint image to generate four sub-bands. The optimized Fast Fourier Transform (OFFT) architecture is designed by computing different twiddle factor angles using modified CORDIC processor and is applied on LL sub-band coefficients to generate final fingerprint features. The test fingerprint features are compared with features of fingerprint images in database using Euclidean Distance. It is observed that the performance of proposed architecture is better compared to existing architectures. Keywords— Fingerprint based biometric system, Optimized 2DDWT architecture, Optimized FFT architecture, Modified CORDIC processor, FPGA.

I. INTRODUCTION In today's networked world, the authenticity of human beings becoming increasingly important since (i) to differentiate criminals and non-criminals. (ii) to identity status of a person like Government employee, Public sector employee, Private sector employee, Big business person, Small business person etc. (iii) to regulate economy of nation by avoiding black money transactions. (iv) elimination of credit and debit card and currency notes to avoid fraudulent and robbery. (v) to maintain database of human being. The traditional method of identifying persons are smart card, PIN, token, password etc. These technologies can be lost or stolen hence are not preferred to use. The recent technology uses biometrics to identify a person which alternates the use of traditional methods. The biometric traits are attached to human body, hence it can’t be lost or stolen. The biometric characteristics are broadly classified into two categories [1] as (i) Physiological characteristics which are part of human body such as iris, fingerprint, palm print, face etc. (ii) Behavioral characteristics which an action and behavior of a person such as voice, keystroke etc. are variable in the lifetime of a person. Fingerprint based identification is one of the most important biometric technology, which has drawn a substantial amount of attention recently, since the process of acquiring fingerprint samples are simple and also believed to be unique among individual person. These essential attributes of

fingerprint samples leads to the use of automatic fingerprint based identification in both civilian and military applications. Paulino et al., [2] have proposed descriptor based Hough transform for fingerprint matching. This approach determines similarity between fingerprints by considering both minutiae and orientation field information. Rong Wand and Bir Bhanu [3] have proposed predicting fingerprint biometrics performance from a small gallery. In this approach a binomial model approach is used to predict both the fingerprint and identification performance. The match and non-match rates are computed using the number of corresponding triangles as the match metric. Shankar Bhausaheb Nikam and Suneeta Agarwal [4] have proposed fingerprint anti-spoofing based detection using ridgelet energy transform. The matching comparisons of each person ridgelet energy and co-occurrence signatures were determined and also testing was done using discrete classifiers. The features of fingerprint image can be extracted by applying (i) Spatial domain technique: in which features of an image are accomplished directly on pixel values. (ii) Transform domain technique: in which any transform is applied on original image to get a transformed image to extract transform domain features. The most commonly used transform domain techniques [5] are Discrete Wavelet Transform (DWT), Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT), Dual Tree Complex Wavelet Transform (DTCWT) etc. The DWT has been extensively used for image processing and support image comparison. The DWT uses sub-band coding techniques which employs filtering methods with different cut-off frequencies at different scale. The main advantages of using DWT are time-frequency resolution and multilevel image decomposition. The DWT mainly uses two sets of FIR filters i.e., low pass filter and high pass filter where the output of each filter is a sub-band. The different types of mother wavelets used in DWT are Haar, CDF-5/3, CDF-9/7 etc. The low pass filter output generates approximation coefficients which have significant information of an image and high pass filter output generates detailed coefficients which has difference information of an image. Most of the available DWT architectures are based on linear convolution property of the wavelet filters. The lifting scheme of DWT computation has become more popular compared with convolution based technique for its lower computational complexity [6]. However, the lifting based

wavelet decomposition has several streamlined features like inplace computation, integer to integer wavelet transform, symmetric forward and inverse transform. Many lifting based architectures have been suggested for efficient hardware implementation of 2D-DWT. In the subsequent we briefly discuss a few of them. Andra et al., [7] proposed four-processor architecture for 2D-DWT. These architectures are used for block based implementation for 2DDWT, which requires large memory. Liao et al., [8] proposed 2D-DWT dual scan architecture, which requires two lines of data samples simultaneously for forward 2D-DWT and also proposed another 2D-DWT architecture, which accomplished decomposition of all stages which result in inefficient hardware utilization and more sophisticated control circuitry. Barua et al., [9] proposed folded based architecture for 2D-DWT by using hybrid level at each stage. In this approach the image is scanned in a raster format by using row processor. The proposed raster scanning decreases the speed of entire structure. The Fast Fourier Transform (FFT) algorithm [10 11] is used to compute discrete Fourier transform in much faster speed than standard DFT algorithm. The output of FFT consists of complex valued coefficients which have both real and imaginary coefficients which gives both phase and magnitude information. The main advantages of using FFT is to reduce the number of computations needed for N points from O(N²) to O(Nlog2N). Some of commonly used FFT algorithms are radix-2, radix-4 etc., which can be used as decimation in time (DIT) and decimation in frequency (DIF).

and Keshab K. Parhi [16] in which the directions of all microrotations are pre-computed maintaining a constant scale factor and also avoiding the examination of the sign of the angle after each iteration. Pramod K. Meher et al., [17] have proposed application based and multi-dimensional CORDIC implemented for higher radix. The output of optimized FFT block provides a set of additional robust feature which consists of phase information required for accurate matching. The recent development of reprogrammable hardware with incorporation of general purpose microprocessor unit for automated fingerprint identification proves to be efficient and economical solution. Mariano Fons et al., [18] proposed FPGA based personal verification system using fingerprints in which they performed an evaluation of system architectures substitute to existing personal computers.

II. PROPOSED ARCHITECTURE The fingerprint recognition system using optimized 2DDWT architecture and optimized FFT architecture with modified CORDIC is proposed, as shown in the Fig. 1.

Different FFT architectures have been implemented to transform data vectors from time domain to frequency domain and vice-versa. Pei-Chen and Yu-Yun Lee [12] proposed real time implementation of the split-radix FFT algorithm to efficiently construct local butterfly modules. In this proposed method the efficiency of the algorithm increases with the FFT size. Chih-Peng Fan and Guo-An Su [13] proposed the grouped scheme for FFT implementation which has fewer complex multiplications to accelerate computational speed and can be implemented with properties of sharing hardware and standard structures. COordinate Rotation DIgital Computer is abbreviated as CORDIC [14] works based on the iterative formulation for different operation modes and planner coordinate systems. CORDIC has two operating modes such as rotation mode and vectoring mode. The rotation mode used to calculate sine and cosine functions for a particular angle and the vectoring mode used to compute phase and magnitude of a given coordinate. CORDIC algorithm has many advantages over traditional techniques. It is used for a large class of applications for its efficient and low cost implementation where trigonometric functions are used. Various CORDIC architectures have been proposed for trigonometric computations. The CORDIC algorithm has implemented using branching method [15] for best VLSI implementation. This CORDIC method accomplishes parallel two classic CORDIC rotations, which gives a constant normalization factor. A pre-computation based rotation CORDIC algorithm has been proposed by Martin Kuhlmann

Fig. 1: Block Diagram of Proposed Method

A. Database Image The fingerprint database of FVC2004 is considered to test the performance of biometric system. The DB3 database of FVC2004 [19] has 8 fingerprint samples per person. The total

numbers of persons in the DB3 are 100 with 8 sample images per person. The original size of each fingerprint is 300x480 and is resized to 256x256, which is suitable for hardware implementation. B. Optimized DWT Architecture The Cohen, Daubechies and Feauveau (CDF-5/3) wavelet filter is used to implement one level 2D-DWT architecture. The CDF-5/3 filter uses 5-taps for low pass filter and 3-taps for high pass filter using shifters and adders. 1). Optimized 1D-DWT (O1D-DWT) Architecture The one level DWT is used to compress fingerprint image to reduce the memory size and decrease computation time. The basic equations for low pass and high pass FIR filters [7] are given in equations (1) and (2) 0.5 x

y y

0.25 y

x

x

(1)

x

y

(2)

Where x is the input signal value and y is the output transformed signal values. a) Low Pass Filter using Shift and Add Operation The impulse response of 5-taps FIR filter is considered as hLPF n

0.125,0.25,0.75,0.25, 0.125

The output of low pass FIR filter is given in equation (3). yLPF n

∑

yLPF n

xn 2 xn 1 2 xn 3 xn 4

hLPF n x n

yLPF n 3 xn 1 xn 2

k

(3) 2

2 xn

2

2 xn

4

1 xn 1 1 xn 3

Fig. 2: O1D-DWT Architecture

2). Optimized 2D-DWT (O2D-DWT) Architecture The O1D-DWT architecture is extended to derive O2DDWT architecture using memory units and controller units as shown in Fig. 3. The LPF and HPF coefficients from O1DDWT Block-1 are stored in the two memory unit blocks of O2D-DWT architecture in parallel. The stored L-band and Hband coefficients in memory unit-1 and memory unit-2 respectively are further processed simultaneously using both O1D-DWT Block-1 and O1D-DWT Block-2 simultaneously to obtain sub-bands of LL, LH, HL and HH through MUX and DEMUX. The O1D-DWT Block-1 is used for obtaining HL and HH sub-bands and O1D-DWT Block-2 is used to generate LL and LH sub-bands. The controller unit is used to synchronize the operation of all blocks. The optimized O2DDWT architecture has high speed due to parallel processing of all sub-blocks compared to existing techniques.

(4) Where () indicates Left shift and Right shift respectively. b) High Pass Filter using Shift and Add Operation The impulse response of 3-tap FIR filter is considered as hHPF n

0.25,0.5, 0.25

Where n=1 to 3 The output of the high pass FIR filter is given in equation (5) yHPF n yHPF n

∑

hHPF n x n

2 xn xn 3

1

k

(5) 1 xn

2

(6)

The equations (4) and (6) corresponding to low pass and high pass filters are modified using only shift and add operations required for optimization with respect to area and speed. The Optimized 1D-DWT architecture designed using adders and shifters are shown in Fig. 2.

Fig. 3: O2D-DWT Architecture

C. Optimized FFT (OFFT) Architecture The FFT is applied on LL band coefficients generated by O2D-DWT block to generate FFT coefficients as final features of fingerprint. The OFFT architecture consists of 8 point Decimation in Input (DII-FFT) block and modified CORDIC block to generate twiddle factor as shown in the Fig. 4.

Fig. 5(b):Pre-processing Unit (Comparators Block)

Fig. 4: OFFT Architecture

The Proposed OFFT uses Modified CORDIC to generate twiddle factor for predefined angles and observed that it avoids ROM based and Look Up Table method of storage. This results in high speed operation of FFT block with less hardware and also the output provides a set of additional robust feature which consist rapid change of phase information required for accurate matching. D. Modified CORDIC Unit The modified CORDIC is designed to compute angles from 0° to 360° by using pre-processing block and existing CORDIC block [14,15] as shown in the Fig. 5(a). The comparator is used as pre-processing unit for angles greater than 90° by using trigonometric functions as shown in Fig. 5(b). The output of the comparator is fed to CORDIC unit to obtain the values of x and y which is used by comparators to calculate the Sinθ and Cosθ for angle 0° to 360°.

E. Matching The cosine and sine components of FFT are compared using Euclidean distance (ED) between database image and test image. The Euclidean distance is between images are calculated using equation (7). ED

D i

T i

D i

T i

(7)

Where, Dc(i)=Cosine component of Database images Tc(i)=Cosine component of Test images Ds(i)=Sine component of Database images Ts(i)=Sine component of Test images III. PERFORMANCE ANALYSIS The proposed architectures are implemented on FPGA device using Virtex xc5vlx110t-3ff1136 with speed grade -3. The Table 1 shows the device utilizations of FFT, O2D-DWT, Modified CORDIC and total Fingerprint Recognition System. It is observed that the clock rate is high for the proposed architecture. TABLE I. DEVICE UTILIZATION SUMMERY

Fig. 5(a): Modified CORDIC

Performance

FFT

O2DDWT

Modified CORDIC

Fingerprint Recognition System

No. of Slice Register

0

301

32

34804

No. of Slice LUTs

309

9424

380

41249

LUT-FF Pairs

0

229

16

18428

No. of DSP48Es

12

0

0

40

Clock Rate (MHz)

----

258.358

1084.952

56.686

The FFT block consists of 309 slice LUTs and 12 DSPs which is used to implement multiplication function on FPGA.

The proposed O2D-DWT block consists of 301 slice registers, 9424 slice LUTs and 229 flip-flop pairs with maximum operating frequency of 258.358 MHz. The Modified CORDIC block consists of 32 slice registers, 380 slice LUTs and 16 flipflop pairs. The maximum operating frequency of this block is 1084.952 MHz. The total Fingerprint Recognition System consists of 34804 slice registers, 41249 slice LUTs, 18428 flipflop pairs and 40 DSPs. It is observed that the maximum operating frequency of entire system is 56.686 MHz which is less than individual blocks, since the proposed system uses more DSP blocks for synchronization which reduces operating frequency of the proposed block than individual blocks. The estimated clock rate in MHz using FPGA of the proposed algorithm and existing algorithms are given in Table 2. The proposed method works faster at maximum clock rate of 56.686 MHz compared to existing techniques.

[2]

[3]

[4]

[5] [6]

[7]

[8] TABLE II.CLOCK RATE COMPARISONS OF PROPOSED METHOD WITH EXISTING TECHNIQUE Author

Technique

Clock Rate (MHz)

Marion Lopez and Enrique Canto [20]

Minutiae Based

40

Alilla et al.,[21]

Rectangular Grid

25

Proposed Method

O2D-DWT and Modified CORDIC

56.686

[9]

[10]

[11] [12]

The Performance of proposed architecture is better compared to existing architecture for the following reasons as (i) the O2D-DWT is implemented using only shifters and adders and (ii) the OFFT is realized by computing twiddle factor using modified CORDIC processor.

IV. CONCLUSION The biometric systems are designed using efficient VLSI architecture for identification of persons. In this paper, an efficient VLSI architecture for fingerprint recognition using O2D-DWT and modified CORDIC-FFT is proposed. The O2D-DWT architecture is designed using only adders and shifters for developing low and high pass FIR filters. The efficient FFT architecture is developed by computing twiddle factor angles using modified CORDIC processor and is applied on LL band coefficients to generate final features of fingerprint images. The features of test fingerprint are compared with features of images in the database using Euclidean Distance. It is observed that, the performance of proposed real time architecture is better compared to existing architectures. In future high speed spatial domain architecture can be developed and combined with high speed frequency domain architecture to design efficient real time biometric systems. REFERENCES [1]

R. Bolle, J. Connell, S. Pankanti, N. Ratha and A. Senior, “Guide to Biometric”, Springer Professional Computing Series, 2004.

[13]

[14] [15]

[16]

[17]

[18]

[19] [20]

[21]

A. A. Paulino, J. Feng. and A. K. Jain, “Latent Fingerprint Matching using Descriptor-Based Hough Transform”, IEEE Transactions on Information Forensics and Security, Vol. 8, No. 1, pp. 31-45, January 2013. Rong Wang and Bir Bhanu, “Predicting Fingerprint Biometrics Performance from a Small Gallery”, Pattern Recognition Letters, Elsevier, Vol. 28, pp. 40–48, 2007. Shankar Bhausaheb Nikam and Suneeta Agarwal, “Fingerprint AntiSpoofing using Ridgelet Transform”, Second IEEE International Conference on Biometrics: Theory, Applications Systems, pp. 1-6, 2008. Rafael C. Gonzalez, Richard E. Woods and Steven L. Eddins, “Digital Image Processing”, Pearson Education, 2004. Tinku Acharya and Chaitali Chakrabarti, “A Survey on Lifting-Based Discrete Wavelet Transform Architectures”, International Journal of VLSI Signal Processing, Springer, Vol. 42, pp. 321–339, 2006. Kishore Andra, Chaitali Chakrabarti and Tinku Acharya, “A VLSI Architecture for Lifting-Based Forward and Inverse Wavelet Transform”, IEEE Transaction on Signal Processing, Vol. 50, No. 4, pp. 966–977, April 2002. H. Liao, M. K. Mandal and B. F. Cockburn, “Efficient Architectures for 1-D and 2-D Lifting-Based Wavelet Transforms”, IEEE Transaction on Signal Processing, Vol. 52, No. 5, pp. 1315–1326, May 2004. S. Barua, J. E. Carletta, K. A. Kotteri and A. E. Bell, “An Efficient Architecture for Lifting-Based Two-Dimensional Discrete Wavelet Transform”, Integration VLSI Journal, Vol. 38, No. 3, pp. 341–352, 2005. John G. Proakis and Dimitris G. Manolakis, “Digital Signal Processing Principles, Algorithms and Applications”, Prentice Hall of India, Fourth Edition, 2008. Monson H. Hayes, “Digital Signal Processing”, Tata McGraw Hill, Second Edition, 2009. Pei-Chen Lo and Yu-Yun Lee, “Real Time Implementation of SplitRadix FFT Algorithm to Efficiently Construct Local Butterfly Modules”, International journal on Signal Processing, Elsevier, Vol. 71, pp. 291-299, 1998. Chih-Peng Fan and Guo-An Su, “Pruning Fast Fourier Transform Algorithm Design using Group-Based Method”, International journal on Signal Processing, Elsevier, Vol. 87, pp. 2781–2798, 2007. Shaoyun Wang and Vincenzo Piuri, “A Unified View of CORDIC Processor Design”, Kluwer Academic Publishers, pp.121-160, 1997. Jean Duprat and Jean-Michel Muller, “The CORDIC Algorithm: New Results for Fast VLSI Implementation”, IEEE Transaction on Computers, Vol. 42, No. 2, pp. 168-177, February 1993. Martin Kuhlmann and Keshab K. Parhi, “P-CORDIC: A Precomputation Based Rotation CORDIC Algorithm”, International Journal on Applied Signal Processing, Hindwai Publication Corporation, pp. 936–943, 2012. Pramod K. Meher, Javier Valls, Tso-Bing Juang, K. Sridharan and Koushik Maharatna, “50 Years of CORDIC: Algorithms, Architectures and Applications”, IEEE Transaction on Circuits and Systems, Vol. 56, No. 9, pp. 1893-1907, September 2009. Mariano Fons, Francisco Fons, Enrique Canto and Mariano Lopez, “FPGA – Based Personal Authentication using Fingerprints”, International Journal of Signal Processing Systems, Springer, 2011. http://bias.csr.unibo.it/fvc2004/download.asp [Online], “FVC 2004 Database Reference”, Third Fingerprint Verification Competition, 2004. Mariano Lopez and Enrique Canto, “FPGA Implementation of a Minutiae Extraction Fingerprint Algorithm,” Biometric Signal Processing Conference, pp. 21-25, September 2008. A. Alilla, M. Faccio, T. Vali, G. Marotta and L. DeSantis, “A New Low Cost Fingerprint Recognition System on FPGA,” IEEE International Conference on Industrial Technology, pp. 988-993, February 2013.