Voltage Synchronization Scheme Based on Zero Crossing Detection for Parallel Connected Inverters in AC Microgrids M. Azrik, K.H. Ahmed, S.J. Finney, and B.W. Williams Department of Electronic and Electrical Engineering Strathclyde University, Glasgow, UK E-Mail:
[email protected] Tel: +44 (0)141 548 2124 Fax: +44 (0)141 552 2487 Abstract— A new voltage synchronization scheme is proposed for parallel connected inverters in AC microgrids. Instead of using the same reference voltage for all inverters, this scheme directly synchronizes the reference voltage of a connecting inverter to the point of common coupling voltage. Two contactors are used with each inverter module to enable the inverter to operate in 4 different modes. Voltage synchronization using this scheme requires no control interconnection among parallel connected inverters. Experimental results validate the practicality of the proposed synchronization schemes. Index Terms— Inverter, microgrid, voltage synchronization, zero crossing detection try
I. INTRODUCTION The increasing number of distributed energy resources (DERs), especially in developed countries, requires proper and systematic coordination among them. Microgrid concepts have been introduced to coordinate the DERs in a more decentralized way [1], thereby offering improved service reliability, better economics, and a reduced dependency on the utility [2, 3]. In a microgrid system, proper current distribution and load sharing strategies are essential to achieve reliable parallel operation. Many control techniques have been introduced to solve the problems associated with parallel operation. In general, the control methods can be categorized as wireless control and active load sharing [4]. Wireless control is also known as droop control [5-8], has advantages in terms of simplicity and reliability as it requires no interconnection among inverters and is only based on local measurements. However, there is a well-known drawback in which an inherent trade-off exists between output voltage regulation and power sharing accuracy. In the last decade, attention has been given to improving the droop control method for microgrid application. The improvements can be classified into modified droop [6], adaptive droop [7] and combined droop [8], which have significantly improved droop control performance. On the other hand, active load sharing control [9-11], requires some control intercommunication among the parallel connected inverters for information sharing. It can be
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classified as circular-chain control, master-slave control and average current control. In circular-chain control [9], successive inverter modules track the current of the previous inverter to achieve equal current distribution. In master-slave control [10], the master module regulates the microgrid voltage and provides the output current reference for other modules. The slave modules act as current source inverters to share the power with the master module. Although performance is acceptable, this control lacks reliability as it is dependant on the master module. If the master module malfunctions, the whole system fails. Average current control [11] enables all the parallel connected inverters to take part in voltage, frequency and also current regulation. In this technique, the parallel system can be flexible, redundant and also hot swappable at any time. Implementation of average current control requires synchronization of the reference voltage (Vref) for each parallel connected inverter module. Several approaches have been proposed to get proper voltage synchronization [12-15]. In [12], the authors utilize a synchronization control unit (SCU) that uses microcontroller to generate a synchronous signal and sends it to each parallel connected inverter in every line cycle. This approach depends on the SCU and the synchronization is affected if the SCU fails. In [14], a synchronization bus, that contains the wiredAND results of a square wave generated by each module, is used. The synchronization signal is then sent to each module for Vref synchronization. There is also precondition controlling of the frequency of the synchronization signal for stabilizing it to the fundamental frequency. In [15], the authors use a synchronization bus that contains the average value of Vref from all modules. Each inverter sends a Vref signal to the bus through an averaging circuit. The average signal is then sent back to each module and the zero crossing instant of this signal is used to adjust the Vref generation. A phase locked loop (PLL) approach is adopted in [13]. PLL is a technique which enables one signal to track the phase of another signal. It allows an output signal to synchronize with a reference input signal in phase and frequency [16]. However, there are drawbacks in term of implementation complexity and it is inherently noise sensitive. Furthermore, the loss of synchronization can occur 588
during distorted or unbalanced voltages. In this paper, a voltage synchronization scheme for parallel connected inverters in an AC microgrid is proposed. A new zero crossing detection based technique approach is used for synchronization. Instead of having the same Vref for all inverters, this scheme directly synchronizes the Vref of a connecting inverter to the point of common coupling voltage, Vpcc. This synchronization method requires no control interconnection among parallel connected inverters. However, a specific procedure and hardware is needed for successfully implemented. One inverter needs to set up the voltage in the microgrid. When this voltage is established, the other connecting inverters can synchronize their Vref to this voltage. Two hardwire contactors are added to each inverter module to enable the inverter to operate in 4 different modes. This paper is organized in six sections. The system structure and proposed synchronization scheme is discussed in the second and third sections respectively. The fourth section covers the zero crossing detection technique used in the proposed scheme. The fifth section presents the experimental results to validate the advantages of the proposed technique. The last section concludes this paper. II. SYSTEM STRUCTURE Some control schemes, such as average current control, require synchronization of Vref for each parallel connected inverter module. In simulation, this is a simple implementation task because the same sine wave generator can be used for all parallel connected modules. There is no phase or frequency difference in the generation of Vref. However, in hardware, using the digital signal processor (DSP), the implementation is not that straightforward. The following issues need to be addressed. 1) Clock cycle difference among the DSPs • There is a small difference in the clock cycle of different DSPs. • Although the difference is small, over millions of cycles, this difference accumulates to be significant. • For Vref generation, this results in changing of the generated Vref frequency. 2) The phase angle difference • The phase angle of the generated Vref depends on the instant when the DSP starts the voltage generation build up. • If the starting time differs between inverters, the phase will differ. To successfully implement voltage synchronization of parallel connected inverters, a configuration as in Fig. 1 is used. Each module consists of a single phase sinusoidal pulse width modulation (SPWM) inverter, output power filter, and two contactors. The first contactor is placed after the output power filter, followed by the second contactor. The output voltage and current are sensed between the two contactors. The measured voltage is sent to the reference voltage
Fig. 1. Proposed parallel inverter configurations.
generator (RVG) to generate Vref. The output voltage, output current, and Vref are then sent to the controller. The controlled signal from this controller is passed to the SPWM modulator to generate gate drive signals for the inverter. The reason for two ac contactors with each module, is to enable the inverter to operate in 4 different modes. 1) Mode 1 • Both contactors A and B are opened. • Inverter is not connected to the microgrid. • Inverter is not generating voltage. 2) Mode 2 • Contactor A remains open and Contactor B is closed. • Inverter is not connected to microgrid. • Inverter is not generating voltage. 3) Mode 3 • Contactor B is open and Contactor A is closed. • Inverter is not connected to microgrid. • Inverter is generating voltage. 4) Mode 4 • Contactor A remains closed and Contactor B is closed. • Inverter is connected to the microgrid. • Inverter is generating voltage. • Inverter supplies power to microgrid. III. VOLTAGE SYNCHRONIZATION SCHEME The synchronization flow chart is shown in Fig. 2. Before
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voltage is defined as follows:
Vref (k ) E sin k
(3)
where the angle (k) is given by k k 1 360 f T ( k ) if k 360
(4)
k k 360
where f is the system fundamental frequency and T(k) is the switching period. In normal operation T(k) is fixed. However, in the synchronization process, this value is adjusted to offset the clock cycle difference among the different parallel connected inverter DSPs. While the inverter is still in Mode 2, it detects the zero crossing of Vpcc. This is the point when Vpcc changes from –ve to +ve. At this point, the inverter resets (k) to 0 to ensure that Vref is in phase with Vpcc. At this stage, Vref and Vpcc waveforms will be same as in Fig. 3(a). For the ideal case where there is no clock cycle difference between DSPs, this will be the end of the synchronization process. The inverter can be changed to Mode 3, ready to be connected to the microgrid. However, this is usually not the case. The clock cycle difference makes the frequency of Vref differ slightly from Vpcc. If Vref frequency is slightly lower, the Vref waveform moves to the right of the Vpcc waveform as shown in Fig. 3(b). If Vref frequency is higher, its waveform moves to the left of the Vpcc waveform as shown in Fig. 3(c). From these observations, some corrective actions should be taken. Vpcc Vref
Fig. 2. Synchronization flow chart
the synchronization process starts, the voltage must be already established in the microgrid network. Inverters measure the Vpcc and if there is no voltage available, the inverter can switch to Mode 4 and starts to establish the voltage using a predefined Vref. Otherwise if the voltage is already established in the microgrid, the inverter starts the synchronization process from Mode 2. The connecting inverter in Mode 2 tracks the peak amplitude of Vpcc.
(a)
(5)
Zero Crossing of Vpcc
Vpcc Vref
if Vpcc _ max ( j ) V pcc ( k ) V pcc _ max ( j ) Vpcc (k )
Vdiff
(1)
else Vpcc _ max ( j ) Vpcc _ max ( j )
(b)
Vpcc Vref
where Vpcc(k) is the instantaneous value of Vpcc and Vpcc_max is the peak instantaneous Vpcc. j is the number of measured peak samples. Several samples of peak value are measured and averaged to reduce the effect of noise in the measurements. The averaged peak value is given by E
V pcc _ max (1) V pcc _ max (2) ... V pcc _ max ( j ) j
(2)
Then the inverter generates the Vref based on E. The reference
Vdiff
Zero crossing of Vpcc (c) Fig. 3. Vref and Vpcc waveforms. (a) Vref and Vpcc in phase with each other. (b) Vref have lower frequency than Vpcc. (c) Vref have higher frequency than Vpcc.
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Frequency synchronization can be achieved using ResetWait-Measure-Change procedural loops. After generating Vref and setting (k) to 0, Count(k) is set to 0. This is the counter of the frequency synchronization loops. The system then waits for tx seconds, which is the time to observe the behavior of Vref and then measure the voltage difference Vdiff(k). Vdiff(k) is defined as follows:
Vdiff (k ) Vpcc (k ) Vref (k ) There are 3 possible values for Vdiff(k). The value is 0 if the frequency of Vref and Vpcc are the same. If Vref frequency is higher than Vpcc, Vdiff(k) will be +ve and if Vref frequency is lower than Vpcc, Vdiff(k) will be –ve as shown in Fig. 3 parts (b) and (c) respectively. For the +ve value of Vdiff(k), the switching period T(k) is increased to increase Vref frequency while for –ve Vdiff(k), the switching period T(k) is decreased to decrease Vref frequency as shown in the following equations. if Vdiff 0 T (k ) T (k 1) X (k ) (6) if Vdiff 0 T (k) T (k 1) X (k) where X(k) is the offset value. The initial value of X(k) is chosen large enough to change the polarity of Vdiff at the second loop cycle. (k) is then reset back to 0 to ensure Vref is in phase again with Vpcc. The process continues with calculating the next cycle value of X(k), namely X (k 1) ½ X (k )
produces the time elapsed from the previously detected zerocrossing instant as a feedback signal to the network [18]. Although this method gives competitive performance, it is complex and difficult to implement. Using an averaged instantaneous voltage can give a good approximation of the real instantaneous value. Several instants of instantaneous voltage are measured during one switching cycle and then averaged to get the average value. The average instantaneous voltage is given by V (k )
V ( k1 ) V ( k 2 ) ... V ( k n ) n
(9)
where V(kn) is the n th instant of the instantaneous voltage and n is the total of measured instants. The more measurements, the better the approximation. However, the control bandwidth of the controller should be taken into consideration. More measurements consume control bandwidth. The zero crossing detection is now based on this averaged instantaneous voltage value. To detect the zero crossing of the voltage, the previous cycle value V(k-1) is required. The controller then starts to locate the zero crossing by searching for the following conditions: V (k 1) 0V AND V (k) 0V (10) However, in practice, it is difficult to meet ideal conditions. It is not possible to get an exact 0 value for V(k). A more attainable ;condition can be used:
(7)
V (k 1) 0V AND V (k ) 0V AND V (k ) 0.1 V (11)
This condition specifies that V(k-1) should be –ve while V(k) should fall within the range 0 to 0.1. This is a close enough approximation for the zero value. The controller (8) might need a number of cycles to locate a V(k) value that Count (k ) Count(k ) 1 meets these conditions. However, for a fast DSP this The DSP checks whether Count(k) is smaller or equal to the detection process might take a few milliseconds. specified number of loops required, N. The frequency V. HARDWARE IMPLEMENTATION synchronization loops repeats if Count(k) has not reach N and A microgrid consisting of two single phase IGBT inverters proceeds to the next stage when N is reached. Normally the and a local load is used to demonstrate the practicality of value of N is selected to be more than 10 to get satisfactory voltage synchronization based on the zero crossing method. results. This is because after 10 iterations, X(k) converges to The hardware arrangement is shown in Fig. 4. Each inverter 0.1% of its initial value. is controlled by an Infineon TriCore™ TC1796B. System After the synchronization process, the inverter moves to parameters are listed in Table I. Mode 3 in which it generates a voltage based on the new TABLE I synchronized Vref. The inverter is now ready to be connected SYSTEM PARAMETERS to the microgrid. Description Symbol Value The next cycle value of X(k) is set to be half the present value so that the value converges after several loops. Count(k) is then incremented:
IV. ZERO CROSSING DETECTION This section presents the zero crossing detection approach used. The zero crossing detection method used is based on the measurement of the voltage and locating the zero crossing of the instantaneous voltage which is the instant when the voltage changes from –ve to +ve as shown in Fig. 3(b). Due to the use of switching devices, noise problems are unavoidable. Noise will affect the accuracy of the zero crossing detection [17]. To solve the noise issue, an author proposed a neural network structure and a logic circuit which
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DC link voltage
VDC
200 V
Reference voltage
Vref
110 Vrms
Switching frequency
fsw
4.2 kHz
System frequency
f
60 Hz
Filter inductance
Lf
1 mH
Filter capacitance
Cf
20 F
Initial switching period
T(0)
2.381 e-4 s
Initial offset value
X(0)
1.0 e-7 s
Waiting time
tx
5s
Counter limit
N
11
Inverter 1 Contactor 1B
Contactor 1A
Gate Driver
ADC
DSP Tricore 1796B
VDC
Load
Vpcc V2
V1
I1
V2
I2
Voltage and Current Sensors
5 ms/div,
Vpcc : 50 V/div,
V2 : 50 V/div
(a)
Contactor 2B
Inverter 2
Contactor 2A
Gate Driver
ADC
DSP Tricore 1796B
Voltage and Current Sensors
VDC
Vpcc V2
Fig. 4. Hardware arrangement.
5 ms/div,
Vpcc : 50 V/div,
V2 : 50 V/div
(b) Vpcc V2
Fig. 6. Vpcc and V2 waveforms with the frequency synchronization. (a) just after the phase reset and (b) after 20 minutes.
5 ms/div,
Vpcc : 50 V/div,
V2 : 50 V/div
(a)
Vpcc V2
V2 Vpcc 5 ms/div,
Vpcc : 50 V/div,
V2 : 50 V/div
(b) Fig. 5. Vpcc and V2 waveforms without the frequency synchronization. (a) just after the phase reset and (b) after 90 seconds.
The system starts with Inverter 1 in Mode 2, which measures the voltage at microgrid. Because the voltage is not established, Inverter 1 changes to Mode 4 and starts to generate voltage based on the specified value in Table 1. Inverter 2 is now ready to start the synchronization process. In Mode 2, it detects the availability of the Vpcc and starts to track its peak amplitude, E. This peak value is used to generate Vref. It then locates the zero crossing of Vref and resets (k) to 0 at that instant. This makes Vref in phase with Vpcc. However, due to DSP clock cycle differences, there is slight different in frequency between these two waveforms.
To demonstrate the clock cycle difference effect on the voltage generation, frequency synchronization is bypassed. Inverter 2 uses the same switching period, T as Inverter 1 which is 2.381e-4 s, changes to Mode 3 after resetting (k) to 0 and starts to generate its output voltage, V2. Fig. 5 parts (a) and (b) show Vpcc and V2 waveforms just after the phase reset and after 90 seconds, respectively. In Fig. 5(b), V2 waveform moves towards the right. This indicates that the clock cycle of Inverter 2 DSP is slower than the clock cycle of Inverter 1 DSP, thus giving V2 a lower frequency than Vpcc. To solve this issue, frequency synchronization steps are applied. Using the frequency synchronization steps, Inverter 2 seeks the best switching period, T that can offset the difference in clock cycle. After loops of the Reset-Wait-Measure-Change steps, the new switching period becomes 2.381131e-4 s. Inverter 2 then moves to Mode 3 and generates voltage at its output using the new Vref. Fig. 6 parts (a) and (b) show Vpcc and V2 waveforms just after phase reset and after 20 minutes respectively. From these results it is seen that the voltage synchronization process is able to find the best parameter for reference voltage generation which can offset the clock cycle difference between the DSPs. Even after 20 minutes, V2 still maintains synchronization with Vpcc. A desired performance feature in parallel operation is hotswap operation capability [4]. The proposed 2 contactor hardware arrangement of this technique is suited for hot-swap operation. By switching ON and OFF contactor B of any inverter, the inverter can be connected and disconnected respectively from the microgrid. Fig. 7 parts (a) and (b) show 592
synchronized by resetting the angle (k) to 0 when the DSP locates the zero crossing of Vpcc. Experiments using two parallel connected inverters confirm the practicality of the voltage synchronization scheme.
I1
I2
Ipcc
[1] [2]
Vpcc
50 ms/div,
I1 : 2 A/div,
I2 : 2 A/div,
Ipcc : 2 A/div, Vpcc : 100 V/div
[3]
(a) [4]
I1
I2
[5]
I pcc
[6] Vpcc
[7] 50 ms/div,
I1 : 2 A/div,
I2 : 2 A/div,
Ipcc : 2 A/div, Vpcc : 100 V/div
(b) Fig. 7. I1, I2, Ipcc and Vpcc waveforms under different operational conditions. (a) Inverter1 in Mode 4 and Inverter 2 entering Mode 4 from Mode 3 and (b) Inverter1 in Mode 4 and Inverter 2 entering Mode 3 from Mode 4
inverter 1 output current, I1, inverter 2 output current, I2, point of common coupling current Ipcc and Vpcc under different operational conditions. Fig. 7(a) shows the waveforms when inverter 2 enters Mode 4 from Mode 3 while inverter 1 is supplying current to the load. The waveforms when both inverters are supplying current to the load and inverter 2 enters Mode 3 from Mode 4 are shown in Fig. 7(b). This figure indicates a smooth transition at the moment inverter 2 ceases supplying current to the load, without disrupting Ipcc and Vpcc. The proposed synchronization scheme is not only easy to implement but also produces good performance as shown by the experimental results. VI. CONCLUSION This paper has proposed a new voltage synchronization scheme for parallel connected inverters in an AC microgrid. It is based on zero crossing detection of Vpcc. This synchronization method requires no control interconnection among parallel connected inverters. Two ac contactors are added to each inverter module to enable the inverters to operate in 4 different modes. The concept of the scheme is to synchronize Vref of a connecting inverter to Vpcc. The synchronization is classified into amplitude, frequency and phase synchronization. The amplitude is synchronized by measuring the averaged peak amplitude of Vpcc and uses this value as the amplitude for Vref. Frequency synchronization is achieved by adding an offset value X(k), to the switching period T(k) to compensate for clock cycle differences among DSPs. The phase is
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
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