A Voltage-Based Leakage Current Calculation Scheme ... - IEEE Xplore

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A Voltage-Based Leakage Current Calculation Scheme and its Application to Nanoscale MOSFET and FinFET Standard-Cell Designs Zia Abbas, Antonio Mastrandrea, and Mauro Olivieri, Member, IEEE

Abstract— Logic-level estimators of leakage currents, in nanoscale standard-cell-based designs, are relevant for the dramatic speed advantage with respect to analog SPICE-level simulation. We propose a novel logic-level leakage estimation model based on the characterization of voltages at the internal nodes of digital cells, in conjunction with the characterization of leakage currents in a single field-effect transistor (FET) device and with the input-dependent Kirchhoff current law expression of the total current in the cell topology. The voltage-based nature of the approach simplifies the inclusion of supply voltage variation/scaling impact, as well as of output voltage drop (loading effect), on leakage currents. The method has been implemented in hardware description language models of a complete cell library. Exhaustive tests report average accuracy below 1% error in 22-nm CMOS and 20-nm FinFET technologies, when compared with SPICE BSIM simulation results. Index Terms— Leakage current, standard cells, VLSI.

I. I NTRODUCTION

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N DIGITAL nanoscale standard-cell-based design flows, the prediction of speed and energy consumption of a given design with reliable accuracy is a primary concern. SPICE-level circuit simulations represent the most accurate technique for predicting both propagation delays and energy consumption, at the expense of a very long computation time. Therefore, techniques have been developed to predict speed and power at the logic level by means of logic-level models for propagation delays and energy consumption. As for propagation delay estimation, fast and accurate logic-level delay calculators are presently well integrated in standard-cell-based design flows [19]. For energy consumption, an accurate logic-level computation is a challenging task in nanoscale technologies, especially for static power, as the various leakage current sources exhibit dissimilar dependencies on temperature, cell input values, technology parameters, and they are significantly affected by voltage fluctuations [13]. SPICE-level leakage analysis of complex designs is simply unfeasible. Efficient leakage power calculators have been Manuscript received May 10, 2013; revised September 27, 2013; accepted December 3, 2013. This work was supported by the JU ENIAC under Grant 120214 END Project funded by the European Commission. The authors are with the Department of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome, Rome 00185, Italy (e-mail: [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2013.2294550

proposed in the last years, either based on dedicated analytical physical models of the relevant leakage currents in a cell or based on offline SPICE characterization of the currents in typical circuit structures or in library cells as functions of input logic values [29]. We propose a leakage calculation model based on the offline characterization of the voltage profiles at the internal circuit nodes of the cells, in conjunction with the offline characterization of the currents in a single device (e.g., a MOS transistor or a FinFET). The method supports separate calculation of gate leakage, subthreshold leakage, and junction leakage, including input pattern dependence, stacking effects, and loading effects As for any logic-level estimation tool (e.g., PrimeTime PX), the rationale of the proposed approach is to match as closely as possible SPICE accuracy in the estimated power of a design, starting from a SPICE-level characterization of the basic devices [28], [29]. The work does not propose a new analytical model of leakage currents to be compared with measurements on fabricated devices, but rather a new characterization and simulation approach built upon SPICE-level models. At present, available analytical models integrated in SPICE, namely BSIM4 [10] and BSIM-CMG [27], have been widely verified against TCAD simulation and physical measurements [30] and have been adopted as reference models by the Compact Model Council [26] contributed by the major semiconductor companies. The contributions of the proposed voltage-based leakage calculation scheme with respect to the state of the art are: 1) with respect to present logic-level commercial estimators (e.g., PrimeTime PX) based on current lookup tables, the method improves accuracy discriminates different leakage components and supports loading effect; 2) with respect to research works on logic-level leakage estimation, the method outperforms previously published algorithms as for accuracy, reaching less than 1% error with respect to SPICE. In addition, in the proposed paradigm, the inclusion of voltage scaling and loading effects in the leakage estimation is straightforward, while in existing approaches, the latter are calculated by iterative computations [25]–[16]. The technique is feasible for implementation in a hardware description language (HDL) environment or as a standalone calculator operating on value change dump trace files. In this perspective, the proposed work can be seen as an innovative

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characterization approach of standard cell libraries, which could be integrated into a simulation engine like PrimeTime PX. Our present implementation relies on Very High Speed Integrated Circuits Hardware Description Language (VHDL)coded cell models. Although the approach is applicable in any field-effect transistor (FET) technology, we report the case of 22-nm planar bulk CMOS cells and 20-nm bulk FinFET. This paper is organized as follows. Section II analyzes the related works, Section III introduces the new paradigm for leakage calculation, Section IV details the characterization phases, Section V discusses the results obtained on estimation accuracy, and Section VI summarizes the conclusion. II. BACKGROUND AND R ELATED W ORKS In nanoscale digital circuits, several leakage phenomena in FET devices can contribute to total static power dissipation, depending on the specific technology, such as MOSFET, FinFET [18], Carbon Nano-Tube FET (CNFET) [9], and so on. In MOS devices, at least seven physical phenomena have been accounted [24]; yet, in digital CMOS below 65-nm node, gate leakage, subthreshold leakage, and body leakage have been recognized as the dominant types [2] and are the focus of estimation/reduction techniques. In FinFET devices, only subthreshold drain-tosource tunneling is significant while gate oxide tunneling and drain/source to body conduction are substantially reduced [18]. Overall, the various leakage types in FET devices behave differently from each other with temperature and circuitlevel countermeasures, so that it is of interest to individually estimate the impact of each type in a given circuit design. All of the major leakage current components show an approximately exponential dependence on the voltages at the terminal nodes implicated [24]. As a consequence, while a very accurate characterization of leakage currents in a single FET is straightforward, this is not the case for connected transistors in generic digital cells, due to two effects affecting node voltages and therefore the actual currents flowing in the devices: the stacking effect and the loading effect. The former occurs whenever transistors are stacked in a drain–source series connection, and strongly affects all leakage components due to the substantial change in the node voltages [1]. The latter occurs when the gate leakage of a cell driven by another cell is high enough to induce a voltage drop/rise on the output terminal of the driving cell, thus affecting the leakage currents in both [16] and [25]. A preliminary version of the proposed approach for CMOS cells is in [1]. There have been previous researches in estimating total leakage currents at both gate and circuit level in CMOS designs. D’Agostino et al. [8] describe an analytical approach to model statistical variations of total leakage currents in circuit level netlists. Mukhopadhyay et al. [17] accurately modeled total leakage current in logic gates, neglecting loading effect. Rao et al. [23] reported an efficient technique for estimating gate leakage current by performing a logic-state-based analysis of the transistors; however, their

analysis is limited to gate leakage only and loading effects are not considered. Similarly, Rahman and Chakrabarti [20] proposed a technique focused on gate leakage without considering stacking and loading effects. Mukhopadhyay et al. [16] finally introduced an estimation technique for the loading effect, based on an iterative calculation. In [25], Sanyal et al. presented the STABLE methodology for the estimation of subthreshold, gate, and junction leakage calculating the loading effects using a Newton–Raphson iteration method. In FinFET designs, physical device-level models of leakage are available [4], showing that subthreshold current is dominant over gate and body currents. In [6], a thermal model for FINFET-based NAND , NOR, and inverter is presented, for predicting thermal runaway, considering dynamic and static power, the latter based on a previous model of subthreshold leakage in double-gate FETs. In [11], Gu et al. present an analytical model of statistical standard deviation of leakage currents, taking into account the inherent quantization of FinFET device width. The results refer to single devices, and are compared with TCAD simulations. In [21], a more comprehensive analytical model of single FINFET devices is elaborated, including gate and subthreshold leakage currents subjected to process variations. The results are compared with the numerical and experimental data. Such work is complementary with respect to the proposed work, as it may be used as an alternative to BSIM-CMG for the single device current characterization phase (Section IV-A). In [3], Agostinelli et al. report a comprehensive physical-level analysis (through DESSIS device simulator, now Synopsys Sentarus) of an inverter, a ring oscillator, a tapered buffer, and a mirror full adder, with the target of investigating the effects of stacking and other circuit design techniques on leakage. In [15], Mishra et al. develop empirical leakage current macromodels for single FINFET devices and NAND / NOR gates, extracted from Sentaurus TCAD simulation data; they build a thorough mathematical model of leakage statistical behavior in spatially correlated layouts of NAND / NOR cell grids, and apply it to circuit benchmarks synthesized as NAND – NOR, to effectively optimize the predicted leakage by proper cell replacements. The accuracy of the predicted results in the benchmark circuits is not compared with any TCAD or SPICE simulation. Yet, the macromodel developed in n. 17 may be used in our approach as an alternative to BSIM-CMG for the single device current characterization phase. In [5], dedicated abstract models based on response surface methodology have been proposed to predict leakage behavior of FinFET standard cells with process variations. The abstract model is tuned on TCAD simulations and the results are shown for an inverter and a N and. The work in [5] can be considered as an alternative to the proposed approach, though it has not been tested on other cells and the extension to multicell circuits is not accounted for. Finally, the BSIM-CMG model is a mathematical compact model of FinFET behavior for SPICE simulation engines, and it represents the industry’s golden reference for circuit simulation [13], [26], [27]. The proposed work is presently built upon BSIM-CMG characterization of FinFETs.

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Fig. 1. Abstract voltage-controlled non-linear bipole model of FET in static conditions, used in the proposed approach. TABLE I I NTERNAL N ODE V OLTAGE I NDEPENDENCE F ROM C ELL R ESIZING [V]

To the best of our knowledge, no similar logic-level leakage models applied to FINFET standard cells have been published yet.

Fig. 2.

Example cell NAO12.

the Kirchhoff current law (KCL) characterization of a cell (see Section III-B). In the present implementation of the method, we omitted the current flowing directly from gate to body, as in the target technologies, we found it to be always negligible with respect to other currents; however, the approach is not restricted to this hypothesis. The assumption results from BSIM4 simulations extracting the i gb current, by biasing an n-type device at VG = V D = VS = 1 V and V B = 0 V. In addition, previous works (see [25, Table I]) similarly showed that i gb is about seven orders of magnitude smaller than the other leakage currents. Having assumed the abstract model of the (n- and p-type) device, it is possible to accurately characterize the current of each nonlinear bipole in the model as a function of the voltage difference at its terminals, by means of a proper characterization procedure based on SPICE simulation (see Section IV); therefore, we assume to know the value of all the currents in Fig. 1 given the static voltage values at the terminals of the device, in the full range from zero to VDD . B. KCL Static Characterization of a Single-Stage Logic Cell

III. L EAKAGE C ALCULATION PARADIGM A. Abstract Device Model All the physical leakage phenomena in a FET device result in currents flowing from a terminal at higher voltage to another terminal at lower voltage. Hence, we base the analysis on an abstract model of the basic device in the target technology, composed of ideal voltage-controlled current generators, as shown in Fig. 1. Similar abstract models have been proposed in the previous works [24], but with different use. In the proposed abstract model, the (nonlinear) current generators are solely controlled by the voltages at their terminals, so that each generator acts as a voltage controlled nonlinear bipole, also known as nonlinear resistor [7]. In principle, such modeling assumption is in contrast with the fact that the subthreshold current i ds also depends on vSB and vGS [24]. Thus, in any cell circuit, the model in Fig. 1 will be only applicable to those transistors having vSB = 0 and vGS = 0, which must be kept in mind when performing

Given a logic circuit in static conditions, the total leakage current is identified by the current flowing through the external (constant) voltage generators, i.e., the power supply and the generators driving the inputs (the latter generators representing static outputs of other logic cells in the design). As the external generators are connected to the ground node, the total current is often calculated as the sum of the currents in the circuit branches connected to ground, i.e., body currents of n-type devices, source currents of n-type devices directly connected to ground, and gate currents of devices with gate terminal ground voltage [1]. However, for a general and accurate application to any cell topology, this is not a practical option, usually for the presence of transistors in the on-state, as shown by the example cell NAO12 in Fig. 2: assuming A = 1, B = 0, and C = 1, we can compute the total leakage as the sum i b Q1 + i b Q2 + i b Q3 + i s Q1 + i s Q3 + i g Q3 , where the exact current values depend on the actual voltage values at the circuit nodes. Such expression is formally correct but demands the calculation of i s Q3 flowing through device Q3 as the sum



Fig. 3. Equivalent circuit of cell NAO12 and KCL Gaussian surface, for ABC = 101. Black arrows identify transistors in the on-state.

of other currents flowing in Q4 and Q5, because Q3 is on and its drain–source current is determined by the leakage currents of the other devices. While a solution to this case can be found at the first sight, the ultimate general rule that guarantees a correct result is to apply the KCL, by drawing a Gaussian surface and deriving an algebraic sum expression of the leakage current flowing to ground: Fig. 3 shows a possible KCL solution for the given case, leading to Ileak = i gs Q2(vG S Q2) + i gd Q2(vG D Q2) + i gd Q4(vG D Q4) +i ds Q4(v D S Q4) − i dbQ4(v D B Q4) − i gs Q6(vG S Q6) −i gd Q6(vG D Q6) + i gs Q3(vG S Q3) + i gd Q3(vG D Q3) (1) where each current term emphasizes its dependency from the node voltages. The key point of the above solution is that all the terms refer to static leakage currents directly available from the characterization of the single FET as the abstract model in Fig. 1, provided that we know the circuit node voltages. None of the voltages in the KCL expression above are to be considered exact digital voltage levels: this is evident for the internal nodes, which depart significantly from 0 V and VDD , but it is also true for input and output nodes as in a complete circuit they are affected by loading effect. As a general rule, for each input combination, we write a KCL expression of the total leakage current flowing through the external generator, by means of a Gaussian surface, which traverses i gs , i gd,i bd , i sb branches, and i ds branches only in devices in the OFF-state and with vSB = 0 and vGS = 0 The latter constraint is necessary because the abstract device model used for current characterization is only valid under such assumption (Section III-A). We call this operation as KCL static characterization of the logic cell. C. Internal Node Voltage Calculation in Ideal Conditions When two or more transistors in the pull-down (pull-up) network of a logic cell are OFF, the voltages at the nodes connecting the transistors are not easily predictable on the basis of simple models of transistor behavior. As an example, for input ABC = 000, node n. 1 in Fig. 2 is not actively driven

Fig. 4. In NAO12 and in NAND 2, for the same input and output values, the internal node voltage is the same.

by any device (we may say it is in high-impedance state) and its voltage is only determined by nonlinear voltage–current characteristic of the connected devices in OFF state. Yet, the accurate evaluation of internal node voltages allows assessing the values of the leakage currents in the KCL expression of the cell under analysis, when we model it as the example in Fig. 3: the substitution theorem [7] ensures that the currents in a subcircuit composed of generators and voltage-controlled nonlinear resistors are fully determined by the voltages at the terminals of the subcircuit, as if the subcircuit terminals were driven by ideal voltage generators. Thus, knowing the voltage-dependent characterization of currents in a single device and the voltages at the terminals of the devices allows us to evaluate all the currents occurring in an expression like (1). The same pull-down (pull-up) structures often occurs in different cells, leading to the same internal voltage values: as an example, the two-transistor stack in the pull-down network of the cell in Fig. 2 also occurs in a NAND cell, so that for the same input values on the transistor gates and the output node, the voltage on node n. 2 is the same in both cells, as shown in Fig. 4. This again is a general result derived from the substitution theorem, as the internal node voltages in a subcircuit are fully determined by the voltages imposed at the external terminals of the subcircuit. By SPICE simulation of the cells for all input patterns, we therefore characterized the internal node voltages of all the circuit structures that occur in the pull-down and pull-up networks of the cells in the library. Importantly, we found out that at fixed supply and no output load, the voltages at the internal nodes of the OFF pull-down (pull-up) network of a digital cell do not depend from the resize factor of the cell: the internal node voltages do not substantially change if the widths or the number of fins of all the devices in the cell are multiplied by a factor X. Table I reports the evidence of such result referring to the NAO12 cell in Fig. 2. All the cells gave analogous results. In general, given the input pattern of a cell, we can assume to know the voltages at the internal nodes, assuming a fixed supply voltage and no output load.


Fig. 5.

Voltage swing for different output states in a generic cell.

D. Internal Node Voltage Dependence on Voltage Swing Scaling Adaptive supply voltage is one of the most widely adopted and effective techniques for leakage reduction [14]. The proposed estimation approach allows us to directly implement supply voltage scaling effect calculation, as we refer all the calculated currents to the voltage values at the circuit nodes. In this context, we refer as voltage swing to either the voltage difference between output and ground in a pull-down network, or the voltage difference between supply and output for a pull-up network. In ideal conditions, the voltage swing is equal to the actual VDD value in OFF pull-down/pull-up networks, and it is zero in on pull-down/pull-up networks. In a real circuit, the actual voltage swing is affected by a voltage drop δV due to loading effect (Fig. 5) that is quantified in the following section. The characterization of internal node voltages in all the pullup/pull-down circuit structures that compose a cell library can be easily done as a function of the actual voltage swing. A very important outcome of our analysis is that for any pull-down or pull-up circuit structure, the internal node voltages always scale linearly with the voltage swing for the voltage ranges of practical interest. An evidence of this behavior is shown in Fig. 6 for stacks of three n-type transistors and three p-type transistors. The first two charts from the left show the internal voltages V1 and V2 for all the input patterns that set the pull-up/pulldown circuit OFF. The behavior is (perfectly) linear for all the input patterns except for one, for which anyway the behavior is linear down to voltage swing values approaching 0.4 V. The latter case occurs because the three transistors are OFF–ON–OFF, respectively, until the voltage swing gets small enough to set the central transistor gate-source voltage below threshold voltage v t , and the behavior aligns with the OFF – OFF – OFF configuration. The rightmost chart shows the special case of input pattern that sets the pull-down/pull-up circuit on: if we force a small voltage swing δV different from zero (which occurs in case of nonnegligible loading effect, as shown in the following section), the internal nodes of the stack still behave linearly with the forced voltage gap. In addition to the two subcircuits shown in Fig. 6, we found that any pull-down or pull-up circuit structure occurring in our 102 standard cells shows the same linear behavior of internal node voltages with respect to the applied voltage swing.

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Importantly, we found a substantial technology independence of the behavior, as the linearity was evident for both CMOS and FinFET implementation of the same cell. A full characterization of the linear behavior of the internal node voltages in pull-down/pull-up circuit structures has been accomplished (see Section V). As a result of such characterization, for each internal node of a cell, we can associate a voltage line to each input pattern. Referring to the NAO12 cell in Fig. 2, the voltage lines extracted for internal node 1 with respect to input pattern ABC are as in Fig. 7. The right part shows the voltage lines occurring when the pull-down network in the cell is OFF (with a voltage swing VDD − δV ), whereas the left part shows the voltage lines occurring when the pull-down network is on (with a small voltage swing δV ). In general, we can apply the characterized voltage lines to calculate the internal node voltages, using VDD − δV voltage swing in OFF pull-down/pull-up networks and +δV voltage swing in on pull-down/pull-up networks. E. Calculation of Output Voltage Drop Due to Loading Effect Without loss of generality, here we refer to the loading effect on a digital cell driving a high logic value on its output node OUT, connected to the input nodes of other digital cells. Fig. 8 shows the corresponding equivalent circuit. Q P models the pull-up network in the driving cell, while Q 1 …Q N are the transistors in the driven cells directly connected to node OUT. Given a cell with resize factor X, it is easy to determine the approximately equivalent width W D of the pull-up network in the given technology. For simplicity, we also assume Q 1 …Q N being all n-type devices; the same analysis can be carried on distinguishing a set of n-type and a set of p-type driven devices and leading to the same conclusion. The total equivalent N Wk , where W K is the width of the load is WLOAD = k=1 width of transistor Q K . In FinFET technology, the equivalent parameter of gate width is the number of fins NFIN, so we can similarly define NFIN D in the driver and NFINLOAD as the total equivalent number of fins in the load. Due to the presence of nonnegligible static gate currents on Q 1 …, Q N , there is a voltage drop δV on node OUT. In addition, due to the presence of static currents in the pull-down network, there is a (very small) intrinsic voltage drop even in case of no load, i.e., for WLOAD = 0. The value of δV for typical cells and loads in nanoscale CMOS technologies has been studied in several previous works [16], and it is always in the range of a few millivolts for 1 V supply, so that the pull-up transistor Q1 is in its linear operating region with its drain current I D proportional to the pull-up transistor width W D . The sum of the currents flowing through the gates of the load is I L = i G (VOUT ) · WLOAD , where i G (VOUT ) is the gate current per unit width in a FET having VOUT as gate-source voltage in the given technology. As from the previous works [17], i G (VOUT ) is exponential in VOUT , so that the resulting situation is shown in Fig. 8, where the intersection of I L and I D identifies the solution of the circuit. As the vertical amplification of I D and I L depends on W D and WLOAD , respectively, it is possible to characterize the value of δV for the set of practically interesting values of



Fig. 6. Internal node voltage as a function of voltage swing (SPICE results, 22 nm CMOS). Each line refers to one ABC input pattern. The case of switched-on stacks is shown separately in the rightmost charts.

Fig. 7.

Internal node voltage lines for cell NAO12, node 1. The input pattern associated to each line is shown.

cells, it is possible to estimate the voltage drop δV caused by the loading effect, for both high and low logic output voltage. F. Overall Procedure for Leakage Calculation

Fig. 8. Equivalent circuit of a CMOS cell driving a high logic value, with N driven transistors as its load.

the pair W D , WLOAD . The voltage drop δV generally behaves nonlinearly with VDD . To accurately calculating the voltage drop, we chose to characterize it at different supply voltages (see Section IV). In general, given a cell driving a set of other

Assuming to have done the single device static current characterization, the KCL static characterization of the cells, the node voltage lines characterization of the circuit structures composing the cells, and the voltage drop loading effect characterization, the procedure to obtain the leakage current drawn by any cell in a design is as follows. 1) From the input pattern, in the characterization database of the cell, we recover the voltage lines associated the internal nodes of the pull-up and pull-down circuit structures. 2) From the input pattern, the resize factor of the cell, the total equivalent width of the load, and the VDD value, we find the output voltage drop δV due to loading effect. 3) We apply the actual voltage value VDD − δV to the voltage lines of the internal nodes of the OFF pullup/pull-down network, and find the actual internal node voltages.


Fig. 9.

Graphical solution of the loading effect determining δV .

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Fig. 11. Internal node voltage circuits for N-type and P-type stacked devices (only one internal node).

Fig. 10. Simulation setup for the single device static current characterization (N-type devices. P-types are considered by complementary configuration).

4) We apply the actual voltage value +δV to the voltage lines of the internal nodes of the on pull-down/pull-up network, and find the actual internal node voltages. 5) We evaluate the algebraic sum of functions in the KCL expression of the total static current absorbed by the cell for the given input pattern, applying the actual internal node voltages to find the values of the functions. IV. C HARACTERIZATION S TEPS FOR M ODEL C ALIBRATION The approach relies on two technology characterization steps: 1) voltage-dependent characterization of static currents in single FET device; 2) internal node voltage characterization in stacked n- and p-type transistor structures. The characterization relies on SPICE simulation and can be accomplished with any compact device model operating in a SPICE simulation engine, and for any FET device technology. The present implementation of the project addresses MOSFET and FinFET devices, making reference to NGSPICE simulator [12] with BSIM4 device model [10]–[22] and HSPICE simulator with BSIM-CMG device model [13]–[27], respectively.

Fig. 12. Internal node voltage circuits for P-type stacked devices (two internal nodes). N-type stacks are considered accordingly.

terminals, rather looking at it as a black box to be characterized by the abstract model in Fig. 1. Considering the digital switch operation of the device and assuming full symmetry between drain and source terminals, the rules adopted to characterize the voltage-controlled nonlinear resistors of the single device abstract model can be easily derived by the inspection of Figs. 1 and 9 as follows (n-type device): i gs (VGS = v) = i G (Vgs = v, VDS = v, VBS = 0), v > 0 i gd (VGD = v) = i gs (VGS = v), v > 0 i gs (VGS = v) = i gd (VGD = v), v < 0 i gd (VGD = v) = i G (VGS = 0, VDS = −v, VBS = 0), v < 0 i db (VDB = v) = −i B (VGS = 0, VDS = v, VBS = 0), v > 0 i sb (VSB = v) = i db (VDB = v), v > 0 i ds (VDS = v) = −i S (VDS = v, VGS = 0, VBS = 0), v > 0

A. Characterization of Currents in Single FET Device The single FET device current characterization is realized by the basic simulation setup shown in Fig. 10 (for n-type devices). It is worth noting that we are not interested in the physical meaning of the measured currents at the device

where v is a voltage value varying from 0 to 1.2 V, or from 0 to −1.2 V, with 0.05 V steps. The case of i sb , i db , and i ds is only considered for v > 0 as from standard operating mode of digital circuits. The set of characterization rules for p-type devices are derived accordingly.



TABLE II S AMPLE OF C HARACTERIZED I NTERNAL N ODE V OLTAGE L INES IN 22 nm CMOS AND 20 nm F IN FET (C ELL NAO12). VALUES IN V OLTS . D O N OT C ARES R EFER TO U NUSED VALUES

B. Characterization of Internal Node Voltage Lines and of Output Voltage Drop Due to Loading Effect The internal node voltage characterization is needed for circuit structures including stacked transistors, which occur in generic cells. The characterization covered all the basic structures shown in Figs. 11 and 12. Note that the characterization can be easily extending to series-connected transmission-gate structures. In the specific case of our target library, this was not necessary as the chosen multiplexer and latch cells contain no series of transmission gates. Each circuit structure was simulated using a dc sweep, at 30 °C and 100 °C, for VDD = 0.1–1.0 V with 0.1 V step, for all input patterns. The resulting data confirmed the linear behavior for all the circuit structures and the substantial independence on the resize factor of the circuit. The internal node voltages for voltage swing = 0.08, 0.6, and 1.0 V were saved in a database, which is sufficient for the linear interpolation of all other intermediate cases, for on and OFF pull-down/pull-up network. Table II shows a sample of the characterization result, referring to cell NAO12. The characterization data were further processed by software routines to automatically create data tables, which are used in the logic-level HDL-coded estimation. As for the output voltage drop due to loading effect, referring to the model in Fig. 7, we characterized the behavior of δV for each pair of values W D , WTOT and for a set of VDD values. Table III shows the resulting δV values in the given CMOS technology for a representative subset of driver and loads, and for the upper and lower limits of VDD , referring to pull-up drivers. In the given FinFET technology at 0.9 V supply, for the extremely unbalanced case of NFIN D = 1 in the driver and NFINLOAD = 400 in the load, we measured a voltage drop δV = 0.048 mV and δV = 0.021 mV for pullup and pull-down drivers, respectively. As a result, we can

TABLE III S AMPLE OF C HARACTERIZED V OLTAGE D ROP VALUES D UE TO L OADING E FFECT IN 22 nm CMOS [mV]

conclude that the loading effect in the FinFET standard cells is absolutely negligible. For each cell in the CMOS library, we identified the equivalent W D as a characteristic number of each cell for a given input pattern, as the width of a single pull-up transistor giving the same drive strength as the cell. For WTOT computation, we found that nonstacked transistors in the driven cells were significantly dominant in affecting the leakage through loading effect in real-circuits, because, on average, stacked transistor has a lower gate current. Therefore, our approach relies on computing the equivalent WTOT considering only nonstacked transistors in the driven cells. C. Model Implementation In this paper, we implemented the logic-level leakage estimation procedure by means of a HDL (VHDL) description of the standard cells. The model can be equivalently implemented in an offline tool.


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TABLE IV PATTERN D EPENDENT BASIC C ELLS L EAKAGE R ESULTS IN nA (L ATCH C ELL I NCLUDES O UTPUT VALUE IN R EFERENCE PATTERN )

The implementation is based on two packages single− dev− leakage.vhd and single− cell− voltage.vhd, the former defining arrays containing the single device current characterization data, and the latter defining arrays containing the internal node voltage characterization data. Each cell description includes a technology-independent section with the KCL-based leakage expression, invoking the functions defined in the packages according to the logic values on the input signals. For loading effect, in the present VHDL implementation, each cell sends back to its driver the actual value of its Wk to the driven cell. A resolution function computes the total WTOT as a sum of the Wk values in the fanout of the driver cell, and the latter computes the value of δV before evaluating the leakage expression based on node voltages. We developed a library model of 17 basic cells, each with six different drive strength factors X1, X2, X3, X4, X6, and X8, for a total of 102 standard cells. V. L EAKAGE E STIMATION ACCURACY R ESULTS We verified the proposed estimation procedure on three different technologies: 1) 22-nm bulk CMOS at 1 V supply and 2) 22-nm bulk CMOS at 0.5 V; and 3) 20-nm FinFET at 0.9 V supply. The reference circuit-level simulators for comparison were NGSPICE BSIM4 for the CMOS technology and HSPICE BSIM-CMG for the FinFET technology, as predictive models for FinFETs are not presently supported by NGSPICE. A. Single Cell Leakage Estimation We tested the accuracy of the method against SPICE simulations of single cells, for each basic cell type and resize factor, and for each possible input pattern. Table IV reports our results for a subset of cells, detailing pattern-dependent leakage values. The different accuracy among input patterns can be ascribed to quantization errors in internal voltage values. Table V reports the average leakage current estimated

with respect to all input patterns, for the 17 basic cells, with a relative error with respect to SPICE always below 1%. Supplementary results on single cells in scaled CMOS technologies are reported in [31]. B. Specific Loading Effect Estimation for Critical Circuits It has been shown that, in complex circuits, the loading effect often exhibits compensation between positive and negative leakage modification in different cells [4]–[6]. However, it is essential that an estimation technique be capable of accurately capturing those design cases where such compensation does not occur. Thus, to demonstrate the effectiveness of the approach in modeling the loading effect, we focused on a set of critical netlists, specifically designed to show a considerable loading effect due to the disproportion of the fanout with respect to the driver size. The underlying technology in this analysis is 22-nm CMOS at 1 V. Table VI shows the comparison of the calculated results with SPICE results. C. Multicell Multistage Circuit Leakage Estimation In a circuit composed of multiple cells, the estimation algorithm sums up the leakage contributions of all cells considering the loading effects, whereas in SPICE simulations, we measure the total static current flowing through the supply voltage generator connected to the circuit under test. Table VII shows a set of results on digital blocks composed of multiple cells and multiple logic levels, thus subjected to loading effect; all the cases show error percentage below 1%. Table VIII shows the comparison of the average performance of the proposed method with reported previous research works, referring to multicell circuits. In [16], Mukhopadhyay et al. do not report precise error percentages; however, the bar diagram in [16] suggests circa 1% error. In [5], Chaudhuri et al. report the error with respect to their reference TCAD simulation for a NOT and a NAND cell.



TABLE V C ELL L IBRARY L EAKAGE E STIMATION . R EPORTED VALUE IN nA I S THE AVERAGE A MONG ALL

S IGNAL PATTERNS . A LL C ELLS A RE AT M INIMUM S IZE FACTOR

TABLE VI L OADING E FFECT E STIMATION IN C RITICAL N ET-L ISTS (X1 = M INIMUM S IZE ; X8 = 8 T IMES M INIMUM S IZE ). VALUES IN nA

TABLE VII M ULTICELL M ULTILEVEL L OGIC L EAKAGE E STIMATION . R EPORTED L EAKAGE VALUE IN nA IS THE AVERAGE A MONG ALL I NPUT PATTERNS

Table IX shows the accuracy and CPU time comparison with commercial PrimeTime PX based on current lookup tables. While the improvement in accuracy is significant, the comparison for speedup is partly unfair for the present HDL implementation absolutely lacks any speed optimization. D. Extension to Statistical Leakage Estimation Though statistical variation analysis was not the target of this paper, it is important to explore the feasibility of statistical leakage estimation under process variations. We manually implemented a procedure to support logiclevel Monte Carlo (MC) analysis for global die-to-die and local cell-to-cell mismatch variations. First, we generated a vector

of pseudorandom values of the technology parameters affected by variations. In our experiment, we assumed variations of L, Tox, and Nbody as 15% variation at 3σ in the 20-nm FinFET library, and generated a variation vector of 103 values. Each element of the variation vector is labeled by an integer index α = 1…103 . Second, we extended the SPICE-level characterization of currents in single device as follows: i gs (Vgs ) = i gs0 (Vgs ) + i gs (Vgs )(α) i gd (Vgd ) = i gd0 (Vgd ) + i gd (Vgd )(α) i db (Vdb ) = i db0 (Vdb ) + i db (Vdb )(α) i sb (Vsb ) = i sb0 (Vsb ) + i sb (Vsb )(α) i ds (Vds ) = i ds0 (Vds ) + i ds (Vds )(α)


TABLE VIII AVERAGE E RROR W ITH R ESPECT TO SPICE

TABLE IX C OMPARISON W ITH P RIME T IME FOR A CCURACY (E RR %)

11

VI. C ONCLUSION The proposed novel logic-level model allows the accurate estimation of leakage currents in nanoscale digital standard cell circuits. The analysis of voltages at the internal nodes of standard cells shows a practically linear dependence on the output voltage swing, which allowed a direct implementation of supply voltage variation impact on leakage currents, as well as of the voltage drop effect (loading effect). In this paper, the method has been implemented in HDL cell models supporting leakage estimation at simulation time; it can also be implemented in offline estimators. Exhaustive tests have been carried out on a full cell library, on dedicated circuit cases for loading effect analysis and on multicell circuit cases, at different supply voltages. Accuracy results in 22-nm CMOS and 20-nm FinFET technology show a better agreement with SPICE estimations than the existing approaches, with average percentage error below 1%. R EFERENCES

TABLE X S TATISTICAL L EAKAGE E STIMATION IN M ULTICELL M ULTILEVEL L OGIC S UBJECT TO P ROCESS PARAMETER VARIATIONS

where the subscript designates nominal value and the prefix designates the variations, which are associated to the variation α. With similar notation, the characterization of the voltages at the internal node n of each cell is extended as V (n) = V (n) + V (n)(α). Note that such scheme preserves the correlation between current variations and node voltage variations associated to the same process parameter variation. Therefore, for each cell, we collected 103 randomly distributed characterization instances, each identified by an index α, which can be used in a logic-level MC iterative leakage calculation. At each iteration, for each cell in the design, a random α is chosen and the corresponding characterization instance is used for leakage calculation. We repeated the estimation for a sufficient number of iterations to obtain a stable value of the average total leakage and standard deviation. Table X shows the results compared with SPICE MC, referring to the standard deviation of the total leakage current. For intracell transistor mismatch analysis, variations at node voltages should be characterized with respect to the joint pseudorandom variations of single transistors, which results in a more complex implementation of the procedure but it does not imply any modification to the leakage calculation scheme (it only affects the selection of current and voltage values passed to the KCL expressions at each MC iteration). In this paper, such analysis has not been explored

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Zia Abbas received the M.Sc. degree in electronics and the M.Tech. degree in electronics circuits and systems in 2001 and 2009, respectively, and the Ph.D. degree from the Sapienza University of Rome, Rome, Italy. He was a Senior Lecturer with Amity University, Lucknow, India. He is currently a Research Assistant with the Department of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome. His current research interests include low-power, variation-aware nano-CMOS and FinFET circuits, and current mode devices.

Mauro Olivieri (M’98) received the master’s (Laurea) degree (cum laude) in electronic engineering and the Doctorate degree in electronic and computer engineering from the University of Genoa, Genoa, Italy, in 1991 and 1994, respectively. He was an Assistant Professor from 1995 to 1998. In 1998, he joined the Sapienza University of Rome, Rome, Italy, where he is currently an Associate Professor, teaching digital electronics and VLSI system architectures. His current research interests include digital system-on-chip design, microprocessor core design, and digital nano-CMOS circuits. He has authored more than 100 research papers and a textbook in three volumes. Prof. Olivieri is a reviewer for several IEEE T RANSACTIONS and is in the Technical Program Committee of the IEEE DATE Conference. He is an evaluator for the Joint Technology Initiative of the European Commission on Nano-Electronics (ENIAC Joint Undertaking).

Antonio Mastrandrea received the master’s (Laurea) degree (cum laude) in electronics engineering and the Ph.D. degree, from the Sapienza University of Rome, Rome, Italy, in 2010 and 2014, respectively. He is a Research Assistant with the Department of Information Engineering, Electronics and Telecommunications, Sapienza University of Rome. His current research interests include digital system-on-chip architectures and nano-CMOS circuits oriented to high-speed computation.