IEEE PEDS 2011, Singapore, 5 - 8 December 2011
Voltage Vector Approximation Control of Multistage Multilevel Inverter Using Simplified Logic Implementation Menshawi K.M., M.N. Abdulkader , and Saad Mekhilef Department of Electrical Engineering,University of Malaya,Kuala Lumpur,Malaysia Email:
[email protected].
[email protected] [email protected]
Abstract- Three-stage redundancy-free multilevel inverter and its innovative control method have been presented. Logic comparators
have
been
implemented
in
order
to
ease
calculations and to ensure simplicity as well as to improve resultant
voltage
waveforms.
The
multistage
inverter
is
formed by high, medium and low voltage stages, connected in series. Six-switch conventional inverter represents the main high- voltage stage. Cascaded H- bridge units are used to build the medium and low voltage stages of the inverter. The proposed control strategy is to keep the state of the high voltage stage if it can lead to the target voltage vector or medium and low approximations otherwise, are triggered. Hysteresis Comparators are used in high and medium voltage stages to hold switching states or to decide the next change. The low voltage stage works to reach the reference voltage vector by using integer rounding and comparators to achieve the best approximations. The designed control technique is verified
by simulations as
well as testing to prove its
advantages over previous control methods.
INTRODUCTION
Multilevel inverters (MU) were first introduced back in 1975 [1] and have lately received considerable attention in the development of high and medium power applications [2]. The main strength of MUs over the conventional inverters,is the capacity to have output voltage and current levels higher than those of the device ratings; hence, MUs have been classified as high - power inverters [2] . The cascaded R-bridge (CRB) topology,as a basic form of the multistage inverter, is composed of a number of full bridge units supplied with equivalent and isolated DC sources (Vs). For each inverter branch, the outputs of the full bridge cells are connected in series to accumulate the branch voltage [3]. The k-cell inverter branch has a maximum, minimum and steps voltages of kVs, -kVs and Vs respectively,and therefore (2k+1) voltage levels. As all cells have the same voltage steps, it is expected that the branch voltages, except for the extreme levels, can be achieved with multiple combinations of the individual cells switching states. The asymmetrical CRB inverter has been introduced to increase the number of voltage levels for the same number of full bridge cells by supplying the cascaded cells with different DC voltages [4]. It has also been shown that with the cascaded cells voltages related by ratio 3 (i.e. Vs, 3Vs. 9Vs...), the number of the uniformly spanned
voltage levels is maximized as each voltage level has unique switching state for the individual cells which implies the elimination of redundant states [5]. Cascaded H-bridge (CHB) topology is designed with large number of isolated DC sources and therefore,increases the overall cost of MLI. In order to reduce the DC supply cost, the highest voltage stage (referred to as the main inverter stage) must be designed with a special topology that uses one DC supply for the three phase branches instead of the three full bridge cells. Constructing multistage inverters with a conventional 6-switch and a 3-level neutral point diode clamped (NPC) main stages have been reported in [6] and [7] respectively. In hybrid multistage inverters,the main stage withstands the largest portion of the total DC voltage rather than dividing the voltage equally between the switching devices as in the basic multilevel inverters. This might be understood as a giving up of one of the main features of multilevel inverters which is the ability to construct an inverter with voltage rating that is multiple of the switching devices ratings. The design of hybrid inverters, however, relies on the fundamental feature of semiconductor switching devices which is a tradeoff in device switching frequency and voltage ratings [8, 9]. Therefore the main stage should be restricted to low switching frequency, preferably the fundamental frequency,while the low voltage stage could be operated at the desired carrier frequency. To maintain the low frequency operation of the high voltage stage, it must be confirmed that the PWM carrier frequency switching between the adjacent voltage levels, can be carried out without involving the high voltage stage. The capacity of changing the voltage between adjacent levels by controlling the low voltage stage only has been addressed and referred to in the literature by the modulation condition [11]. The modulation condition imposes a restriction on the DC voltage ratio of the cascaded stages. Maximizing the number of levels by eliminating state redundancy leads to the failure of the modulation condition,i.e. some redundancy is necessary to satisfy the modulation condition.
978-1-4577-0001-9/11/$26.00 ©2011 IEEE
57
Most of the research presented in the literature with ratio-3 based multistage inverter sourcing used a low frequency control methods to avoid the undesirable high frequency switching of the high voltage stage. Rather than attempting to produces the local time average of the reference voltage by PWM switching between the nearest higher and lower inverter voltage levels, the reference voltage approximated to the nearest inverter voltage level [12]. With the presence of large number of voltage levels, this approximation is justified. The voltage vector approximation has been also
and elimination of look-up tables, which in return saves memory space and the execution time. In this paper the staged controller structure, as in [17, 18] has been adopted; but the control algorithm has been implemented using especially designed 2-D hysteresis comparators rather than algebraic-based equations. This approach aims to simplify the implementation and to overcome some of the bugs associated with the previous implementations. In the following section, the control concept is introduced followed by a brief description of the previous implementations and the associated problems.
presented [13]. The approximation control algorithms follow either one of two possible approaches. The first approach has two stages. The first stage is to calculate the nearest inverter vector and the second is to determine the corresponding switching signals for the individual cascaded stages [13], [14]. As the number of levels is usually large, there will be a large number of equivalent switching states sharing the same voltage vector. This makes the second stage rather complicated particularly if the designer aims to optimize the utilization of the equivalent states. The second approach is based on individual inverter cascaded stage calculations; this approach has been introduced for phase voltage level approximation [15] and extended recently for vector approximation of multistage inverters designed with maximum number of levels [16-18]. The staged vector approximation has been found to be useful as a basis for PWM control of inverters with state redundancy elimination without subjecting the high voltage stage to high switching frequency [19], [20]. In this paper the voltage vector approximation algorithm is designed according to the second approach. To mInImIze the switching losses and ensure fundamental switching frequency for the high voltage stage, the algorithm has been designed to hold the higher voltage stage switching state as long as this state can lead to the target vector. If the present switching state cannot lead to the target vector then the inverter changes it. The new switching state can lead to the target vector and should maintain minimum switching losses. In the work presented in [17], the determination of whether the present state should be maintained or changed and the determination of the next state are all carried out by calculations depend on the geometric description of vanous locations within the vector space. These calculations involve a lot of algebraic expressions, many trigonometric functions and some lookup tables which have resulted in complicated calculations. To simplify the calculations, a 60°- displaced coordinate system is used to represent the inverter and the reference voltage vectors in [18]. In this representation it has been shown that the comparison needed to determine if a given reference can be realized using certain state is a very simple integer expression. This has led to a considerable simplification
Next, the three inverter stages controllers are discussed in details, as well as the simulations & experimental verifications and finally the conclusions of the paper. VOLTAGE VECTOR ApPROXIMATION
The control concept presented in this section is suitable for any multistage inverter designed with ratio-3 related voltage steps of the cascaded stages. However, the 3-stage inverter shown in Fig. 1 has been considered to describe and implement the designed control algorithm. c
B
A
Vs
F. Bridge
F. Bridge
3Vs
F. Bridge
F. Bridge
Low.voltage smgc
Medium-voltage stage
High-voltage stage
Fig.I.
The three-stage inverter with singly-fed main stage.
A. The control strategy Consider the multistage inverter shown in Fig. 1. this inverter has I8-levels as shown in Fig. 3. in which x, y and z denote the switching state of the high, medium and low voltage stages respectively. Fig. 3. describes the voltage levels of one inverter branch output (A, B or C) with respect to the arbitrary reference point (Ret). x is a binary number with x=o and 1 representing the ON state of the lower and the upper switching devices in the main stage sub-inverter. With y (z) = 0,1 and 2,the medium (low) full bridge cell is producing the negative, 0 and positive of its DC side voltage respectively. The voltage vector corresponding to a given switching state is obtained by applying Park's transformation equation in the following form:
58
-0.5
J3
( 1)
2 where Vd and Vq are the d- and g- components of the voltage vector and the subscripts CA, Band C) denote the phase. For all possible combinations of the switching variables, the resultant voltage vectors compose the inverter voltage vector diagram as given in Fig. 2. In this figure the voltage vector diagram has been drawn with three line thicknesses and colors to show that any inverter voltage vector can be represented as a sum of three vectors: due to the high,medium and low voltage stages.
The aim of the controller is to approximate a reference vector within the inverter vector space to the nearest inverter vector with minimum switching losses. To minimize the switching losses, the controller should approximate target vector with minimum switching giving priority in switching reduction to the higher voltage stage. The inverter voltage vectors have been obtained by adding all possible combinations of high, medium and low stages voltage vectors as shown in Fig. 2. In this figure,the three stages vector diagrams is used to construct the 18-level MLI vector diagram by the superposition of the lower stage vector on the higher stage vector diagram. Despite the absence of the state redundancy as indicated in Fig. 3, the inverter voltage vectors, except for the outmost layer can be obtained by multiple switching combinations of the three stages. More flexibility is added by the fact that: zero vectors for all the stages and the non zero vectors of norm Vs and 3Vs for the low and medium voltage stages are realized by multiple switching states. In Fig. 4, the detailed hexagonal area around the high voltage stage vector corresponding to state x= I 00 is denoted by "Domain of state xARc=lOO". This area is formed by all the medium and low voltage stages vectors superimposed on the high stage vector corresponding to state xARc=lOO. If and only if a reference vector is located within the domain of a high voltage state, this vector can be approximated by adding the appropriate medium and low voltage vectors to that high voltage vector. The voltage vector
Fig. 2.
of the medium state YABc=220
The inverter vector diagram.
The domain of the medium state YABC=220, high domain
(within the XABc=100)
I
The voltage vector
of the
high state
XABC=100
Fig. 4.
Fig. 3.
The 18 voltage levels of the inverter.
High and medium states domains definitions
The cascaded controller determines the next switching state of the three stages consecutively as shown in Fig. 5. The high voltage stage controller compares the reference vector to the present high voltage stage domain. If the reference vector is located in the present high state domain, then the high voltage stage preserves it switching state over the next sampling interval. Otherwise,it should be changed to a one that has the reference voltage in its domain. The high voltage states domains overlap in some regions of the vector space as indicated in Fig. 6. If the reference voltage is located in domains overlap, there will be more than one
59
option m the next state selection. To mmlmlze the switching losses the state reachable with minimum switching actions is selected. Reference voftag" veder
High Vollage Slage . 1---....XA8C
Low Voltage Stage Calculations Referenco\-__---J Low
Fig. 5.
The controller structure
Once the next high voltage state is determined, as the present or a new state, the corresponding voltage vector is then subtracted from the reference voltage vector. The resultant vector is denoted in Fig. 5. by the medium reference and represents the balance of the reference vector that is required to be realized by the medium and low voltage stages. To control the medium voltage stage, the state domain has been defined similarly to the high voltage stage domain as indicated in Fig. 4. The medium voltage stage control concept is like the high voltage stage's, i.e. the switching state is maintained if the reference vector is located in its domain, else the nearest state that has the reference voltage in its domain is selected. The vector corresponding to the next medium state is subtracted from the medium reference and the result, denoted in Fig. 5. by the low reference vector that is required to be approximated,by the low voltage stage.
High 'Yoltag(l :s.la5J9 �€II;;tof tOO
\
he �r :sub:s;paoo that is reachable throug.h state 100
•
Fig. 6.
.
.
, , •
The inverter vector space and the comparison lines to control the high voltage stage
B. implementation by geometric-based calculations In the study presented in [14], the described voltage vector approximation has been implemented by representing the voltage vectors by its orthogonal (d-q) components. The geometry of the voltage vector space has been represented by linear equations that must use floating-point coefficients. The vanous domains overlapped regions have been examined by a series of comparisons to determine the reference vector location in terms of various domains after specifying the reference sector. For low voltage stage control an interpolating polynomial has been composed to approximate the points around each low stage voltage vector to the nearest vector. This implementation, despite achieving the design goals in terms of the controller function suffers from some drawbacks,mainly: \- The need for large memory space; due to the long routines and the use of lookup tables. 2- The need for costly floating point controller or the slow processing with the fixed point controller; due to the floating point coefficients and the frequent use of trigonometric functions. 3- The difficulty in extending the design for over modulation region. C.
Implementation using 60°-displaced coordinates
The control procedure has been significantly simplified by representing the normalized reference voltage and the inverter vectors in the 60°-displaced coordinates system G H as shown for a three-level inverter in Fig. 7. The three inverter stages voltage vectors have simple integer coordinates in G-H system. Also the relationship between the switching variables and the G-H coordinated is simple integer expression. As for any stage, the inverter vector G H coordinates are given by:
1 -11 [1Ic:; 1 [ VH
=
�JC
0
(2)
Where VDcis the stage DC voltage and O"ABC is the stage switching variable, i.e. x, y and z for the high medium and low voltage stages respectively. This simplifies the voltage vector approximation procedure to a mostly integer calculations [18]. The comparisons to determine the location of the reference vector in terms of various domains have been abandoned and the valid next states have been determined by repeating the comparison of the reference vector coordinates with all the vectors domains; thanks to the simple comparison expressions. The low voltage stage has been controlled by rounding the normalized low reference G-H coordinates and reversing the relationship expressed in (2) to determine ZABC. With this implementation the memory and execution time have been considerably reduced but some errors are generated
60
due to the fact that G-H rounding does not lead to the best vector approximation all the time.
(3) Where CI_6 and SI_3 are the comparators used to determine the domain borders crossing as shown in Fig. 8.
Vref,g
X8t---t--..(2,0)
Fig. 7.
The GH coordinate system and the normalized coordinates of a three level inverter.
D. The present work hypothesis The proposed control method is described for the hybrid three level inverter shown in Fig. I and is based on the cascaded controller structure shown in Fig. 5. The control technique, however, has been modified to seek a simpler implementation and more robust control. The control concept described in this section can be explained for high and medium voltage stages as the sub inverter holds its switching state as long as it can lead to the reference approximation. This function can be viewed as a hysteresis comparator that deals with inputs represented as vectors in two-dimensional space. The characteristics of the various stages comparators are determined by the stage domain and the form of adjacent states domains overlap. II.
HIGH VOLTAGE STAGE CONTROLLER
In the proposed implementation, the three binary digits representing the high voltage switching state, XABC are held by three RS flip-flops as indicated in Fig. 8. The vector corresponding to the present high state is always subtracted from the reference vector. If the difference (Vref.g,d, Vref,h.d) is located within the hexagonal hysteresis band,or the state domain, then the switching state is preserved by keeping the R S signals inactive. When the difference vector exceeds the hysteresis region it will be detected by one of the comparators design to determine the excess segment as defined in Fig. 9. The comparators signals trigger the Set or Reset signals according to the relationship between the binary expressions of the present and the new state indicated in Fig. 6. The triggering signals have been composed as a set of combinational logic expressions that have the following form:
COll1pinational Logic
Fig. 8.
The high voltage stage logic controller
MEDIUM VOLTAGE STAGE CONTROLLER
The switching state of each medium voltage stage full bridge cell has been held by two flip-flops, each controls one of the full bridge arms. The flip-flops outputs are denoted by YAI and YAO for phase A. Table I defines the code used to represent the three switching states. The advantage of this coding is that the 2-bit values can be directly used to drive the switching devices without further decoding. Also this coding reflects the full bridge characteristic to have two zero-producing switching states and, hence, provides a simple method to balance the devices currents.
I I
I I I
c)
I
Fig. 9.
" I I
The comparators to determine the high voltage state transition.
61
TABLE I THE 2-BTT CODING USED TO REPRESENT THE MEDTIJM VOLTAGE STATE IN THE PROPOSED CONTROLLER.
Base-3 State (y)
Bride voltage
olp
Yl
yo
0
-3Vs
0
1
1
0
Oil
Oil
2
3Vs
1
0
(=Yl)
The design of the medium voltage stage controller is based on the distribution of the medium stage domains in a high state domain shown in Fig. 10. This distribution shows that the border of one domain with an overlapping one is always formed by two halves of the hexagon adjacent sides. Therefore, the six detectors to indicate the exceeding reference have been characterized as shown in Fig. I I. In this figure, the action of the medium stage controller has been also indicated as an increment or decrement in one of three differences defined as follows:
L1YA l(YA - YB) (YA - YC)J L1ys [(Ys- YA) (Ys- YcJ L1Ye [eYe - YA) (Ye - YsJ
Fig. II.
Medium voltage stage domain excess comparators and control actions.
TABLE II
=
=
beyond the medium vector space and the medium stage preserved. The core of the medium stage controller is implemented using a 2-bit saturable up/down counter with a special counting sequence.
THE CONTROLLER ACTION TO CHANGE THE MEDIUM STAGE DUE TO
(4)
=
EXCEEDING THE PRESENTS DOMAIN.
Desired Change
Priority I
Increment
2
L1Yl++
3
Decrement
L1Yn--
Fig.
10.
Medium voltage domains within one high state domain
Table II describes how the medium voltage stage controller implements the increment or decrement commands indicated in Fig. 11. by examples. The controller takes one of three actions according to the priority. First: changing the corresponding switching variable in the desired direction. Second: changing the other two switching variable in opposite direction. Third: if both changes are not possible, then the present switching state is maintained. In other words, the increment or decrement in the state is subjected to saturation as the switching variable y E [0, 2]. If the desired change cannot be realized due to this limit, it implies that the reference is
Initial state
Increase y, Decrease YR
,Y,·
No change
I
Decrease YR
2
Increase y,
3 Low
Example
Action
Next state
120
121
212
201
210
210
120
110
,Yc
001
102
No change
102
102
VOLTAGE STAGE CONTROLLER
The aim of the low voltage stage controller is to approximate the low reference vector,indicated in Fig. 4 to the nearest inverter vector. The low reference is represented in G-H coordinates. The method presented in [ \8] uses the relationship between the G-H representation of the reference and the switching state to approximate the reference in two steps: 1- The reference coordinates rounding: the normalized reference coordinates rounded to the nearest integers; the integer coordinates have been taken as the coordinates of the nearest target vector. 2- The state(s) corresponding to the target vector has been obtained using the following equation, which is the inverse form of equation (2):
[:�:] �[�l \] [:!rereff.,LL 1 =
Zc
,
-\
-2
(5)
The specific solution(s) are obtained by imposing the
three-level switching variables limits Z E [0,2]. This method leads to approximating the parallelogram area around each vector to its center point. However, the
62
best approximation to each reference vector is given by the 90° rotated hexagon around each vector as indicated in Fig. 12. This implies error in approximation if the reference vector is not located in the mutual area between the parallelogram and the hexagon. Therefore, the G-H coordinates of the target vector have to be corrected before determining the switching states according to steps 2. The correction procedure is explained in Fig. 13. In this figure the low stage reference coordinates are denoted by (gref) and (href) and their nearest integers rounding are Gr and Hr respectively. Over the four triangular regions shaded in Fig. l3, the G-H coordinates of the best approximation or nearest inverter vector (Gb, Hb) has to be calculated after considering the following conditions representing the operation of five comparators: Fig. 13. C1 : gref
>
Gr -Hr +href
C2 :g ref > 1 + Gr + 2Hr
-
2href
] href H :gref >"2+Gr + --2C4 : gref < Gr + 2H r ] 2href
-t
C3
-
Cs :gref
-
Hr 1 href
