Session T4E
Work in Progress –Test Engineering Program Tamara A. Papalias 1, William DeWilkins 2, and Solaiman Harooni 3 Abstract - A pilot program of lectures and laboratory work in mixed-signal test development engineering has been initiated at San Jose State University with support from Agilent Technologies and National Semiconductor Corporation. Class one uses bench-top equipment and a specifically-designed printed circuit board to explore the basic issues of testing: accuracy, guard bands, design for test (DfT), DSP-based tests, load board design, and the blocks of the per-pin architecture present in all manufacturing testers. Class two revisits many of the issues of class one in off-line and on-line programs for a variety of manufacturing testers. The trade-offs of accuracy versus test time are focal. This paper outlines the primary course sequence and its laboratory work. Index Terms – DSP-based test, design for test (DfT), mixedsignal test, test development. INTRODUCTION A series of courses on test development engineering are being developed and implemented at the electrical engineering department of San Jose State University. While an electrical engineering education focuses on issues of design, EE-trained engineers fill an array of jobs in the IC industry. Specifically, as systems-on-chip (SOC) increase in popularity, their complexity drives the cost of testing to become dominant. With typical training programs of 18 months for new test engineers, the industry would benefit from candidates with exposure and aptitude for the specific array of skills needed in the development of IC testing.
The lab also includes workstations with SmarTest, the off-line tester simulation software for Agilent’s 93K testers. Networking is planned to allow the students access to a local tester at specified times. CLASS ONE The first class has been designed to introduce students to the techniques and issues of test engineering through a bench-top, hands-on environment. A group of practicing test engineers from Agilent Technologies and National Semiconductor joined San Jose State faculty to generate lecture material [1], laboratory exercises and a test board for lab work (Figure 1). A bare test board and a pile of components is provided to each student. The soldering of through-hole and surfacemount components allows the students first-hand knowledge of the parasitics of non-ideal connections. This exercise naturally leads to the first laboratory on measurements. A set of resistors is given to each lab group—half are composed of carbon and the other half of metal film. Students measure the resistance of every resistor to analyze the distribution. Students then investigate the inaccuracies of their measurements and are introduced to the 4-wire measurement method. Resistance measurements are collected versus temperature, guardbanding is discussed, and histograms are generated.
LABORATORY Every bench in the lab has been outfitted with the necessary equipment to model a per-pin tester environment. Students first manipulate the equipment manually and work towards computer automation. A list of equipment is provided in Table 1.
Equipment Agilent 34401 Agilent 52624A Agilent E3620A Agilent 33120A Weller WTCTP Fluke 187 -
TABLE I LIST OF EQUIPMENT PER LAB BENCH Description 6.5 Digit Digital Multimeter 4-channel 100MHz Digital Oscilloscope Triple Output Power Supply (quantity = 2) Function Generator Soldering Iron Handheld Multimeter Log Book of Bench Use
Figure 1. Class Test Board Supplied to Each Student
1
Tamara A. Papalias, Professor of Electrical Engineering, San Jose State University, San Jose, CA,
[email protected] William DeWilkins, Global Test Applications Manager, Agilent Technologies, Santa Clara, CA,
[email protected] 3 Solaiman Harooni, Product Engineer, National Semiconductor Corporation, Santa Clara, CA,
[email protected] 2
0-7803-9077-6/05/$20.00 © 2005 IEEE October 19 – 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference T4E-24
Session T4E The final project for the course requires the students to choose a current production part, design an evaluation board, characterize the performance of their board, and present the results to a panel of test engineering professionals. These professionals also reviewed the students’ lab notebooks. CLASS TWO
Figure 2. Op Amp Test Loop Circuit The second lab presents a standard op amp test loop as shown in Figure 2. Students take DC measurements such as gain, offset voltage, and common-mode rejection ratio after tackling the bias and stability of the feedback loop. This is the first introduction of testing circuitry, using additional components to make it easier to take measurements. Students are reminded of accuracy issues, especially in regard to the settings of the test equipment. The third lab challenges the students with 8-bit digital-toanalog converters (DACs) and analog-to-digital converters (ADCs). Students determine the size of the least significant bit as well as full-scale. The quality of conversion is found in differential nonlinearity (DNL) and integral nonlinearity (INL) measurement standards. Since DACs and ADCs are the core of digitizers and arbitrary waveform generators within testers, examining this basic block prepares the student for the tester environment. The fourth lab integrates the previous labs into one. First students measure basic AC characteristics of the op amp under test. Next, they measure the gain and phase effects on a signal traveling through the DAC in series with the ADC. Finally, they repeat the measurement of the AC characteristics of the op amp while it is in a loop with the DAC and ADC, as in Figure 3. This lab most closely represents the manufacturing test environment and introductory DSP testing techniques [2] similar to those used in test programs generated to evaluate production ICs.
The second class revisits the basic mixed-signal blocks in the manufacturing tester environment. Students navigate off-line tester simulators to characterize voltage regulators, clock chips, op amps, DACs and ADCs. On-line tester work will be accomplished at local companies. Universal tester issues like timing, levels and vectors are presented in generic form along with focused calibrations, correlation, and shmoo plots. Students will have exposure to a number of tester platforms. Since many of the students were able to acquire summer internships related to test engineering, their course work will be continued on the platform which they have become accustomed to. Teamwork on laboratory assignments ensures exposure to multiple platforms. Students will leave this class with simple, working tester programs for each of the four main mixed-signal tester companies: Agilent, Credence, Eagle, and Teradyne. Development for this class continues; it will be offered for the first time in the fall semester of 2005. CONCLUSION Two classes are presented that form the core of a test development engineering program. The first is focused on bench-top analysis and debugging skills, while the second involves programming testers for standard mixed-signal blocks. Other courses are planned to broaden the program. One class will explores the issues that arise in RF testing. Since many of the package and board parasitics degrade IC evaluation at RF frequencies, built-in self test (BIST) techniques are the major component. Another class will present graduate-level issues of Design-for-Test (DfT) systems. A project course is also planned to allow student groups to address current topics provided by local industry. This unique program strives to bring the developing area of test engineering into the university. Economics of test, precision of instruments, and correlation issues of off-shore testing are now available in the university setting and at the undergraduate level. Success will be measured through continued contact with the students who have participated in the program. Feedback will be solicited from both the students and their managers to gauge the effectiveness of the program. REFERENCES
Figure 3. DAC-DUT-ADC Loop to Represent Tester
[1]
Burns, Mark and Roberts, Gordon W., An Introduction to Mixed-Signal IC Test and Measurement, Oxford University Press, 2001.
[2]
Mahoney, Matthew, DSP-Based Testing of Analog and Mixed-Signal Circuits, IEEE Computer Society Press, 1987.
0-7803-9077-6/05/$20.00 © 2005 IEEE October 19 – 22, 2005, Indianapolis, IN 35th ASEE/IEEE Frontiers in Education Conference T4E-25
