תכן חומרה בשפת VERILOG

‫תכן חומרה בשפת ‪VERILOG‬‬

‫סמסטר ב ' תשע " ג‬ ‫מרצה ‪ :‬משה דורון‬ ‫מתרגלים ‪ :‬אריאל בורג ‪ ,‬חן חג ' ג '‬ ‫הפקולטה להנדסה‬ ‫‪1‬‬

Course Topics - Outline             

Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling Lecture 6 - Data flow modeling Lecture 7 - Gate Level modeling Lecture 8 - Tasks and Functions Lecture 9 - Advanced Modeling Techniques Lecture 10 - System Tasks and Compiler directives Lecture 11 - Switch Level modeling Lecture 12 - Coding Styles and Test Benches Lecture 13 - Synthesis issues 2

Lecture 1 - Introduction               

Course Objectives Evolution of CAD What is HDL What is Verilog Verilog History Design Advantages Language Capabilities Levels of Abstraction Design Flow Design Methodologies Basic Unit – module Structural Hierarchy Description Style Module Ports Module Instantiation Exercise 1 3

Course Objectives  Gain thorough understanding of the essential concepts

and capabilities of Verilog HW Description Language  Gain practical experience in writing Verilog code for

Hardware Systems Design, Verification and Synthesis  Participants will be able to approach their Verilog-

based Digital Design Projects with confidence

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Evolution of EDA  Over 30 years, Integrated Circuits (ICs) scaled up in

complexity from hundreds gates to millions gates  Electronic Design Automation (EDA) techniques evolved,

enabling Chip Designers to cope with the ever increasing design complexity  Today, EDA support HW Design Languages, Behavioral

Simulation, Functional Verification, Synthesis to GateLevel Netlist and Automatic ICs Placement and Routing  During last 4 years, the hot trend is High Level Synthesis 5

What is Hardware Description Language (HDL)  A convenient, powerful, Device-independent

representation of Digital Logic (Behavior and Structure)  Boosts Design Methodology: Functionality can be

verified early in the design process. Simulation at a higher level, enable architectural evaluation and decisions.  Coupling HDL Compiler with Logic Synthesis tools,

automatically converts a Technology-independent HDL Design description and Functionality to a Gate-Level implementation, in different target Technologies. 6

What is Verilog  One of the two major HDLs used by Hardware

Designers in Industry and Academia. Ada-like VHDL is the other one  Advantages:

C- based Syntax, easy to master and use Condensed and efficient code Intensively used by Israeli Hi-Tech Industry  Disadvantage:

Poor constructs self-checking 7

Verilog History • 1985: Introduced as Hardware modeling

language by Gateway Design System • 1990: Cadence acquired Gateway and became

the language owner • 1995: Verilog became an IEEE Standard 1364 • Verilog 2001 fixed lot of Verilog 1995 problems 8

Verilog – Design Advantages  Single Language for Design & Simulation  Increased ability to work with massive HW design  HW documentation, Design reuse  Verilog Simulator Tools allow you to perform the

following tasks in the design process without building a Hardware Prototype: - Determine the feasibility of new design ideas - Try more than one approach to a design problem - Verify Functionality - Identify Design Problems 9

Language Capabilities  Design can be described in a wide range of levels:

Switch, Gate, Register Transfer Level (RTL), Algorithmic  Design can be modeled in a mixed style –

Behavioral, Dataflow and Structural  At the Behavioral level, Design can be described in RTL ,

Architecture and Algorithmic levels  Hierarchical design can be described, up to any level,

using the module instantiation construct  A design can be of arbitrary size. No limit imposed 10

Language Capabilities (2)  Two data types:

net (wire) & variable (reg - abstract data storage element)  Primitive Logic Gates and Switch-Level Gates, are built-in  Language used for Test Bench - Stimuli & Monitor results  Flexibility of creating a Combinational or Sequential,

User Defined Primitive (UDP)  Programming Language Interface (PLI), allow foreign

functions access Verilog module info – enables Designer’s interaction with the Simulator 11

Levels of Abstraction Verilog is a High-level Language, having constructs supporting various Design’s Abstraction Levels: (Top-to-Bottom)  Behavioral - A module is implemented in terms of desired

algorithm, without knowing the HW implementation details.  Data Flow- A module is designed by specifying the data flow

between registers and how data is a processed. (RTL)  Gate Level- A module is implemented in terms of logic gates

and the interconnections between them.  Switch Level- A module is implemented in terms of switches

(transistors), storage nodes, resistors and the interconnections between them. 12

Design Flow using Verilog Specification Architecture Design Coding in Verilog

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Function/Performance Definition Structure and Function (Behavior) of the Design Efficient, well-documented coding

Simulation & Verification

Design Behave as Required? Timing: Waveform Behavior

Compilation

HDL description into Netlist

Synthesis

Logic Optimization

Mapping

Mapping Verified Design to target HW - FPGA or ASIC

Design Methodologies

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Basic Unit – The Module  Verilog describes a digital system as a set of modules

 Element or a collection of lower level design blocks  A module can be instantiated in another module  Each module has an interface and contents description  Modules communicate externally with input, output

and bi-directional ports 15

Module Structure module module_name (port_list) ; declarations: port declaration (input, output, inout, …) data type declaration (reg, wire, parameter, …) task and function declaration statements: initial block Behavioral always block module instantiation gate instantiation Structural UDP instantiation continuous assignment Data-flow endmodule 16

Example - AND module (data flow & behavioral) module AND (out, in1, in2) ; // input in1, in2 ; output wire out ; assign out = in1 & in2 ; // data flow - continuous Assignment endmodule in1 out in2 module AND (out, in1, in2) ; // input in1, in2 ; output reg out ; // must be reg type when used as LHS in an always block always @( in1 or in2) // always block (sensitivity list) - behavioral out = in1 & in2 ; /* statements inside always block are executed only when one or more signals in the list changes value */ endmodule 17

Example - NAND (gate level) module a b

nand

q

module Nand (q, a, b) ; // output q ; input a, b ;

nand (q, a, b) ; // Language gate primitive endmodule 18

Example – D_FF (behavioral) module d q clk nrst

module D_FF(clk, nrst, d, q) ; input clk, nrst, d ; output reg q ; always @(posedge clk or negedge nrst) // Event-based Timing Control if (!nrst) // reset state q