02 Introduction to VHDL

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Digital Design - 1990. M.Morris Mano £33. Prentice-Hall International ISBN 0-13- 212994-9. • Computer Engineering ( Hardware Design ) - 1988. M.Morris Mano ...
VHDL - a recapitulation

Books - Archaic • Digital Design - 1990 M.Morris Mano £33 Prentice-Hall International ISBN 0-13-212994-9 • Computer Engineering ( Hardware Design ) - 1988 M.Morris Mano £33 Prentice-Hall International ISBN 0-13-162926-3

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Books - Less Archaic • Digital Design (Principles and Practices) - 3rd Ed. 2000, John F Wakerly £37 Prentice-Hall International ISBN 0-13-082599-9 • Logic and Computer Design Fundamentals - 2000 Mano,M. Morris; Kime,Charles R. £30 Prentice-Hall International ISBN 0-13-012468-0 – p.s. Prices from Waterstones as of 20/10/2000, not that I’m recommending them for sales. 33

Oh, and…

• http://tech-www.informatik.uni-hamburg.de/vhdl/ lots of VHDL links including to Peter Ashenden’s ‘VHDL Cookbook’

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VHDL- Overview • VHDL= VHSIC Hardware Description Language • Commissioned for US Department of Defense contracts – Initially for simulation only !

• Looks similar to programming language ADA (which is like Pascal) • Now governed by IEEE standards – 1076-1987/1993

• Popular description language for European design houses • Support from all major CAD tool vendors – Lots of different design tools available 35

VHDL - Overview • The job : – Create Hardware designs – Create Hardware designs which can be Synthesised – Create Hardware designs which can be simulated / verified » Allow for the creation of test vectors » Functional verification » Timing verification

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Why/Why not Machine Code ?

• You’ve been asked to code “The Sims VIII - It’s a Jungle Out There” by Maxis. C++ or assembler, and why ?

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VHDL- A First Look I • Each description comprises 2 components – Interface description- a list of the connections (ports) in and out – Architecture body- some description of how the block works A Z B

– A,B,Z are the interface – AND gate is the architecture 38

VHDL- A First Look II • So, what does the corresponding code in VHDL look like for our simple AND gate ? architecture MYARCH of ANDGATE is

entity ANDGATE is port ( A,B: in std_logic; Z: out std_logic );

begin Z 1 then output changes after some time (propagation delay)

• Synchronous – We have a notion of state – Contains gates + Flip-Flops – We have to clock the system before changes take place 43

Simple Combinatorial Architectures- I • Back to our simple AND gate example.. • Reserved VHDL keywords are in bold, lower case The architecture name (can be anything)

The corresponding entity for this architecture

architecture MYARCH of ANDGATE is begin Z