VHDL Primer

A VHDL Synthesis Tutorial First Edition

Valentina Salapura Michael Gschwind

Technische Universität Wien Vienna, AUSTRIA

© Copyright 1997 by V. Salapura and M. Gschwind

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1. VHDL Primer 2. VHDL Simulation 3. Exercise 1: Simulation of an ALU 4. VHDL Synthesis Primer 5. Synthesis and Gate Level Simulation with Synopsys 6. Exercise 2: Synthesis of an ALU 7. Modeling Sequential Logic and Finite State Machines 8. Resource Sharing 9. Exercise 3: Design of a Digital Thermometer

For bug reports, please contact YDOHQWLQD#YOVLYLHWXZLHQDFDW

Disclaimer: the authors make no warranty of any kind with regard to this material, including, but not limited to, the implied warranties or merchantability and fitness for a particular purpose.

© Copyright 1997 by V. Salapura and M. Gschwind All rights reserved. This book may be copied for noncommercial purposes. The material from this booklet may not be excerpted or stored in any other medium.

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VHDL Primer Valentina Salapura Michael Gschwind

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© Copyright 1997 by V. Salapura & M. Gschwind

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About this VHDL primer ◆ ◆ ◆ ◆

this is not a complete description of VHDL concepts have been simplified only issues and constructs related to synthesis are explained in this overview refer to a VHDL textbook for a full and exact description of the language

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VHDL ◆ ◆ ◆

◆ ◆ ◆

VHSIC (Very High Speed Integrated Circuit) Hardware Description Language developed by DARPA Very High Speed IC Initiative sponsored by US Department of Defence IEEE standard hardware description language – IEEE Std. No. 1076 since 1988 developed for design specification and validation required for government defence projects by DoD similar to ADA programming language – also developed by DoD 78:LHQ


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VHDL references ◆

◆

◆

The VHDL Cookbook, by Peter J. Aschenden – available via FTP ftp://ftp.vlsivie.tuwien.ac.at/pub/hdl/ VHDL-Cookbook.tar.Z Peter J. Ashenden The Designer’s Guide to VHDL Morgan Kaufmann Publishers, Inc. IEEE Standard 1076-1987 IEEE Standard VHDL Language Reference Manual

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VHDL descriptions a design can be described in VHDL at different abstraction levels: for the description at the behavioral level, register-transfer level and at the gate level appropriate for describing both hardware structure and behavior

◆

◆

structure

behavior

A

Y = AB + AB Y

B 78:LHQ


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VHDL as a programming language ... ◆ ◆ ◆

◆

◆ ◆ ◆

several constructs in VHDL like in programming languages (not hardware specific) comments : two hypens -identifiers : letter {[underline] letter number} 7KLV1DPH WKLVQDPH 7KLVB1DPH 7KLV1DPH numbers : integer and real, in bases 2 - 16 (( DEF character constants : using single-quote marks =

string constants : using double-quote marks bit strings: B⇒2, O ⇒8, X ⇒16 %;$ 78:LHQ


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Data types ◆ ◆

◆

data type has to be declared - VHDL strongly typed language data type specified using type definition W\SHidentifierLVtype_definition basic data types – scalar » » » »

integer types floating point types physical types enumeration types

– composite » arrays » records

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Scalar data types ◆

◆

◆

◆

integer: integer values within a specified range W\SHsmallLVUDQJH0WR100; W\SHbit_indexLVUDQJH31GRZQWR0; floating point: real values within a specified range W\SHprobabilityLVUDQJH0.0WR1.0; physical: for physical quantities (mass, voltage, time...) QVPP enumeration: possible values are listed W\SHbooleanLVtruefalse W\SHweekendLVsaso 78:LHQ


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Composite data types - arrays ◆

array: indexed set of elements of the same type – one-dimensional and multidimensional – constrained and unconstrained – example: one-dimensional, constrained W\SHwordLVDUUD\31GRZQWR0 RIbit – example: multidimensional, constrained W\SHregister_bankLVDUUD\0 WR31 RI word – example: one-dimensional, unconstrained W\SHwordLVDUUD\positiveUDQJH! RI bit 78:LHQ


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Composite data types - records ◆

record: set of elements of different types W\SHinstructionLVUHFRUG op_codeprocessor_op operand1: LQWHJHUUDQJH0WR15 operand2LQWHJHUUDQJH0WR15 HQGUHFRUG

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Subtypes ◆ ◆ ◆

constrained subset of some data type subtypes of scalar types and arrays examples: W\SHdaysLVmotuwethfrsa VR VXEW\SHweekend LVdays UDQJHsa WRso W\SHbin_vectorLVDUUD\LQWHJHUUDQJH ! RIbit VXEW\SHwordLVbin_vector31GRZQWR0 78:LHQ


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Objects ◆ ◆

object: named item having value of a specified type three classes of objects – constants – variables – signals FRQVWDQWcrc_polbit_vector7GRZQWR0 00110011 YDULDEOHcrc_accbit_vector7GRZQWR 11000011 VLJQDOcrc_regbit_vector7GRZQWR0 78:LHQ


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Operators ◆

◆

◆

◆

logic operators DQGQDQGRUQRU[RUQRW arithmetic operators

DEVPRG relational operators !! concatenation operator

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Execution in VHDL ◆ ◆

◆ ◆

statements in VHDL can be executed sequentially and concurrently sequential statements only contained in processes – detailed explanation later, see PROCESS statement several statements can be executed both sequentially and concurrently statements which can be executed both sequentially and concurrently – signal assignment – procedure call statement 78:LHQ


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Sequential and concurrent execution ◆

◆

statements executed sequentially: – variable assignment – IF statement – CASE statement – LOOP statement – NULL statement statements executed concurrently: – PROCESS statement – conditional signal assignment – selected signal assignment – component instantiation statement 78:LHQ


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Assignments and NULL statement ◆

◆

◆

variable assignment – sequential statement a new_value-- a is variable signal assignment – can be executed both sequentially and concurrently b new_value-- b is signal NULL statement QXOO 78:LHQ


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IF statement ◆

IF statement LIcondition_1WKHQ sequence_of_statements HOVLIcondition_2WKHQ sequence_of_statements HOVH sequence_of_statements HQGLI

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CASE statement ◆

CASE statement FDVHexpressionLV ZKHQchoice_1 ! sequence_of_statements ZKHQchoice_2 ! sequence_of_statements ZKHQRWKHUV ! sequence_of_statements HQGFDVH

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LOOP statement ◆

◆

◆

infinite loop label: ORRS sequence_of_statements HQGORRS basic loop statement can be extended to while or for loop label:ZKLOHcondition_IRUparameter ORRS sequence_of_statements HQGORRS NEXT and EXIT expressions optional – NEXT: starts the next loop iteration – EXIT: exits the loop 78:LHQ


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Examples of LOOP statement ◆

◆

while loop Loop_1ZKLOHindxmaxORRS indx indx1 HQGORRS for loop Loop_2IRUindxLQ1WR maxORRS vector_aindx 0 HQGORRS

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Subprograms ◆

◆

two forms – procedures – functions defined in two parts – declaration » interface

– body » implementation ◆

statements in a subprogram are executed sequentially 78:LHQ


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Subprogram declaration ◆

◆

declaration syntax – procedure SURFHGXUHname formal_parameter_list; @ – function IXQFWLRQname>formal_parameter_list @ UHWXUQtype_result declaration example – procedure SURFHGXUHreadLLQRXWline valueRXWstd_logic – function IXQFWLRQshlargsignedcountunsigned UHWXUQsigned 78:LHQ


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Subprogram body ◆

syntax subprogram_specificationLV subprogram_declarative_part EHJLQ subprogram_statements_part HQGname

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Example: function body IXQFWLRQmaxLRinteger UHWXUQintegerLV EHJLQ LIL!RWKHQ UHWXUQL HOVH UHWXUQR HQGLI HQGmax 78:LHQ


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Calling of subprograms ◆

◆

if calling subprograms, parameters may be passed through – parameter position UHDGact_linenew_value – parameter name UHDGvalue !new_value L !act_line overloading - several subprograms with the same name – subprogram is selected using the number and type of parameters 78:LHQ


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Package ◆ ◆ ◆

encapsulated modules for structured programming collection of data types, constants, and subprograms defined in two parts – package declaration » interface description

– package body » implementation ◆

package usage XVHpackage_nameDOO XVHstd_logic_1164DOO 78:LHQ


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Package declaration ◆

◆

syntax SDFNDJHidentifierLV package_declarative_part HQGidentifier example SDFNDJHstd_logic_1164LV W\SHstd_logicLV U X 0 1 Z W L H - W\SHstd_logic_vectorLVDUUD\ naturalUDQJH! RIstd_logic IXQFWLRQand LRstd_logic_vector UHWXUQstd_logic_vector HQGstd_logic_1164 78:LHQ


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Package body ◆ ◆

◆

contains subprograms implementations syntax SDFNDJHERG\nameLV package_body_declaration_part HQGname example SDFNDJHERG\std_logic_1164LV IXQFWLRQand LRstd_logic_vector UHWXUQstd_logic_vectorLV EHJLQ HQGand HQGstd_logic_1164

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VHDL description of a function block ◆

consists of – entity » description of the function block interface » contains generics and ports

– architecture body » implementation of the block functionality » multiple architecture bodies for same interface can be defined ◆ different performance ◆ different size ◆ different abstraction levels ◆ different detail ◆ for simulation or for synthesis

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Entity declaration ◆ ◆

ports – input, output, inout generics – parameterize function blocks – select templates parameters » delay (gates, …) » bit width (RAM, ALU, adder, …) » implementation (multiplier, divider, …)

◆

syntax HQWLW\identifierLV JHQHULFgenerics_constants_list SRUWport_list HQGidentifier

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Example: entity declaration HQWLW\processor LV JHQHULFwidthinteger SRUWclockLQstd_logic addressLQstd_logic_vector31GRZQWR0 dataLQRXWstd_logic_vector31GRZQWR0 controlLQstd_logic_vector5GRZQWR0 readyRXWstd_logic HQGprocessor

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Architecture body ◆ ◆

◆

contains the implementation of the block functionality several architecture bodies may be specified for each entity – different implementations architecture bodies implemented at different abstraction levels – structural » block diagrams, net lists

– RTL » operation description using formulas

– behavioral » procedural description 78:LHQ


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Architecture body syntax ◆

syntax DUFKLWHFWXUHidentifierRIentity_name LV architecture_declarative_part EHJLQ architecture_statements_part HQGidentifier

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Structural description ◆

◆ ◆

block functionality described as interconnection of smaller and simpler components – net list, schematic hierarchical block structure contains – components » function blocks, usage of existing design entities

– signals » for interconnection of components ◆ ◆

advantage: easily mapped on hardware disadvantage: bad readability and overview 78:LHQ


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Components ◆ ◆ ◆

◆

for structural descriptions, interconnected with signals existing entities used as components component described at different abstraction levels – different levels of detail component used in a structural description has to be – declared » in the architecture body declaration part

– instantiated » in the architecture body statements part

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Component declaration ◆ ◆

◆

in architecture body declaration part syntax FRPSRQHQWidentifierLV JHQHULFgeneric_constants_list SRUWport_list HQGFRPSRQHQW example FRPSRQHQWcounter JHQHULFN: integer SRUWclock resetLQstd_logic yRXWstd_logic_vector0 WR N-1 HQGFRPSRQHQW 78:LHQ


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Component instantiation ◆ ◆ ◆

◆

in architecture body statements part specify connections and parameters for generic parameterizable modules syntax labelnameJHQHULFPDSgeneric_list SRUWPDSport_list parameter for example parameterizable blocks u3counterJHQHULFPDS4 SRUWPDSclk, n245, n254 connections 78:LHQ


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Structural description - example ◆ ◆

multiply-and-accumulate function block block diagram FORFN LQ LQ

ACC UHVXOW 78:LHQ


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MACC Entity HQWLW\ maccLV SRUW in1LQstd_logic_vector7GRZQWR0 in2LQstd_logic_vector7GRZQWR0 clockLQstd_logic resultRXWstd_logic_vector15GRZQWR0 HQGmacc

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Architecture body - structural description DUFKLWHFWXUHstructure RImaccLV VLJQDOmul_resstd_logic_vector15GRZQWR0 FRPSRQHQWmult SRUWabLQstd_logic_vector7GRZQWR0 yRXWstd_logic_vector15GRZQWR0 HQGFRPSRQHQW FRPSRQHQWacc SRUWaLQstd_logic_vector15GRZQWR0 clkLQstd_logic yRXWstd_logic_vector15 GRZQWR0 HQGFRPSRQHQW EHJLQ multiplymultSRUWPDSin1in2mul_res accumaccSRUWPDSmul_resclockresult HQGstructure 78:LHQ


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RTL description ◆ ◆ ◆ ◆

◆

◆ ◆

register transfer level description at higher abstraction level operations described with formulae usage of signals – for value exchange between formulae functionality described as calculation of new signal value from other signals \Q I\N\O advantage: good readability disadvantage: complicated mapping on hardware 78:LHQ


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Simplified VHDL simulation model ◆

execution of a VHDL description – statements in an endless loop – all statements executed repeatedly – signal change visible only in the next simulation loop iteration » signals introduce one unit delay » abstract model of hardware delay

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Consequences of signal delay ◆

◆ ◆

in architecture body all statements executed concurrently – corresponds to hardware where all components and wires concurrently active order of concurrent statements not important exact delay of signals possible using “after” clause

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Execution of concurrent statements ◆

exercise: – write an RTL description for the following block diagram a

b

y2 y1 y3 78:LHQ


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Solution HQWLW\simpleLV SRUWabLQstd_logic y1y2y3RXWstd_logic HQGsimple DUFKLWHFWXUHarchRIsimpleLV EHJLQ y2 aDQGQRWb y1 QRWa DQGb y3 aRUQRWa DQGb HQGarch 78:LHQ


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AFTER clause ◆ ◆

◆

defines exact delay syntax target value_expressionDIWHU time_expression example out2 QRWin2 DIWHU5 ns in2 out1DIWHU1 ns

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Concurrent statements ◆ ◆

◆

signal assignment conditional signal assignment – corresponds to sequential IF selected signal assignment – corresponds to sequential CASE

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Conditional signal assignments ◆ ◆

◆

concurrent IF syntax target ^waveformZKHQconditionHOVH` waveform example reset 0 1 DIWHU10 nsZKHQ short 1 HOVH 0 1 DIWHU25 ns

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Selected signal assignment ◆ ◆

◆

concurrent CASE syntax ZLWKexpression VHOHFW target ^waveformZKHQchoice` waveformZKHQchoice example ZLWKcodeVHOHFW result a b ZKHQaddition abZKHQsubtract 78:LHQ


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MACC - RTL Description DUFKLWHFWXUHrtlRImacc LV VLJQDOmul_resregstd_logic_vector15 GRZQWR0 rising clock edge EHJLQ reg regin1 in2 ZKHQ clock DQGclock HYHQW UHVXOW reg HQGrtl ◆

VHDL defines attributes for various object types – for signals: ¶HYHQW - signal value has changed

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Behavioral description ◆ ◆ ◆ ◆

◆

descriptions at high abstraction level behavioral VHDL similar to “normal” programming languages encapsulated in VHDL processes advantages – simple and quick description – high simulation speed disadvantages – complicated mapping on hardware – less detailed description 78:LHQ


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Process statement ◆ ◆ ◆

◆

concurrent statement in architecture body – executed concurrently with other statements contains sequential statements – encapsulated statements executed sequentially variables used in a process – variables change value immediately, like in “normal” programming languages signals can still be used – semantics differ from variable ⇒ changes only visible in next iteration of process – useful for communication with other concurrent elements in architecture body 78:LHQ


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Process statement: syntax SURFHVV>sensitivity_list @ process_declarative_part EHJLQ process_statements_part HQGSURFHVV

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Process statement: example P22SURFHVVclockreset EHJLQ LIreset 1 WKHQ reg 0000 HOVLIclock 1 DQGclock HYHQWWKHQ reg 1100 HQGLI HQGSURFHVV

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Building a VHDL description ◆ ◆

in a single VHDL design used many different packages, architecture bodies and entities active components (architecture bodies, packages) for a particular design selected using – libraries – configurations

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Library ◆ ◆ ◆ ◆

encapsulates various related components identified with a logic name design descriptions compiled in libraries for simulation and synthesis order of compilation important – primary library units » have to be compiled first » package declarations, entities, configuration declaration

– secondary library units » package bodies, architecture bodies 78:LHQ


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Using libraries ◆ ◆

◆

referenced with “use” clause example OLEUDU\IEEE XVHIEEEstd_logic_1164DOO XVHIEEEstd_logic_arithDOO library “work” always selected – working library – need not to be referenced 78:LHQ


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Configuration ◆

◆

configuration selects – architecture body for entities – entities for components – generics for components selects architecture body for each instance, e.g. – architecture body with optimized timing for timing critical parts – architecture body with minimal area for area critical parts – behavioral description for fast simulation 78:LHQ


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Configuration syntax FRQILJXUDWLRQidentifierRIentity_name LV use_clause IRUarchitecture_name use_clause IRUblock_name HQGIRU HQGIRU HQGidentifier; ◆

first hierarchical “for” clause specifies architecture body

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Configuration: example DUFKLWHFWXUHsimulateRIadder LV FRPSRQHQWhaddSRUW« HQGFRPSRQHQW EHJLQ %haddSRUWPDS« %haddSRUWPDS« HQGsimulate FRQILJXUDWLRQmixedRIadder LV IRUsimulate IRUB1 haddXVHHQWLW\workhaddrtl HQGIRU IRUB2 haddXVHHQWLW\workhaddsynth HQGIRU HQGIRU HQGmixed 78:LHQ


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Standard logic ◆ ◆

◆ ◆ ◆

standardized data types for portably describing signal values in VHDL IEEE standard multivalue logic system for VHDL model interoperability (Std_logic_1164) – IEEE Std. No. 1164-1993 – defined in ,(((VWGBORJLFB package should be supported by all simulators and synthesis tools simple mapping on hardware arithmetic operations on VWGBORJLF standardized in IEEE 1076.3 synthesis package Numeric_Std 78:LHQ


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Standard logic data types ◆

data type VWGBORJLF: – 8

- not initialized – ;

- unknown, strong –

- 0, strong –

- 1, strong – =

- high impedance (tri-state) – :

- unknown, weak – /

- 0, weak – +

- 1, weak –

- don´t care 78:LHQ


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Other standard data types ◆ ◆

VWGBORJLFBYHFWRU VWGBXORJLF, VWGBXORJLFBYHFWRU – unresolved VWGBORJLF » several drivers drive single bus / wire

◆

VLJQHG, XQVLJQHG – defined in IEEE 1076.3 Numeric_Std – array of VWGBORJLF with integer semantics

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Data type conversion functions ◆

◆ ◆

VHDL strongly typed - but not hardware – synthesis tools have to provide trivial mapping of functions in synthesis package ,(((VWGBORJLFBDULWK most important conversion functions – FRQYBLQWHJHU – FRQYBXQVLJQHG – FRQYBVLJQHG – FRQYBVWGBORJLFBYHFWRU 78:LHQ


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Some conversion functions ◆

◆

◆

FRQYBLQWHJHU – input is LQWHJHU | VLJQHG | XQVLJQHG | VWGBORJLF – return LQWHJHU FRQYBXQVLJQHG, FRQYBVLJQHG – input is LQWHJHU | VLJQHG | XQVLJQHG | VWGBORJLF – return XQVLJQHG, VLJQHG FRQYBVWGBORJLFBYHFWRU – input is LQWHJHU | XQVLJQHG | VLJQHG | VWGBORJLF – parameter LQWHJHU (for width) – return VWGBORJLFBYHFWRU

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VHDL Simulation Valentina Salapura Michael Gschwind

7 8 : H LQ


Introductory note ◆ ◆ ◆ ◆

this collection only gives short overview of simulation concepts have been simplified intended to give basic understanding of VHDL simulation for full information on VHDL simulation check VHDL simulation text book

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Simulation ◆ ◆

◆

for validating VHDL Models simulation shows – whether errors are found for given test vectors – not that the design is correct quality of test vectors is critical for quality of simulation

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Simulation development ◆

1980 - CAE – simulation at the gate level » long simulation time

◆

1990 - High level approach – simulation at behavioral and RTL levels » » » »

usage of test benches procedural description of test vectors simple and quick design at higher abstraction level faster simulation because less detail required

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Usage of simulation ◆

◆

◆

VHDL system simulation – behavioral and RTL description post-synthesis simulation and timing analysis – at the gate level sign-off simulation – after layout and routing » exact timing analysis

7 8 : H LQ


Simulation model ◆ ◆

discrete event simulation simulation controlled by events ⇒ event driven simulation – event – the value of a signal had changed – change of a signal is not immediately executed – assignment of new signal values scheduled along a time axis

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Simulation algorithm ◆ ◆

◆

defined by IEEE VHDL standard 1076 simulation starts with the initialization phase – simulation time = 0 – all objects initialized iterate 2 stage simulation cycle – propagation » all transactions (signal changes) scheduled for this simulation time executed

– evaluation » execute all VHDL modules which react to events occurring in the first stage » schedule new signal changes 7 8 : H LQ


Delta method ◆

two dimensional time t0 t0 + 1 ns

0δ

1δ

2δ

0δ

1δ

2δ

delta

time ◆

guarantees – compatibility between different simulators – determinism 7 8 : H LQ


37

Signal assignment ◆ ◆

t0

without “after” clause input a is ‘0’ at t0 DUFKLWHFWXUHsimpleRIdemoLV EHJLQ b a c QRWb HQGsimple D µ¶ E F µ8¶ 0δ

D E µ¶ F µ8¶ 1δ

D E µ¶ F µ¶ 2δ

delta

t1 time

7 8 : H LQ


Signal assignment (2) ◆ ◆

with “after” clause input a is ‘0’ at t0 DUFKLWHFWXUHsimpleRIdemoLV delta EHJLQ D µ¶ t0 b aDIWHU 5 ns 0δ E F µ8¶ c QRWb DIWHU1 ns D E µ¶ HQGsimple t0 + 5 ns 0δ F µ8¶ t0 + 6 ns

0δ time

D E µ¶ F µ¶ 7 8 : H LQ


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Controlling simulation ◆

evaluate – only the modules affected by changed signals » activation list for concurrent statements » sensitivity list for processes

◆

propagate – only the signals whose value should change

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VHDL for simulation ◆

statements for describing time flow in the simulation – after » for time flow of signal assignments a ³11110000´DIWHU100 ns

– wait » to start and stop a process ZDLWIRU10 ns ZDLWXQWLOreset ’1’; ZDLWRQclock¶HYHQW

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Test bench ◆ ◆

defines the stimuli of a design consists of two components – UUT (unit under test) » tested design

– TG (test generator) » generates stimulus for the design » collects the design’s response, compares with reference values TEST BENCH

TG

UUT

7 8 : H LQ


Types of test bench ◆

◆

system test bench – describes the design environment – designer know how comparison test bench – compares the implementation with a reference model » reference model = expected simulation results at higher abstraction levels or golden device » difficulties with timing differences between the implementation and the reference model TG

=?

UUT

GD 7 8 : H LQ


40

Building a test bench HQWLW\TBLV HQGTB DUFKLWHFWXUHTBARITBLV declarative_part_signals_components EHJLQ instantiate_UUT_and_other_components and_optional behavioral_description_of_TG HQGTBA 7 8 : H LQ


Putting together a simulation model ◆

arranging a configuration – connecting objects » component entity » entity architecture » generics

◆

example FRQILJXUDWLRQcfg_tbRITB LV IRUTBA IRUuutu_entity XVHHQWLW\worku_entityu_arch HQGIRU HQGIRU HQGcfg_tb 7 8 : H LQ


41

Simulation of VHDL models ◆

◆

VHDL model has to be – compiled (analyzed) – simulated simulation using Synopsys – interpreted » » » »

intermediate format (byte code) similar to VHDL source code easy debugging slow simulation

– compiled » translated to machine code » fast simulation 7 8 : H LQ


Working environment for Synopsys ◆

◆

◆

setup file in the working directory .V\QRSV\VBYVVVHWXS – contains data path for system libraries library ZRUN – contains analyzed elements typical working directory - listing OV V\QRSV\VBYVVVHWXS6\QRSV\VFRQILJXUDWLRQ YKGOBILOHYKG9+'/VRXUFHILOH ZRUNFRQWDLQVDQDO\]HGVRXUFH

◆

Synopsys online documentation LYLHZ 7 8 : H LQ


42

Compilation with Synopsys ◆

◆

compilation command (for library work) YKGODQYKGOBILOHYKG compilation to other libraries YKGODQYKGOBILOHYKGZOLEUDU\BQDPH – library name has to be specified in .V\QRSV\VBYVVVHWXS

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Simulation with Synopsys ◆ ◆

Synopsys VHDL debugger - YKGOGE[ select design

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Useful commands ◆

◆

◆

◆

◆

WUDFH – signal selection for waveforms FG – moving through the program hierarchy VWHSQH[W – execute simulation in steps UXQWLPHBH[SUHVVLRQ – simulation start LQFOXGH – usage of scripts 7 8 : H LQ


Vhdldbx - working window

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Vhdldbx - waveforms

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Simulation example: MACC entity XVHworkDOO (17,7

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