2011 IRPS tutorial program

2011 IRPS Tutorial Program Gaudenzio Meneghesso, University of Padova [111] ELECTRICAL CHARACTERIZATION METHODS AND THEIR APPLICATION TO METAL GATE / HIGH-K CMOS RELIABILITY EVALUATION Andreas Kerber, GLOBALFOUNDRIES - Since the 45nm CMOS process technology node metal gate (MG) / high-k (HK) is used in semiconductor manufacturing. The introduction of high-k as a new gate dielectric in combination with a metal electrode brings additional reliability challenges for qualification of advanced technologies nodes previously not encountered with conventional poly-Si / SiON gate stacks. In addition to negative bias temperature instability (NBTI) in pFET devices, positive bias temperature instability (PBTI) and stress-induced leakage currents (SILC) in nFET devices as well as dielectric breakdown are in the focus of MG/HK reliability. This tutorial summarizes recent achievements in the electrical characterization of MG/HK stacks towards understanding the reliability physics for CMOS applications. In particular time resolved characterization techniques are being discussed and various stress modes are being explored to address the reliability impact. Unipolar and bipolar AC characterization techniques are considered beside the conventional DC device reliability characterization methods to assess BTI, SILC and TDDB. Finally, applicability of Voltage Ramp Stress is explored for MG/HK process screening and monitoring. [112] FORECASTING BTI IMPACT IN CIRCUITS - IT'S SUNNY AND HUMID WITH CHANCES OF RAIN - Aditya Bansal and Jae-Joon Kim, IBM T.J. Watson Research - In current high-k metal gate technologies, NFETs and PFETs weaken with time causing circuit performance to deviate from post-fabrication test specifications. Accurate prediction of BTI induced degradation before shipping a product is important to eliminate chip failures at customer site. Prediction of BTI impact on circuits can be classified as model-based or direct. Model based prediction involves generating BTI models for FETs, circuit representation and simulation under usage conditions (voltage, temperature etc.). FET level models are typically extensively verified with hardware under various usage conditions. Alternatively, in direct prediction, representative circuits are implemented to monitor BTI induced degradation. These circuits can be used for BTI characterization during technology ramp-up and/or for monitoring BTI shift in the field. We will discuss in depth the nature of functional failures which differ for each design block; for example, a combination block may suffer from increased delay whereas a memory cell may suffer from stability failures.Further, we'll give a detailed review of the process flow for model-based prediction and existing stateof-the-art BTI stress-recovery characterization circuits. Finally, we will discuss the possible circuit and architecture based solutions to reduce the impact of BTI. [113] RTN ANALYSIS FOR DEFECT IDENTIFICATION IN ADVANCED GATE STACKS - Gennadi Bersuker, SEMATECH - In highly scaled devices and, especially, devices fabricated on high mobility substrates characterized by a relatively low carrier density, fluctuations of the drive current caused by carrier trapping/detrapping at the defects in the dielectrics presents a serious challenge to meeting performance requirements. Indeed, advanced gate stacks, such as metal/high-k dielectrics with a variety of cap layers, barrier-engineered tunnel oxides in charge

trapping memories, etc., exhibit complex compositional profiles, which are usually prone to defect formation. Due to the compositional complexity of these stacks, identifying the nature of traps that contribute to RTN is critically important to process improvement efforts. In the most widely used elastic trapping description, the time of an injected electron capture by a bulk defect is controlled by the electron tunneling from/to the substrate. However, this model was recently shown to be inadequate since it results in RTN times many orders of magnitude shorter than measured ones. A more comprehensive analysis needs to consider that the bulk oxide traps change the atomic configuration of the surrounding lattice when capturing/releasing electrons. These structural changes may control, to a great degree, the characteristic trapping/detrapping times. Therefore, analysis based on explicit consideration of the trap atomic properties provides an opportunity to identify the nature of the defect from the RTN data. The model considering structural relaxation processes is applicable to analyzing charge pumping, trap-assisted tunneling transport, and other measurements probing defects in the dielectrics. [114] HOT-CARRIER DEGRADATION IN ADVANCED CMOS NODES: FROM THE NBTI SHADOW BACK TO THE FRONT SCENE - A. Bravaix, ISEN-IM2NP - For the last ten years, Negative Bias Temperature Instability (NBTI) has eclipsed all other CMOS device degradation modes, including Hot Carrier (HC) degradation. The difficulties in optimizing last CMOS technologies in convergence with aggressive CMOS scaling have recently seen the Hot-Carrier (HC) phenomena back to the front of topics for device and circuit reliability challenges. Besides, Among all these CMOS nodes, the impact of Channel Hot Carriers (CHC), Cold Carriers (CCC) and Non Conductive HotCarriers (NCHC) are indicative of the quality of gate and drain processes and the ability to resist to wearout mechanisms with operating time. This makes the HC examination mandatory to qualify actual CMOS nodes. This tutorial presents the underlying HC mechanisms through basics to advanced analysis focusing the distinction between the channel energetic ‘hot’ carriers (CHC), the channel thermalized ‘cold’ carriers (CCC) and finally the non conductive hot carriers (NCHC) mechanisms. A thorough review of the existing HC modeling yields to a composite lifetime modeling (in three distinctive modes) for the generation of interface traps in advanced CMOS nodes. Oxide charge trapping in thicker gate-oxides is added on top of the generation of neutral traps. All these elements are required to allow a complete modeling function which could be used for both accurate DC and AC device lifetimes. Additionally, temperature effects have a strong effect on the PMOS side through NBTI - and to a lesser magnitude in NMOS under positive bias - we will show that both phenomena are closely interlinked during digital application, while finally, the HC degradation in last CMOS nodes is compared to Self Heating (SH) mechanism which is found much larger in FD SOI technologies than in last silicon bulk 40nm node. This opens new perspectives for an accurate lifetime evaluation of the future scaled CMOS nodes at high frequency operation. [121] FLASH MEMORY RELIABILITY - A. S. Spinelli and C. Monzio Compagnoni - This tutorial will cover the operation principles and the main reliability constraints which affect the performance of scaled floating-gate non-volatile memories. After

introducing the operating principle of the memory cell and the array architecture, the key reliability issues and their underlying physical concepts are described. The tutorial will then address P/E endurance, charge detrapping and SILC phenomena, random telegraph noise and charge injection effects, and will eventually describe some recently-found phenomena that have become important for Flash reliability. The emphasis of the tutorial will be on physical comprehension rather than quantitative modeling, and will mostly rely on published experimental data rather than theoretical extrapolations. [122] RELIABILITY ISSUES ON PCM MEMORIES - Matthew J. Breitwisch, IBM T.J. Watson Research Center - This tutorial will review the reliability issues associated with the phase change memory (PCM) technology and will cover the following topics: an introduction to PCM technology including physical structure and electrical characterization, a review of key metrics for performance and functionality, and a review of reliability issues including endurance, resistance drift, retention, and write disturb. [123] FROM DEVICE TO LIBRARY RELIABILITY IN ADVANCED CMOS NODES Vincent Huard, STMicroelectronics - The continuous scaling of CMOS technologies down to sub-micron range inevitably yields to increased reliability challenges, such as Negative Bias Temperature Instability (NBTI), Time-Dependent Dielectric Breakdown (TDDB) and Hot Carrier Injection (HCI). All these effects, which contribute to degrade transistor temporal performances, cannot be handled anymore by process means only. Reliability mitigation should then be addressed by design strategies of information processing and knowledge ordering. A top-down approach is essentially the breaking down of a system to gain insight into in many compositional sub-systems down to libraries elements (standard cells, IPs) often specified with the assistance of "black boxes". However, black boxes may fail to elucidate elementary mechanisms or be detailed enough to realistically validate the model. A bottom-up approach is the piecing together of systems to give rise to grander systems. In this approach the individual libraries elements of the system are first specified in great detail. These libraries are then linked together to form larger subsystems, which then in turn are linked, sometimes in many levels, until a complete top-level system is formed. Independently of the design strategy chosen for reliability mitigation, libraries elements are always at the heart of the approach. This tutorial will address the need to move from device to library level reliability to handle coming challenges in advanced CMOS nodes. Both basics and advanced topics on reliability modeling and simulation tools will be presented including: transistor-level reliability compact modeling, library-level modeling approach, ageing effects on various kinds of libraries and simulation approaches for hierarchical reliability analysis. [124] TIME-DEPENDENT DIELECTRIC BREAKDOWN (TDDB) IN HIGH-K DIELECTRICS - Robin Degraeve, IMEC The introduction of Hf-based high-k dielectrics as a low-leakage alternative for the SiO2 gate insulator has raised many questions on the reliability issues of these materials. Concerning TimeDependent Dielectric Breakdown (TDDB), the physical and statistical models developed for SiO2 served historically as a

starting point for the research on high-k TDDB. An important change when moving from SiO2 to high-k is the increased defect density, which poses significant extra reliability challenges even in process-optimized layers. Further complications arise from the change from a single-layer oxide to a multi-layer stack consisting of an interface SiO2 layer and a high-k. On top of this, the gate electrode has been changed from poly-Si to metal (usually TiN). This tutorial discusses the theory and applicability of some electrical defect characterization methods in high-k (like charge pumping, charge and sense methods, Stress-Induced Leakage Current,...) and demonstrates how they helped in understanding the details of high-k stack degradation and breakdown. The multilayer aspect of breakdown is discussed with emphasis on the latest developments in the theoretical and statistical models on this subject. The phenomenon of soft, hard and progressive breakdown in high-k is explained and critically evaluated. It is shown how reliability criteria can be constructed in presence of soft and progressive breakdown. Finally, guidelines and boundary conditions for fast TDDB evaluation techniques are presented. For this tutorial, it is assumed that the attendant has basic knowledge of TDDB statistics (Weibull distribution, area scaling,...) and of SiO2 degradation and breakdown concepts (accelerated testing, percolation model,...). [131] SEMICONDUCTOR CHIP QUALIFICATION AND VARIABILITY - Pascal Nsame, IBM STG - The robust functional operation of semiconductor chips over their specified lifetime is a requirement for products in the current and future nanotechnology era. The robustness of key IP with a wide range of functions must be realized in the presence of variability. This tutorial compares and contrasts variability sources such as: design, test, analytics, and manufacturing environments. We analyze the impact of the variability of these components on the reliability models; relative to the target product functional robustness across semiconductor technology nodes from 90nm to 32nm with examples from recent high performance compute systems including advanced processors and custom logic. [132] LATEST DEVELOPMENTS IN FAILURE MODELING OF ELECTROMIGRATION AND ILD TDDB - Jim Lloyd, SUNY Albany College - Recently there has been some progress in the modeling of both electromigration and TDDB for low-k interlevel dielectrics that may impact how these problems are dealt with in engineering. For electromigration, the concept of damage nucleation and growth provides both a more satisfying conceptual framework as well as a more logical method to project lifetimes from test to use conditions than the classical Black Model (n=2) or the modified Black model (which has serious conceptual problems). In addition, the time dependent dielectric breakdown (TDDB) in low-k interlevel dielectrics (ILD) has been shown to behave quite differently than in SiO2 based dielectrics. Here we have seen that several “root-E” models provide a better fit to the empirical data than the classic but controversial E or 1/E models. These new models will be described in detail and compared with the traditional methods and the physical interpretations discussed in detail. [133] ELECTROMIGRATION, THERMOMIGRATION, AND STRESS-MIGRATION IN FLIP CHIP SOLDER JOINTS - K. N. Tu, Dept. of Materials Science and Engineering, UCLA, Los Angeles, CA - Owing to the line-to-bump configuration in flip chip solder joints, electromigration is affected by current crowding

and has a unique mode of failure by growing a pancake-type of void across the contact area at the cathode. Joule heating in interconnect line can induce a temperature gradient across flip chip solder joints, so thermomigration accompanies electromigration. A temperature gradient of 1000 °C/cm or a temperature difference of 10 °C across a solder joint of 100 μm in diameter is sufficient for thermomigration. Phase separation occurs in composite flip chip solder joints driven by thermomigration. It has been found that Sn moves to the hot side. On stress-migration, current crowding drives Sn atoms to the anode and leads to Sn whisker growth.

models, which are commonly used for common IC failure mechanisms, will be discussed. These failure mechanisms include: Electromigration (EM), Stress Migration (SM), TimeDependent Dielectric Breakdown (TDDB), Negative-Biased Temperature Instability (NBTI), Hot-Carrier Injection (HCI), Surface Inversion/Mobile-Ions, Plasma-Induced Damage (PID), Thermal Cycling (TC) , Energy-Density Issues (EDI), and SingleEvent Upsets (SEU). This tutorial will provide the attendee the basics of reliability physics ---- which should serve as a solid foundation for a better understanding of the papers presented at the IRPS.

[134] BEOL RELIABILITY CHALLENGES AND ITS INTERACTION WITH PROCESS INTEGRATION - Oliver Aubel, GLOBALFOUNDRIES - In former technologies nodes the reliability investigation was a central part of the process qualification but mainly served as verification for the technology development success only. In recent technologies, latest since 65nm technology node, the reliability characterization is becoming one major part of the technology development itself. It has strong impact on the choice of process options or necessary process changes. Future technology nodes are very challenging with respect to meeting reliability targets. Only with carefully chosen unit process options and an optimized balance between design and reliability demands, technology nodes of 32nm dimensions and beyond can be successfully introduced.

[142] PHOTOVOLTAIC MODULE RELIABILITY: ENDURING A STORM - Glenn Alers, University of California at Santa Cruz - In contrast to integrated circuits, solar panels need to withstand large variations in environment and weather conditions. Photovoltaic modules must withstand 0-100% humidity at -20C to 100C with voltages up to 1000V and thousands of thermal cycles. Therefore, predicting lifetime is no better than predicting the weather. Yet lifetime estimates directly impact the levelized cost of a power generation system and therefore must be quantified. This tutorial will review the qualification procedures for assuring reliability of photovoltaic panels. The wide range of failure modes for solar panels will be summarized along with the failure analysis techniques that are commonly used. Thermal and emission images are the dominate method for identifying degradation in a solar module.

In this tutorial the interaction between process options and reliability requirements will be covered and several critical aspects to ensure BEOL reliability in 32nm technology nodes and beyond will be discussed. A common key work for intrinsic reliability performance loss is for example the electromigration crisis. Here the reliability robustness is reduced due to scaling leading to reduced critical void volume yielding a resistance increase failure. Aspects such as barrier via side wall coverage or potential etch back issues are not cover is this physics based model. The tutorial will focus on the process related items which overlay the intrinsic reliability performance. [141] BASICS OF RELIABILITY PHYSICS - J.W. McPherson, Texas Instruments - All devices are expected to degrade with time so device reliability is of great practical importance. Reliability investigations generally start with measuring the degradation rate for a material/device and then modeling the time-to-failure versus the applied stress. The term “stress” is very general ---- any external agent (electrical, mechanical, chemical, thermal, electrochemical, etc.) which is capable of producing material/device degradation. Time-to-failure occurs when the amount of degradation reaches some critical threshold level. Timeto-failure (TF) models generally assume either a power law or exponential stress-dependence and with either an Arrhenius or Erying-like activation energy. From these TF models, the all important acceleration factors can be established and serve as the foundation for accelerated testing. During this tutorial, the basics of reliability physics and accelerated testing methods are discussed: degradation rate modeling, TF model generation, TF statistical distribution determination, and acceleration factor development. Several TF

[143] FAILURE MECHANISMS AND THE USE OF ACCELERATED TESTS IN THE DEVELOPMENT OF RELIABLE PV MODULES - John Wohlgemuth, National Renewable Energy Laboratory - Development of reliable PV modules requires an understanding of potential failure mechanisms. The most straightforward way to determine these failure mechanisms is to observe them in the field, but we can’t wait 20 or 25 years (the warranty lifetime of today’s commercial PV module) to see: • • •

What failure mechanisms a module type might suffer from; To get an estimate of lifetime or degradation rate (durability) to see if the product can meet the warranty; To determine if a change in materials or design will have an effect on the safety, lifetime and durability of the subsequent modules.

Therefore we try to develop stress tests that accelerate the same failure mechanisms that have been seen in the field. This tutorial will start with a discussion of observed field failure modes for PV modules. From this list and knowledge of the environment in which PV modules operate, a number of accelerated stress tests have been developed. As the tests became more sophisticated and their use more widespread the lifetime and reliability of PV modules increased. Accelerated stress tests can be utilized in a number of different ways. PV module Qualification tests (like IEC 61215 for crystalline Si or 61646 for Thin Films) have become a commercial tool used by purchasers of PV modules to assure a minimum level of performance and by module manufacturers as both marketing and quality assurance tools. Details of these qualification tests and their strengths and weaknesses will be discussed.

Reliability testing goes beyond Qualification testing to actually cause failures. It is used to: • • •

Make long term predictions about module lifetime; Establish the correct set of accelerated tests to be utilized on new PV technologies; and Support efforts in cost reduction by verifying that inherently lower cost designs or use of lower cost materials do not negatively impact the long term safety, reliability, lifetime or durability of PV modules.

[144] RELIABILITY ISSUES IN OPTOELECTRONICS DEVICES - Matteo Meneghini, Gaudenzio Meneghesso, and Enrico Zanoni, University of Padova - With this tutorial we describe in detail the most important physical mechanisms that limit the reliability of optoelectronic devices, focusing on the case of LEDs and laser diodes. Starting with a brief introduction on the operating principles of advanced LED and laser structures, we will describe in detail a number of case studies focused on the analysis of the following degradation mechanisms: (i) degradation of the active layer due to the generation of nonradiative defects; (ii) degradation of the ohmic contacts of optoelectronic devices; (iii) rapid degradation of laser diodes due to the generation of dark-line defects; (iv) catastrophic degradation of the laser facets; (v) sudden degradation of LEDs and lasers due to Electrostatic Discharge events. This tutorial will give a general overview on the critical factors that limit the lifetime of optoelectronic devices, an on the analytical techniques that can be adopted for identifying the degradation mechanisms. Part of the presentation will be devoted to advanced device technologies such as visible LEDs (for lighting and automotive applications) and Blu-Ray laser diodes. [211] NBTI: RECENT FINDINGS AND CONTRO-VERSIAL TOPICS - Hans Reisinger, Infineon Technologies - Recent investigations of the properties of single defects in the insulators of MOSFETs have created new impact on the controversy about the physical origin of NBTI. Basics and results of these new experiments and corresponding physical models will be explained in other tutorials. This tutorial will be divided in three main parts: Part 1 will take the main findings from the defect spectroscopy experiments and use them to establish an empirical, but physicsbased NBTI model. It will be shown how such a model explains DC-degradation and recovery and also the response to dynamic NBTI stress with arbitrary stress/recovery sequences. Of special interest for combinational logic is high frequency AC-stress. Thus a focus topic will be the understanding of the special features of AC-BTI, for example the duty cycle and frequency dependence and the recovery after AC-stress. Part 2 will present a critical review of the contradicting findings and claims made regarding NBTI. An example for such a claim often said to be generally accepted - is that there is a fast, Tindependent precursor to NBTI. It will be carefully checked if the most popular claims are in agreement with hard experimental facts or may be believed only as a consequence of experimental artifacts.

Part 3 will give an overview over fast measuring techniques which have been presented in the literature. Only the techniques being able to provide insight into the NBTI-physics - in contrast to fast measurements just done for qualification - will be treated. Some of these techniques are based on commercial instruments; other ones require home-made components. Compared will be their performances and limitations with respect to time and their resolution in extracting VT values. [212] CHARGE TRAPPING IN OXIDES: FROM RTN TO NBTI - Tibor Grasser, TU Wien - Even under stationary bias conditions, fluctuations in the terminal currents of MOSFETs can be observed, a phenomenon which has become known as random telegraph noise (RTN). The magnitude of these fluctuations increases with decreasing device area. The commonly accepted interpretation explains the noise as a result of stochastic trapping of charge carriers into oxide or interface defects. Experimental data show that the average capture and emission times of this trapping process exhibit pronounced temperature and bias dependences. Of particular importance is the exponential bias dependence of the capture times, which naturally links RTN to the bias temperature instability (BTI): application of large electric fields results in a dramatic decrease of the capture times, thereby upsetting the dynamic equilibrium typical for RTN. Since the defects present in a MOSFET have a wide distribution of time constants, not all defects capture their charge at the same time. Rather, one defect after the other captures its charge, resulting in slow drifts in the terminal characteristics of the MOSFET. The opposite is observed once the stress field is removed, producing long recovery transients. In nanoscale MOSFETs these degradation and recovery transients proceed in discrete steps, with each step being due to charge exchange of a particular defect with the substrate or the gate. This tutorial starts with a review of the stochastic properties of charge capture and emission, which can be described by a Markov process. Fundamental properties like the probability distribution of the capture and emission times, and their expectation values and variance will be discussed. A special focus will be also put on multi-state defects (switching traps), as have been observed recently. These multi-state defects are of fundamental importance, as they explain not only charge trapping but also defect creation. Next, physical models for the capture and emission times required in the Markov model will be discussed. Conventional models based on elastic tunneling or on an extended Shockley-Read-Hall mechanism can neither explain the bias nor the temperature dependence of the data. In contrast, a non-radiative multiphonon processes appears to be consistent with the data. The basic difference between these models is that the latter also considers the additional thermal energy required to accommodate the distortion of the lattice after a charge capture or emission event. Finally, the implications of these stochastic charge trapping events on the lifetime of nanoscale MOSFETs will be discussed. It will become important to realize that each transistor is unique in various aspects: each transistor will have a random number of defect precursors (scaling with area), each defect will have different properties, and each defect contributes in a stochastic

manner to the measured degradation. As a consequence of the stochastic nature of these processes, the lifetime of nanoscale MOSFETs becomes a stochastic quantity, requiring different qualification procedures. [221] RELIABILITY AND MICROSTRUCTURE OF POLY-SI TFTS - Ryoichi Ishihara, Delft University of Technology - Lowtemperature processed polycrystalline-silicon (LT poly-Si or LTPS) has been used as both pixel TFTs and driver circuits for active-matrix liquid-crystal displays (AM-LCDs), because of the much higher mobility than that of the amorphous silicon TFTs. LTPS TFTs have been widely investigated as a potentially suitable material for organic light-emitting diode (OLED) displays as well. If the mobility of poly-Si TFTs is further increased, this technology will enable realization of system on panel (SOP) that will integrate memory, CPU, and display with wireless data communication. For realization of those future applications, improvements of the mobility, uniformity and reliability of LTPS TFTs are very important. This tutorial will provide an overview of reliability of LTPS TFTs under various static and dynamic operations and its relation with microstructure of LT poly-Si. After introducing fabrication technology for LTPS TFTs, degradations on mobility, flat-band voltage and subthreshold characteristic will be explained in terms of physics of trap generation in LT poly-Si and injection of charges into the gate insulator. In addition, effects of grain boundaries on mobility, uniformity and the bias stabilities will be addressed. Finally, reliability of TFTs fabricated inside a single, orientation-controlled Si grain will be discussed. [222] RELIABILITY IN THE IMPLANTABLE MEDICAL ARENA - Scott Hareland and Dennis Scranton, Medtronic - It is impossible to separate the reliability of a circuit from the application of the circuit. What is very reliable in one application may not work well at all in another. The implantable medical environment is an application which puts unique demands on electronic circuits and their manufacturing processes. For example, the ultra-low current application raises the significance of Iddq testing. The implantable environment requires a hermetic enclosure for the electronics which in turn establishes a unique atmosphere for the electronics. This internal atmosphere can have impacts on the performance of components like ceramic capacitors. Even supplier relationships and failure reporting take on unique aspects for implantable electronics. Implantable medical devices must also be designed for a wide variety of operating modes, including sensing signals in the microvolt range, all the way to delivering electrical therapies that operate with energy levels in excess of 30J. All of this is done with the same integrated electrical system which poses unique challenges for the design as well as the reliability of electrical components. These constraints drive, and the relatively low volume of medical electronics permit, design techniques that provide more latitude to increase reliability margin compared to general commercial electronic products. It is important to recognize the operating space and constraints in which implantable medical electronics operate in order to optimize the design and manufacture of medical grade electronic products.

[231] DIELECTRIC CHARGING IN MEMS. A REVIEW OF PRESENT KNOWLEDGE ON ASSESSMENT METHODS AND MATERIALS - George Papaioannou, University of Athens - Dielectric charging constitutes a major problem that still inhibits the commercialization of RF MEMS capacitive switches. During last decade several methods have been applied to assess the charging process involving MEMS switches, MIM capacitors and simple dielectric films on metal or/and insulating substrates. The device temperature has been used extensively because accelerates the charging and discharging processes by providing energy to trapped charges and to dipoles to overcome potential barriers and randomize orientation and reduce the time of charge collection. Materials such as SiO2, Si3N4, AlN, Al2O3, Ta2O5 have been used due to deposition method maturity and high dielectric constant. These materials consist of covalent or ionic bonds, including one piezoelectric, that significantly affects the charging processes. The presence or absence of dielectric film as well as its expansion on the insulating substrate constitute a key issue parameter that influences the charging process. Finally several theoretical models have been proposed to describe the macroscopic effects of dielectric charging. Aim of the tutorial is to discuss these approaches showing the present available knowledge. [232] RELIABILITY CHALLENGES RELATED TO TSVINTEGRATION AND 3D-STACKING - Kristof Croes, IMEC 3D integration is a technology that allows for the vertical connection of basic electronic components. This technology allows better performance and smaller and cheaper systems, linking various designs and applications (logic, memory, analog, passives, sensors, etc.) together in 3D. This will however induce unknown reliability issues related to TSV-integration, impact of the TSV on the FEOL and BEOL performance and reliability, the wafer thinning process and the stacking of these thinned chips. In this course various reliability related challenges encountered in the 3D-stacked IC process which is under development in imec will be discussed. This includes problems related to: - TSV-reliability itself: stress and stability of the Cu in the TSV, stress induced in the silicon and TSV barrier/liner integrity, etc. - Possible impact on FEOL and BEOL performance and reliability. - Backside processing: thinning induced damage in the Si, effect of released copper nail, backside passivation, etc. - Bonding: Sn Cu micro-bumps reliability, IMC growth, Cu-Cu bonding issues, bonding induced stresses and damage, particles, co-planarity issues, etc. [241] ESD DESIGN CHALLENGES IN STATE-OF-THE-ART ANALOG TECHNOLOGIES - Gianluca Boselli, Texas Instruments Inc. - The relevance of Analog technologies has rapidly increased over recent years by virtue of the phenomenal success of portable consumer electronics (MP3 readers, smartphones, navigation devices…), which require a variety of analog functions integrated into the same device.

From an ESD standpoint, the large components portfolio typical of state-of-the-art Analog technologies poses significant development challenges. The focus of this seminar is the discussion of the technical challenges (high current behavior of analog components, applications requirements, design methodology,) encountered in the ESD design in state-of-the-art Analog technologies. Peculiar challenges of ESD design for Analog technologies as opposed to Digital technologies will be discussed as well. [242] ESD PROTECTION CONCEPTS AND METHODOLOGY FOR MODERN SOC DESIGNS - Harald Gossner, Infineon Technologies - Beyond the underlying base ESD elements the

overall ESD protection network of a modern system-on chip (SoC) design poses a significant challenge. This class of IC designs require the integration of digital logic, large SRAM or NVM memory blocks, high voltage circuitry, RF high frequency IOs and sensitive analog circuits on one piece of silicon - many of them working on different VDD levels, most of them belonging to separate power domains. The overall ESD network has to establish an efficient ESD protection path between any pin combination across all supply domains. At the same time the ESD circuits at the RF and high voltage IOs need to comply with high performance requirements of IOs exploiting the limits of technology. Advanced circuit solutions and their verification by a SoC compatible EDA verification flow will be presented. The tutorial will highlight the critical issue of CDM. In addition, the specific limitations and novel approaches of failure analysis to support troubleshooting of these designs will be discussed.