22 nm technology node active layer patterning for ...

22 nm technology node active layer patterning for planar transistor devices Ryoung-han Kima, Steven Holmesb, Scott Halleb, Vito Daic, Jason Meiringd, Aasutosh Davee, Matthew E. Colburnb, Harry J. Levinsonc, a Advanced Micro Devices, Inc., 255 Fuller rd., Albany, NY 12203, USA b IBM Research, 255 Fuller rd., Albany, NY 12203, USA c Advanced Micro Devices, Inc., One AMD Place, Sunnyvale, CA 94088, USA d IBM SRDC, 2070 Route 52, Hopewell Junction, NY 12533, USA e Mentor Graphics Corp., 1001 Ridder Park Dr., San Jose, CA 95131

ABSTRACT As the semiconductor device size shrinks without concomitant increase of the numerical aperture (NA=1.35) or index of the immersion fluid from 32 nm technology node, 22 nm patterning technology presents challenges in resolution as well as process window. Therefore, aggressive Resolution Enhancement Technique (RET), Design for Manufacturability (DFM) and layer specific lithographic process development are strongly required. In order to achieve successful patterning, co-optimization of the design, RET and lithographic process becomes essential at the 22 nm technology node. In this paper, we demonstrate the patterning of the active layer for 22 nm planar transistor device and discuss achievements and challenges in 22 nm lithographic printing. Key issues identified include printing tight pitches and 2-D features simultaneously without sacrificing the cell size, while maintaining large process window. As the poly-gate pitch is tightened, the need for improved corner rounding performance is required inorder to ensure proper gate length across the entire gate width. Utilizing water immersion at NA=1.2 and 1.35, we will demonstrate patterning of the active layer in a 22 nm technology node SRAM of a bit-cell having a size of 0.1 μm2 and smaller while providing large process window for other features across the chip. It is shown that highly layer-specific and design-aware RET and lithographic process developments are critical for the success of 22 nm node technology. Keywords: 22 nm technology, RET, DFM, SRAM, corner rounding

1. INTRODUCTION The resolution of an optical imaging system is governed by Rayleigh’s law P/2 = k1 × λ/NA, where P is the minimum printable pitch, λ is the wavelength of the light, NA is the numerical aperture of the system, and k1 is the process factor. Historically, the semiconductor industry has been scaling down the minimum printable pitch by reducing λ/NA. The current state-of-art technology uses a water immersion (NA = 1.35) and λ = 193 nm. In the absence of a higher NA immersion system or EUV technology, 22 nm node technology will push the resolution limit which will necessitate optimized illumination and design. Therefore, it is necessary to develop a better resolution enhancement technology (RET), a better image forecast ability (i.e. heavy use of computational technology), and a tight control of the process technology are critical in developing 22 nm node technology. In addition, strong support from the design for manufacturability (DFM) is required for successful 22 nm node development. In this paper, we report our 22 nm technology lithography work for the active area mask layer in the IBMAMD-Toshiba-NECEL-STMicroelectronics Research alliance. Lithographic results and challenges for the 22 nm node logic devices will be discussed for logic cells and a 6-transistor planar-device SRAM cell. The device demonstration for this SRAM cell was reported earlier [1].

Optical Microlithography XXII, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 7274, 72742X · © 2009 SPIE · CCC code: 0277-786X/09/$18 · doi: 10.1117/12.814277

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2. DFM and RET Severe design restrictions were implemented for the 22 nm device due to the low k1 factor (k1 = 0.28) at the tightest pitch. Even so, a small lithographic process window has been observed for the active area application and it is approaching the practical limit for single exposure processes. It is important to integrate design and RET optimization by defining critical features in advance and characterizing lithographic process window for these features. Fig. 1 shows sample layout for active and poly-gate in representative SRAM and logic cell designs.

Fig. 1. Active layer (vertical) and poly gate (horizontal) of sample SRAM (left) and logic (right) designs

In general, cell area scaling is determined by both the poly gate pitch in the vertical Y-direction as shown in Fig. 1, and also by the contact pitch in the X-direction. The contact pitch is often the key limitation for lithographic resolution, due to the range of pattern types which must be simultaneously printed, and therefore often becomes the cellsize limiter in general. For example, one challenge for active area (AA) lithography lies in 2-D printing such as the corner rounding (marked (1)) at the jog shown in Fig. 1. In addition, the AA lithographic process must provide large process window for the other features in the layout, such as isolation (marked (3)), tightest pitch (marked (2)), and also peripheral structures. Since the exposure tool NA did not increase as we migrated from the 32 nm node to the 22 nm node, the 2-D corner rounding is larger for the 22 nm node. Due to the smaller poly-gate pitch at 22 nm node, the polygate may be positioned on top of the active-layer corner. The larger corner rounding combined with the overlay driven poly-gate width variation may give rise to an issue of device stability. As a result, we have utilized high-fidelity predictive OPC modeling as part of our optimization of RET for the AA 2-D structures. Illumination source optimization is a well known technique for optimizing source shape [2], and source mask optimization (SMO) [3, 4] is a more advanced tool for concurrent optimization of the source and mask which allows operation at lower k1 values. As reported earlier, our initial goal was to demonstrate 0.1 um2 cell size SRAM. For the active layer of that design, a single exposure with NA=1.2 was used to minimize the cost of ownership. With an NA=1.35 system, the cell size can be further reduced, although depth-of-focus (DOF) is diminished. Within the restrictions in the design and illumination system, a strong off-axis illumination is unavoidable and an illumination source optimization technique is used to choose an optimum conventional or parameterized source type. Fig. 2 shows an example of an optimized source for iso-trenches and single SRAM cell.

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Fig. 2. Source optimization for; (a) Horizontal iso-trench, (b) Horizontal-vertical iso-trenches and (c) a single SRAM

However, It is necessary to optimize the lithographic process window across all feature types in the layout of the chip, and RET shapes need to be chosen with consideration all of the critical features. One key issue in the source optimization is weighting among features. We observed that the weighting can alter the optimized source shape dramatically and it is necessary to adjust the design philosophy for the chip in order to allow a balanced process window for all feature types. A detailed study in illumination optimization process and weighting, it is published elsewhere [5]. Using one of the generally available source types, a process window could be generated for the entire active layer. Fig. 3 shows a process window band (PVAND) simulated for the SRAM array portion of the active layer of 0.1 µm2 SRAM.

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Fig. 3. Process window simulation (PVAND)

However, in choosing the source from the generally available source library, only a few illumination types are found to be useful, and these utilize a strong off-axis feature. Only dipole-like illuminators with a large blade angle or 45o rotated quadrupole illumination can be used to achieve both high resolution in the SRAM array and at the same time be able to reduce the corner rounding.

3. LITHOGRPAHIC PROCESS CONTROL Lithographic process optimization is also important because the aerial image quality is low for some of the feature types. Highly layer-specific lithographic process development is often critical for the success of 22 nm technology node. For example, the choice of resist depends on a balanced capability to print all of the features in the design, including line/space patterns at small pitch, corner-rounding performance, isolated space resolution, and sensitivity to ringing effects in the aerial image. In addition, usually the resist processes such as the post-exposure bake

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temperature, or develop time, may also significantly affect the over-all process window. We observed, as shown in Fig. 4, that the optimization of the develop time and optical polarization can improve resist pattern fidelity dramatically.

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Fig. 4. Top-down SEM images of process optimizations; (a) Initial resist pattern prior to process optimization, showing partial line collapse and LER (b) develop time adjustment, (c) polarization tuning and (d) post-RIE

As mentioned earlier, the resist must be capable of simultaneously printing isolated spaces, small-pitch arrays, and at the same time achieving small corner rounding values in 2-D features. Figure 5 shows some examples of the variation of lithographic fidelity as a function of resist type.

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(b) Fig. 5. Resist screening flow; (a) SRAM printability for four different resists A ~ D (left to right) and (b) Isolated-trench behavior for the two optimum resists selected in (a)

All four resist candidates showed a large process window (> 150 nm DoF @ 5% EL) for the OPC anchor (smallest pitch) structure. However, they showed different behaviors to various design features, such as the 2D SRAM array and the isolated space. Resist chemistry and track process optimization can play a key role in achieving a balanced

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process for all the feature types at 22 nm node applications. In this case, the resist we selected showed an overlap depthof-focus > 100 nm at 5 % exposure latitude for critical designs. Fig. 6 shows DoF vs. EL for isotrench, SRAM’s pull-up gate, and anchor feature.

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Fig. 6. Exposure latitude vs. depth of focus for three separate feature types.

Figure 7 shows a comparison of the dimensions of the resist pattern and the simulated aerial image for the SRAM array. The close agreement between the aerial image and the resist pattern can be used as a measure of the efficacy of the OPC model generated for this application.

Fig. 7. Pattern fidelity comparison for resist pattern and aerial image generated with use of OPC model.

In addition to the resist selection, it is also important to consider reflectivity and image transfer control for hyper-NA 22 nm node applications. In our embodiment, we use a tri-layer lithography stack, which incorporates a thicker organic underlayer, optimized for reflectivity control and etch resistance, with a silicon containing antireflectivity layer (SiARC) coated underneath the resist. In this approach, we have two ARC layers for the optimization of reflectivity issues, and also can utilize the thin SiARC material as a hard mask for amplifying the thin resist layer during the RIE image transfer into the substrate.

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4. CONCLUSION Due to the unprecedented lack of availability of higher NA exposure systems to support the scaling from 32 nm node to 22 nm node devices, it has become critically important to integrate the chip design, OPC, RET and resist process optimization. Our work has shown that 0.1 um2 SRAM cell can be successfully developed with a large process window for all the required feature types. Corner-rounding on 2-D features, dense arrays, and isolated spaces were successfully patterned after proper optimization of the resist, process, OPC and RET. The resulting process has been used to successfully fabricate high-density SRAM and logic devices.

ACKNOWLEDGEMENT This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

REFERENCES 1. 2. 3. 4. 5.

B. S. Haran et al, “22 nm Technology Compatible Fully Functional 0.1 μm2 6T-SRAM Cell,” dipole illumination”, Proc. IEDM, 27-1, 2008. Chang-Moon Lim, Seo-Min Kim, Tae-Seung Eom, Seung-Chan Moon, and Ki-Soo Shin, “Diffraction Analysis of Customized Illumination Technique”, Proc. SPIE, 5377, pp. 1297-1304 (2004). A. Rosenbluth et al, “Optimum mask and source patterns to print a given shape”, Proc. SPIE, 4346, pp.486, 2001. R. Socha et al, “Simultaneous source mask optimization (SMO)”, Proc. SPIE, 5853, pp.180, 2005. Aasutosh Dave and Ryoung-han Kim, “Pushing the limits of RET with different illumination methods”, Proc. SPIE, 7274, 7274129, 2009.

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