Process Control for 45 nm CMOS logic gate patterning

Process Control for 45 nm CMOS logic gate patterning. Bertrand Le Gratiet * a, Pascal Gouraud a, Enrique Aparicioa , Laurene Babauda, Karen Dabertranda, Mathieu Toucheta, Stephanie Kremerd, Catherine Chatonc, Franck Foussadiera, Frank Sundermanna Jean Massina, Jean-Damien Chapona, Maxime Gatefaita, Blandine Minghettia, Jean de-Caunesa, Daniel Boutina a

STMicroelectronics, 850 rue Jean Monnet, F 38926 Crolles Cedex, France c CEA-Leti, 17 Rue des Martyrs, 38054 Grenoble Cedex 9, France d KLA-Tencor, 32 Chemin du Vieux Chêne, 38920 Meylan, France ABSTRACT

This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer, intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay performance with immersion lithography is also presented. Keywords: 45nm logic gate, immersion lithography, scatterometry, CD uniformity.

1. INTRODUCTION CMOS 45nm is the first technology using immersion lithography. In the early phase of immersion process development, process was quite limited by overlay performances of the tool and also by photo resist imaging. In these conditions it has been decided to pattern the gate using “double patterning” scheme for the SRAM blocks. With such approach, end cap (line end) in the SRAM (which is pattern with a specific lithography step) is not correlated to CD and overlay control of the gate and is therefore no more a bottleneck factor for gate process development. A 45nm gate is really challenging by its CD range control in all aspects. After the setup of the double patterning integration scheme, most of our activity was focused on CD budget breakdown with special attention to immersion cell process performance. However, in this paper most of the CD analysis data will be shown after the complete patterning of the gate. Breaking down our CD budget quickly lead us into the need of extensive metrology and as such, to the need of extensive development of scatterometry. All along this paper we present the current CD control performance of CMOS 45nm gate patterning using immersion lithography and outline the coming actions we think are needed to breakthrough the 3 sigma challenge. Overlay is also reported in a less extensive manner.

2. GATE PROCESS INTEGRATION Our 45nm gate patterning integration scheme is based on our 65nm gate patterning scheme using amorphous carbon / Dielectric ARC stack as antireflective and Hardmask [1]. However, if for the logic (like in our CMOS 65nm), the pattern is defined in a single exposure, the end cap control in the SRAM in CMOS 45nm is using a second photo/Etch “assist” step to perform the line cut. This has led us to introduce an intermediate Hardmask. Also due to the hyper NA imaging we had to adapt our DARC which is now a double oxide layer with properly tuned n,k [2]. With such anti reflective layers we are able to control the resist swing effect within 1nm. On figure1 we see typical swing curves registered for immersion process, showing important bulk effect but rather low swing amplitude at working setpoint.

Metrology, Inspection, and Process Control for Microlithography XXII, edited by John A. Allgair, Christopher J. Raymond Proc. of SPIE Vol. 6922, 69220Z, (2008) · 0277-786X/08/$18 · doi: 10.1117/12.776889

Proc. of SPIE Vol. 6922 69220Z-1 2008 SPIE Digital Library -- Subscriber Archive Copy

68 67

Normalized CD (nm)

66 65 64 63

Isolated Line Pitch 180nm Pitch 140nm SRAM 0.299µ²

62 61

170

160

150

140

130

120

110

100

60

resist Thickness (nm)

Fig1: Normalized swing curves (experimental + fit) observed for four critical CMOS 45nm patterns using immersion lithography.

Another important point in this integration scheme (double photo / double etch described on figure2) is the second photo steps which does not play any role in CD (L poly) control. The resist line defined after the first photo steps are trimmed down during the intermediate Hardmask Etch. The final etch poly steps brings down the pattern to the desired target. Exposure Dose Feedforward (static) Feedback loop (dynamic)

Trim Rate Feedforward (static)

t

I

¶I

Organic HM (α-C) TEOS HM

Poly

II LII1 ETCH1: TEOS etch (+ clean)

PHOTO1: GATE line photo

SIfli 1StF1J U U UU U

BARC

]

PHOTO2: SRAM cut

j2 ETCH2: HardMask Cut etch & POLY Etch (+clean)

Fig2: double patterning integration scheme chosen for CMOS 45nm logic Gate patterning. Both photo steps are immersion lithography steps.

3. CD CONTROL PERFORMANCE EVALUATION 3.1. Average CD regulation From the 2 photos and 2 etch steps, CD is dynamically controlled at Photo1 and Etch1 like shown on figure 2 1: A multivariate Run to Run system is used to control Photo CD centering [3]. This system includes feedforward (Reticle maskshop CD bias & error datas / Scanner Spot sensor / Product target) and feedback effects (Scanner / Layer / Mask effects) which are dynamically controlled. Using such system, average lot CD can be controlled without rework within ± 2nm.

Proc. of SPIE Vol. 6922 69220Z-2

2: Etch1 process is based on resist trim which is adjusted by a feedforward loop, compensating any average CD miscentering (within ± 2nm) at Photo1. 3: The second photo step doesn’t impact Gate CD and the final etch process is running at fixed bias. Feedforward / feedback loop quality is strongly relying on metrology residual noise level which can be reduced by higher sampling or improved metrology methods. At the start of CMOS 45nm development, CD’s were measured using CDSEMs. Residual noise was not good enough and the throughput not acceptable to increase the sampling plan. Today for CD regulation, scatterometry has been deployed allowing us to sample 8 wafers per lot with 17points per wafer. 3.2. CD metrology Setup Due to the stack used at Photo1, the development of the libraries was not straightforward. Some publications are available regarding the development of scatterometry libraries on APF stack for our CMOS 65nm process [4]. Several DOE’s were ran to set up scatterometry library which demonstrates stable behavior with respect to polysilicon / TEOS hardmask / amorphous carbon and oxides DARC thickness variations and also with respect to n,k from the DARC stack. The CD measurements were calibrated with SEM (after photolithography) and SEM&TEM (after etch) on exposure matrix wafers. Before switching to scatterometry as primary measurement for process control, double data collection has been performed during about 8 weeks of production. Figure 3 shows the CD correlation results between top down CDSEM measurements after photo1 and etch2 and also with TEM cross section after etch2.

60

75

55 CDSEM (nm)

70 65 y = 1.0414x + 1.5165 R2 = 0.9978

50 45 y = 0.9273x + 5.1083 R2 = 0.9953

40 35

55

60

55

50

45

40

80

75

70

65

60

55

50

Scatterometry (nm)

35

30

50

30

CDSEM (nm)

80

60

V

CD after Polysilicon Etch

CD after Photolithography

Scatterometry (nm)

Fig3: Scatterometry / CDSEM / TEM CD correlations observed after scatterometry library setup for CMOS 45nm Gate patterning

For photolithography the first running version of the library (with which we have done most of the CD budget work) was using 5 levels of freedom. In order to continuously improve the CD measurement, a second libray with 7 levels of freedom is being developed which shows better response in term of stack variations.

3.3. CD budget breakdown As a start for CMOS 45nm process developpement, a target level of 4.5nm (3σ) CD dispersion after Etch has been set (for transistors). This budget includes (i) Lot to Lot (ii) Wafer to Wafer (iii) Within Wafer (iv) Intrafield (v) Proximity effects. Our goal is to use scatterometry for the first four items while proximity effect would be integrated in the OPC model which is characterized by CDSEM. In parallel, some works are on going to evaluate real impact of line width roughness (LWR) on device performance and this is why it is not reported in the budget. The current evaluation and progression of this CD breakdown (after etch) is described on figure 4, details regarding these values are reported later in this paper.

Proc. of SPIE Vol. 6922 69220Z-3

Contributors

Measurement

Q307

Q407

Today

In Line Lot to Lot

Line 40nm Space 140nm (OCD)

2.21

2.04

1.51

Wafer to Wafer

Line 40nm Space 140nm (OCD)

1.58

0.95

0.66

Field to Field

Line 40nm Space 140nm (OCD)

1.67

1.38

1.4

Residual

Line 40nm Space 140nm (OCD)

1.2

1.2

1.2

3.41

2.90

2.47

sub total In line

IntraField Scanner

Line 40nm Space 140nm (OCD)

Mask (xMEEF)

Maskshop data (Melody)

sub total

1.4

1.4

1.4

1.67

1.67

1.67

2.18

2.18

2.18

2.3

2.3

2.3

OPC Proximity (Range)

Line 40nm vs Pitch (SEM)

Total Total (excluding Proximity)

Line 40nm Space 140nm

4.04

3.63

3.30

Total (including Proximity)

CD 40nm all Pitches >180nm

4.65

4.30

4.02

Fig4: CD budget breakdown (3σ values in nm)

3.3.1. Lot to Lot CD control As said earlier the CD lot to lot control relies on Photo Run to Run system and Photo – Etch feedforward loop. Once the scatterometry model has been generated and validated, CDSEM measurement has been replaced by optical CD measurement as lead metrology. Doing so, we could double our sampling scheme and still increase the measurement throughput. The most significant interest of scatterometry was a drastic reduction of the measurement residual noise enabling a better Run to Run regulation at photo and etch. As an example we can see on figure 5 the difference in term Min/Max CD range (in µm) per lot observed with scatterometry on the left side and CDSEM on the right side after photolithography. 0.003 10 weeks period

0.002

(1 point = 1 lot)

nm

0.001

0

v\j ,

r

-0.001

-0.002

Scatterometry

-0.003

J\v

CDSEM

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

Fig 5: Normalized Min/Max CD per lot observed over the same period with scatterometry (left side) and CDSEM (right side)

In line specs could then be set to ± 2 nm for CD average at photo, the remaining error being corrected by the feedforward loop between Photo1 and Etch1. CD dispersion after photolithography and after etch using scatterometry are represented on figure 6. Two periods are represented, one (left) during the implementation phase of the feedforward and the other (right) after stabilization of the process. CDmeantoTarget error distribution

CDmean to Target error distribution

(35lots/ 245wafersmeasured/ 4100measurement points)

(Last Month > 100 wafers sampled)

200

2.3 6.3 2.9

-150 -200

(nm)

.2

Mit

-1.6

MaX

1.4

0.0 -2.7 2.3

RatIo

2.9

6.1

31191110

1.5

2.4

4

Isiqitta

1.9

Meat

3

3.7

1

1.9

Ratttt

0

1

0

-1

-2

-3

-4

-500

Mao

(nm) Mn photo MH etch

-100

-1

-400

4

-300

3

-200

0 -50

-2

(nm) MH Photo Mn Etoh Mtatt 0.1 -0.9 Mitt -1.9 -4.0

50

-3

0

2

Frequency

100

F re q u e n c y

100

200

-100

Photo Etch Poly

150

PHOTO ETCHPOLY

300

-4

400

2

500

(nm)

Fig.6: Observed in line CD dispersion (after Photo1 and Etch2) over (left) 2 month period in Q4/07 and (right) over last month Q1/08

Proc. of SPIE Vol. 6922 69220Z-4

On this graph, photolithography process looks much more stable than etch process but this picture may be too optimistic for photolithography. If fact, we’ll see later that if etch process can have its own signature, some part of it is induced by photolithography focus control. 3.3.2. Wafer to Wafer process control Using scatterometry we could afford measuring up to 8 wafers within a lot. Whether we should measure all the wafers or not was indeed questioned. It means that we would correct process trim time, at wafer level. This option is possible and still open. In our development history and still today we regularly measure full lot, fullmap. We also decided to use the immersion cell with a maximum of process units (3 coaters, 7 PAB, 7 PEB plates, 4 developer module, dual chuck) in order to be able to run at a throughput above 120 wafers per hours and really evaluate the immersion cell in production mode. We still see some moderated process module effects. A typical intralot signature can be seen on figure 7a. Intra lot signature is not really significant and moreover looking back after etch, tuning trim time per wafer could even induce more noise. We should rather correct for a trend than for a single wafer information From photolithographic point of view, modules matching are controlled off-line on structures with aggressive pitches. With such criterias coater, PEB, developer module or chuck effects can be easily detected (see figure 7b). 250

50.5

62.50

47.50

62.00

47.00

61.50

46.50

61.00

46.00

60.50

45.50

100 50 0

52

48.00

11

52.5

63.00

Di40D

51

51

fl!UW

51.5

48.50

1.211111

50

63.50

2.111111

150

50.5

51.5

ETCH PHCTC

200

49

49.00

64.00

2.30

49.49 40.50 50.00

49.5

52

64.50

Wafer rr Wafer See

U!,jth, CD pflth

48

49.50

65.00

M! Mj!

48.5

50.00

52.5

47.5

Average of Value

(nm)

60.00

Step PHOTO ETCH

45.00 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Wafer Max

50 49.5

Wafer Mean

49

Wafer Min

48.5 48 47.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

NLD

Fig 7a: Intralot CD average trend (photo1 & Etch2)

Fig 7b: CD trend and dispersion from 25 photolithography monitor wafers

Basically after photo, beside module matching effects, we systematically see slight begin to end batch trends (< 0.5nm in amplitude), effect which is also visible on scanner monitoring. In this case we tend to think of lens heating effects. We are now in a position to see tiny CD signatures across wafers and or batches. The lens heating model, for example, is a parameter we know we can improve especially when using multi-pole illumination. From this side investigations are still one their way. In fact if we trace resist side wall angle, it shows same kind of trend as CD (figure 8). These are evidences that focus control and so, resist side wall angle, will also start to show up in CD dispersion evaluations. Average of Value

86.8

50.5

86.7

50

86.6

49.5

86.5

49

Resist SWA (°)

CD (nm)

51

86.4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Slot

Fig 8: CD and Resist Side Wall Angle trend within a batch of 25 photolithography monitor wafers from the immersion cell.

Proc. of SPIE Vol. 6922 69220Z-5

3.3.3. Intra Wafer process control Our in-line sampling checks 17 points per wafer. For process setups and also for variance analysis many lots were also measured fullmap / full lot after photolithography and etch, using scatterometry. In the early phase of process development we typically saw the intrawafer signatures shown as reference process on figure 9. This radial signature was, after etch, systematic on all the measured wafers. At that time we decided to tackle this issue from two angles. First one was from etch process side and the second one from photo lithography process side using intrawafer dose correction sub-recipes. Intrawafer dose correction using scanner exposure sub-recipes generated by the dose mapper® application was tested. The sub-recipe was generated from an intrawafer profil average from about 100 wafers mapping. We could remove the radial signature but in parallel etch process was improved and the center edge effect was removed [5]. Finally, intrawafer dose correction was set aside.

Photo (Dose Mapper@)

PHOTO1

PHOTO1

ETCH1

ETCH2

Scanner subrecipe

Previous Reference Process

+10°C

PHOTO1

ETCH1

ETCH2 T0

46

+2°C

45

CD (nm)

44

Etch (Chuck T° tuning)

43 42

T0

41

T0 + 2°C T0 + 10°C

40 39 0

35

50

60

70

80

90

100

110

120

Ref 130

Distance to the center (mm)

Fig 9: Intrawafer critical dimension profiles evolution along the gate patterning brick, using dose mapper@ subrecipes (on top) and etching chuck temperature tuning (at the bottom)

From these experiments we also realized that using exposure dose as the only knob to control CD could be dangerous. We start then to pursue our evaluation looking more carefully at the focus effect on CD budget. Wafers with Focus Exposure Matrix and fixed focus shift were exposed and extensively measured by scatterometry inter and intrafield. Basically 74 fields per wafers with 22 measurements per fields (say 1628 points per wafer up to 3mm from wafer edge) were done. Radial presentation of typical CD profiles and uniformity are represented on Figure 10. 43

Average of CD

63 62

41

61

40

60 Focus -0.12 59 -0.06 58 0 57 0.06 0.12 56

(nm)

39 38 37 36 35

After final Etch

34

After Photolithography

54 53

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145

33

55

Focus -0.12 -0.06 0 0.06 0.12

5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 140 145

(nm)

Average of CD

42

(mm)

(mm)

Radius

Radius

Figure 10: Radial representation of typical intrawafer CD profiles for different focus exposure shifts after Etch2 and Photo1.

Proc. of SPIE Vol. 6922 69220Z-6

-18

5

-19

4

3σ CD variation (in nm)

Etch - photo Bias in nm

We observe that tiny CD variations after photo are amplified after etch (especially at wafer edge) and also that focus shift induces large etch CD variations strongly impacting etch Bias (see Figure 11a). So to estimate intrawafer CD uniformity performance from photolithographic process, we should consider that a part of the variation seen after etch is coming from lithography. On the graph (Fig ure 11b), CD variations after photo are within 1 to 1.5 nm 3σ, while they reach 3nm 3σ after etch. Most probably, a non negligeabme part of the difference could be directly attributed to focus or resist sidewall angle variations.

-20 -21 Etch Bias (from fullmap wafers)

-22 -23 -0.2

After Final Etch

2

1

Etch Bias (from FEM wafer)

-0.1

After Photo1

3

0

0.1

0 -0.15

0.2

-0.1

Defocus in µm

-0.05

0

0.05

0.1

0.15

Defocus in µm

Fig 11: (a) Evolution of etch bias with respect to defocusing

(b): 3 sigma intrawafer CD variations after Photo1 and Etch2.

3.3.4. Intra Field process control Intrafield CD control is less easy to do in-line. Our strategy (outside scanner monitoring itself) has several aspects. 1.

2.

3.

First, we need to insure that reticle will be delivered with an acceptable CD range. Since many years, work is done with the maskshop to improve mask CD uniformity and also to improve mask CD error feedback. The ultimate idea is to correct the mask CD error map (so 2D correction) in the feedforward system. The second aspect is more linked to in-line control of intrafield CD. This will rely on in-field dropped scatterometry targets from which positions and CD mask errors will be known. In the first phase engineering recipes are created to measure these in field targets, giving us feedback. Depending on the mask, we can have tens of scatterometry targets dropped in the field. Since focus will play an important role, we also introduced focus Reticle Shape Correction@ (RSC) which is an option on the scanner. It allows focus compensation of distorsions from the reticle on the reticle stage (reticle glass plate distorsion and clamping).

Mask CD error dispersions is quite stable like seen on Figure 12.

60

(nm) Mean to target 3Sigma

Product1 Product2 Product3 0.17 1.61

-0.59 1.62

-0.27 1.72

50

Frequency

40 Product1 Product2 Product3

30

20

10

-3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3 -3 -2 -1 0 1 2 3

0

CD error in nm (at wafer level x MEEF)

Fig. 12: Distribution of the average mean to target errors (at wafer level including MEEF) measured at maskshop on incoming reticles

Proc. of SPIE Vol. 6922 69220Z-7

We have investigated the use of Dose Mapper@ for intrafield mask bias correction. This work is on going for its implementation as a regular procedure for incoming reticles. The concept is to get the mask CD error map and generate a corresponding intrafield dose correction recipe. To validate the concept, experiments have been done with different level of feedforward corrections (figure 13). To insure proper statistic, two fullmaps wafers (like in chapter 3.3.3) have been measured for each conditions. Results are encouraging but still require deeper characterization. 2.50

Intrafield 3sigma (nm) 2.00

1.50

1.00

0.50

0.00 Ref

Dose Mapper 100% Dose Mapper 200% correction correction

Fig. 13: Intrafield CD distribution using Dose Mapper@ subrecipes generated from mask CD error map.

Intrafield 3s (nm)

As we already said, dose is probably not the only knob to use and intrafield is certainly not only mask CD / Scanner dose uniformity composite. We also investigated focus effect at intrafield level. The best way to put in evidence the intrafield focus effect is to compare results with and without Reticle Shape Correction. For this, two time two wafers were exposed with focus matrixes, with and without Reticle Shape Correction. They are measured the same way as reported on the previous chapter. When looking at intrafield CD dispersion (from this given pattern) it is clear that compensating from reticle focus distorsion on the reticle table significantly opens up the process window. It does not really improves intrafield CD uniformity at best focus, but it stabilizes it across process window (figure 14). 10 9 8 7 6 5 4 3 2 1 0

RSC OFF RSC ON

-0.2

-0.1

0 Focus (µm)

0.1

0.2

Fig 14: Intrafield CD 3 sigma dispersion measured after photolithography on focus matrix wafers with and without Reticle Shape Correction

Like reported for intrawafer effects, de-focusing will introduce CD deviations after etch. Within the focus window where photo CD uniformity stays within 1nm, we see that after etch this will be increased by 50 to 100% (figure 15 a&b)

After Final Etch

4

3

2

1

0 -0.2

5

After Photo1

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

3σ intrafield CD variation (in nm)

3σ intrafield CD variation (in nm)

5

After Photo1 After Final Etch

4

3

2

1

0 -0.2

-0.15

-0.1

-0.05

0

0.05

0.1

0.15

0.2

Defocus in µm

Defocus in µm

Fig15: (a) Intrafield CD uniformity From FEM wafer at best dose (b) From Fullmap wafers at best dose with focus shifts

Proc. of SPIE Vol. 6922 69220Z-8

3.3.5. Proximity effects – OPC From the beginning a lot of attention has been paid to the OPC. 1. 2. 3. 4.

First the model used is a process window aware model taking into account focus and dose variability. Second, etch contribution is being used to optimize the model. Therefore we always look and report data after etch. Third, using process aware model we could get a safer positioning of process set point with respect to OPChotspots, and also more stable CD versus pitch trend across process window. Fourth, due to the double patterning scheme we could afford less restrictive rules on scatterbar size.

Amongst all the checks that can be done for the OPC model, CD versus pitch behavior and hotspot window centering are the one we more carefully look at. In the last model, CD range across pitches was checked within process window after etch. On the two graphs (figure16) CD versus pitch data after etch are presented across dose and focus. I—lilt — I! *IJ —

—-N

-

—.tO',—. T ir .I:w_awI

I! ,TJ—l7Alli

-/ -, C-'-Ci —Ts-- . -..

.. -----

,: t --J

\±

!

.

./-

-.

.

Fig 16: CD versus Pitch after etch observed across dose and focus (focus steps = 50nm).

It is observed that CD range remains within 2 to 2.5nm across the process window. It is also interesting to note that focus (within our DOF window) has more impact on global CD for all the pitches than on iso-dense bias itself. Thanks to the process aware model we can be quite confident on the stability of this proximity effect within dose and focus window. However, these data also reveal once again, how large etch CD shift can be when photo focus is shifting by even 50nm. 3.3.6. CD budget evaluation conclusion Hunting sources of CD variances is a neverending story. Overall, the immersion cell shows a good level of performances. During this evaluation, we could show that focus is probably now one of the main CD variance contributor. Focus effect needs to be investigated with etch bias. We are now deploying a new scatterometry library from which resist sidewall angle information can be used by the photo etch feedforward loop.

4. IMMERSION CELL OVERLAY PERFORMANCE EVALUATION 4.1.1. Overlay and wafer timing Immersion overlay is facing new challenges. One of them is related to the track / scanner timing. We saw regularly wafers presenting translation shifts and/or instability in intrafield. It was quickly related to variations of delay time between two wafers and therefore throughput matching between track and scanner (figure 17a and 17b)

Proc. of SPIE Vol. 6922 69220Z-9

a Misalignment X (nm)

M

Fig 17: (a) Typical within lot overlay translation behavior observed

(b) Corresponding exposure delay timing.

The first action was then to insure that scanner is always bottleneck. We can also remark that intrawafer overlay uniformity was also not optimum. Since then, many improvements have been done leading to seriously improved overlay performance. In order to properly monitor overlay up to 7 wafers are measured on critical layers and systematic full lot measurement is done for the CONTACT to GATE. 4.1.2. Overlay performances On the following charts (figure 18a & b) are reported typical registration error distributions (2 month period) for Gate & Contact overlay. Knowing that we still have improvement actions to be deployed to tighten overlay control, we can say that the immersion cell performance is complient with 45nm process requirements

x _Y_ UI

UI • -11.1

Mean

Miii Max

•

Illillii

1000

(nm)

Mean

• -14.0

Miii Max

12.6 • 13.2 1 Q!Q •

• 10.6

• -14.3 •

8Illillii

4000

800

_X_ _.Y_ 00 -03

• -16.4

13.8 1 Q!4

3000

600

2000 1000

200 X Y

0 -200

Frequency

Frequency

400

X Y

0 -1000

-400

-2000 -600

-3000

-800 -1000

-4000 -15

-10

-5

0

5

10

15

-15

-10

Registration error (nm)

-5

0

5

10

15

Registration error (nm)

(a)

(b)

Fig 18: 8 weeks overlay distribution (a) GATE to ACTI (7 wafers / lot) (b) CONT to GATE (25 wafers / lot)

5. CONCLUSION Along this paper we have shown that keeping CD uniformity within range require a lot of attention on many contributors. The immersion process really shows good performances. If exposure dose, process temperature, etch trim conditions are well controlled, it is clear that focus effect is taking a significant part of the budget and at all levels, lot to lot, wafer to wafer, within wafer and field and also for proximity. Looking back at these CD uniformity results along with overlay data, we can say that immersion is ready for production. There are still a lot of improvement actions in the pipe (i) Scanner hardware-software (ii) track hardware (iii) new resist materials (iv) mask process improvement (v) new options in feedforward / feedback loop system etc… The next challenge of this work will be a development of focus feedforward / feedback loop methodology. Today a lot of attention is paid to focus budget because it is not easy the measure directly and even less easy to control in line.

Proc. of SPIE Vol. 6922 69220Z-10

6. ACKNOWLEDGMENT Many people have been involved in this works. Immersion process development in Crolles started end 2005 and is now really coming to maturity. This paper couldn’t exist without the support of our night and weekend R&D Enginneers, Marianne Decaux, Nicolas Thivolle, Romain Brouillac, Fabrice Baron, Yoann Blancquaert.

7. BIBLIOGRAPHY [1]: J.-D. Chapon ; C. Chaton , P. Gouraud ; M. Broekaart ; S. Warrick ; I. Guilmeau ; Y. Trouiller ; J. Belledent – “Comparision between organic Spin-on BARC and Carbon containing CVD stack for 65nm gate patterning” Proceeding SPIE – Volume 5753 – Advances in Resist Technology and Processing XXII, May 2005, pp. 708-719 [2] : V. Farys ; S.Warrick ; C. Chaton; J. Chapon – “ARC Stack Development for Hyper NA Imaging” – Proceeding SPIE – Volume 6520 – March 2007 [3] J. de-Caunes, J.Van-Herk, S Warrick B. Le Gratiet, M. Mikolajczak, J.-D. Chapon: “Design and use of multivariate approach error analysis APC system”, Proceeding SPIE – Volume 6155 – Feb 2006 [4] : K. Dabertrand; M. Touchet; S. Kremer; C. Chaton; M. Gatefait; E. Aparicio; M. Polli; JC Royer – “Industrial chracterisation of scatterometry for advanced APC of 65nm CMOS logic gate patterning” – to be published SPIE 2008 [6922-30] [5] : L.Babaud ; P. Gouraud; E. Aparicio; E. Pargon; O. Joubert; B. Le Gratiet – “Investigation of 45nm Silicon Gate Etching Process Variability contributor” - PS2-TuM9 - AVS SEATTLE 2007

Proc. of SPIE Vol. 6922 69220Z-11