32 nm logic patterning options with immersion ...

32 NM LOGIC PATTERNING OPTIONS WITH IMMERSION LITHOGRAPHY K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock^, Z. Baum, M. Burkhardt, V. Dai^, D. Dunn, E. Geiss^, H. Haffner#, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery^, Y. Zou^, C. Sarma#, L. Tsou, W. Yan, H. Zhuang#, D. Gil, D. Medeiros Contact via: [email protected] IBM Computational Scaling & Advanced Lithography Research, Hopewell Junction, NY ^Advanced Micro Devices, Inc, One AMD Place, P.O. Box 3453, Sunnyvale, CA # Infineon Technologies NA Corp, Hopewell Junction, NY Keywords: Immersion Lithography, double patterning, 193nm lithography, logic patterning, Double Dipole Lithography, Printing Assist Features, pattern splitting, pitch splitting

ABSTRACT The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

INTRODUCTION The introduction of water-based immersion lithography enabled the 45nm node to achieve a full shrink from the 65nm node by enabling robust 2D imaging and enhancing process window. As we migrate from the 45nm node to the 32nm node, lithographers are faced with the challenge of continued scaling without the availability of a comparable improvement in NA. This situation will be exacerbated at 22nm with the lack of a mature EUV or a high index (NA>1.35) lithography solution. Consequently, the industry is aggressively pursuing double pattering solutions for the 32nm node. While flash memory applications are largely driven by one-dimensional considerations, logic applications are primarily driven by two-dimensional concerns. Due to various topology and ground rules for different levels, there is no “one DPT fits all” technology. We are targeting cost-effective DPTs that provide the necessary resolution and process window to support each critical levels. Most results shown here

Optical Microlithography XXI, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 6924, 69243C, (2008) · 0277-786X/08/$18 · doi: 10.1117/12.784107

Proc. of SPIE Vol. 6924 69243C-1 2008 SPIE Digital Library -- Subscriber Archive Copy

have been demonstrated on a 1.2 NA scanner. Early 1.35 NA results are also presented, which indicate extendability of these techniques to 22nm processes. In the following sections, we describe each DPT approach in detail, including RET (resolution enhancement technique) and process considerations.

DOUBLE PATTERNING TECHNIQUES A. Splitting Patterns by Grouping In the first 32nm active layer, the memory is nominally unidirectional while the random logic has multiple orientation and a greater variety of pitches and structures. Consequently, the illumination for the memory can be highly tailored for resolution and process window with one set of conditions that are unique and distinct from the random logic. The SRAM tends to drive pitch and density and consequently lends itself to aggressive polarized dipole illumination to which random logic is not amenable. However, the random logic region can be printed with sufficient process window with less aggressive illuminators such as quadrupole or quasar to allow for bi-directional designs. At 1.2 NA quasar illumination, the logic circuit with structures having pitch greater than 140nm are printed with sufficient depth of focus and exposure latitude. For structures with pitch in 100-104nm range, dipole illumination is required to achieve fidelity and process window at 1.2NA. Figure 1 shows the decomposition of a full chip into a series of regions with unidirectional tight pitch structure and bidirectional looser pitch structures. Each layout has independently optimized illumination conditions. Each region is then printed separately into the same resist film in a multiple exposure process. The result is a single developed pattern that could not be printed with a single illumination-mask combination. Figure 2 shows top down and x-section views of critical pitch grating structures for each region. The individually optimized illuminations used in this work are listed in Table 1.

Unpolarized

SRAM