Efficient implementation of a fractal color image compression on FPGA Thai Nam Son Television Graphic Center, Vietnam Nat. Television Hanoi, Vietnam e-mail:
[email protected]
Tran V Long, Hoang Manh Thang, Nguyen Tien Dzung Hanoi University of Science of Technology Hanoi, Vietnam e-mail:
[email protected];
[email protected] possibility of successfully coding and decoding without memory overflow using 64× 64 grey scale images at the clock rate of 100MHz. The test attained trade-off results is PSNR of 26.3 dB with compression ratio of 4.71and the encoding time of 11sec. In this paper, we purpose to optimize the PSNR and compession ratio by transforming the RGB components to YCbCr components. The FIC implementation for color images on Xilinx Virtex 5 (XUPV5-LX110T) FPGA board at the same clock rate of 100MHz is proposed. The experimental results showed that FIC algorithms can be realized in SoC for images and also applied to fractal video compression.
Abstract – Fractal Image Compression (FIC) method provides a color image compression solution with an extremely high compression ratio, however it requires relative large amount of operations to complete codification. In this paper, we have developed an efficient approach for a fractal image compression applied to a color image, which utilizes a fractal coding on RGB to YCrCb color transformation and suitable sampling modes, then implemented on FPGA board. The experimental results performed by Fisher’s method for a color image have verified the possibility to design a SoC for fast fractal coder/decoder of a color image.
The paper is organized in four sections. The introduction will be first presented. The summary of theory of Fractal Color Image Compression (FCIC) will be then described following the introduction. The next section presents the proposed FCIC implementation scheme on Xilinx FPGA board. Finally, the last section discusses about experimental results and performance evaluation followed by the conclusion of the paper.
Keywords- FIC, SoC, FPGA, Color Image Compression.
I.
INTRODUCTION
Fractal image compression (FIC) is based on partitioned iterated function system (PIFS) which uses the self-similarity feature of image to compress images [1]. In fractal image compression, an image is partitioned into a set of nonoverlapping blocks called ranges. Another set of larger blocks called domains is used to identyfy the best region in each range, which is most similar to it [2].
II. A.
Fractal Image Compression Algorithm In fractal image compression, an image is partitioned into a set R of n non-overlappig square range blocks. Another set D of 2 n × 2 n largersquare domain block is subsampled by pixel averaging to have the same size as the ranges.
In all, the fractal coding is always applied to grey level images. The most straight forward method to encode a color image by gray-level fractal image coding algorithm is to split the RGB color image into three Channels, red, green and blue, and compress them separately by treating each color component as a single gray-scale image, the so called threecomponent Seperated Fractal Coding (SFC)[11].
For each Ri ∈ R , this compression method searches through all of D to find a Di ∈ D most looks like the range Ri . It also find the best contrast and brightness setting si and oi for the
In place of going for three independent planes, in this paper, a one plane image from the three planes of RGB color image have composed using trichromatic coefficients. This one plane image is then compressed by proposed modified Fractal coding on Spiral Architecture, which minimizes the the number of domain blocks from 343 to 10 using local search to optimize the encoding time[11].
transformation wi of the mapping from Di into Ri :
x ai bi wi y = ci d i z 0 0
Others way, the color data of seperatly three channels, red, green and blue (RGB components) are transformed to YUV components, to take the advantage of the existing spectral correlation to gain more compression. The test attained tradeoff results is PSNR of 33.3 dB with compression ration (CR) of 9.72 and encoding time of 128.06 sec [10].
(1)
where si controls the contrast and oi controls the brightness of the transformation, z is the gray level of a pixel at position ( x, y ) [1]. Therefore, for each Di ∈ D ,
In our previous work [9], we have implemented FIC on Xilinx Virtex 5 (XUPV5-LX110T) FPGA board to test the
978-1-4799-3400-3/13/$31.00 © 2013
THEORY OF FRACTAL COLOR IMAGE COMPRESSION
si and oi using least square
regression are calculated and the Di with the least rms
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Y ' 16 R' C = 128 + A × G ' b B' C r 128
(2)
0.504 0.0979 0.256 A = − 0.148 − 0.29 0.4392 0.4392 − 0.3677 − 0.071
(3)
difference is picked [1]. A set of all wi called W , is the transformation of the encoding image. The image f that
satisfies f = W ( f ) is the fixed point of W . If W is contractive, f is unique and an approximation of the original image, therefore the decoding process is based on this property.
Since the size of R is very large, the number of comparison is very large, too. Hence, the way to partition image is very important in Fractal Image Compression to reduce this size but still keep the quality of decoding image. There are many ways to partition image to cover the image well. In this paper, we use quadtree partition. In a quadtree partition, a square larger than the minimum size in the image is broken up into four equal-sized sub-squares when its entropy is greater than the entropy threshold or there is no domain to satisfy the rms error tolerance [1]. After all ranges are covered, we do not store all the coefficients in (1). The contrast coefficient si and the
Sub Sample: Components Y , C b , C r is sampled by Module subsample according to the standard sample 4:4:4; 4:2:2, 4:2:0, 4:1:1. After that, This data is stored in buffer to complete fractal coding. Buffering: Buffer is used in order to store the components of image including: Y , Cb , C r . These components are utilized in fractal coding. SRAM on FPGA is use as buffer.
oi are quantized and stored in a fixed number of bits. In this paper, we use 4 bits to store si and 7 bits to store oi . Instead of storing the other coefficients, we store
brightness coefficients
the positions of Ri , both the positions and size of Di and the orientation involving the rotation and flip information [1]. The decoded image is created by iterating W from an initial image. For each Ri , Di unpacked from the compressed file, domain Di is sub-sampled by averaging each
(
)
Figure 2. The components of color image
non-overlapping 2 × 2 square sub-block. Then, each pixel value in subsampled domain is multiplied by si , added to oi ,
and placed in the location in the corresponding range Ri determined by the orientation. This process is repeated until the decoding image is fixed (i.e. the fixed point f is approximated). B. Fractal Color Image Compression Algorithm The process of using Fractal Coding compression algorithm implemented on FPGA colors are described as in Figure 1.
4:4:4
4:2:2
Preprocessing Image
Original Image
RGB2YCbCr
Subsample
Buffer
Fractal coding
Buffer
data
Figure 3. 4:4:4 Sampling Mode
Fractal Color Image Compression Figure 1. Fractal Color Image Compression Module
Preprocessing Image: Module RGB2YCbCr implements conversion of RGB color space into YCbCr color space according to the following equation:
Fractal Coding: This module performs a compression of each component ( Y , Cb , C r ) using Fractal algorithm. The coding normally use for Grey scale image. The component of image ( Y , C b , C r ) are considered as grey scale image, and implement compression each of this component.
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First of all, the component Y is encoded by fractal coding, then Cb and finally Cr is encoded. In decoding process, Order of process is similar to in encoder. III.
The GPIO is module connecting LCD-TFT to Micoblaze, it is utilized to display image before and after appling fractal algorithm.
IMPLEMENTATION OF FCIC ON XILINX FPGA
A. Features of Xilinx Virtex 5 (XUPV5-LX110T) The XUPV505-LX110T Xillinx FPGA board is a featurerich general purpose evaluation and development platform with on-board memory and industry standard connectivity interfaces. It features the Virtex-5 XC5VLX110T device. The XUPV5-LX110T is a unified platform for teaching and research in disciplines such as digital design, embedded systems, digital signal, image and video processing and communications etc. As depicted in Figure 1, the XUPV5LX110T Development System has the following features: -
Xilinx Virtex-5 XC5VLX110T FPGA
-
Two Xilinx XCF32P Platform Flash PROMs (32 Mbyte each) for storing large device configurations
-
Xilinx SystemACE Compact Flash configuration controller
-
64-bit wide 256Mbyte DDR2 small outline DIMM (SODIMM) module compatible with EDK supported IP and software drivers
-
On-board 32-bit ZBT synchronous SRAM and Intel P30 StrataFlash
-
10/100/1000 tri-speed Ethernet PHY supporting MII, GMII, RGMII, and SGMII interfaces
-
USB host and peripheral controllers
-
Programmable system clock generator
-
Stereo AC97 codec with line in, line out, headphone, microphone, and SPDIF digital audio jacks
-
RS-232 port, 16x2 character LCD, and many other I/O devices and ports
Figure 4. Model Fractal coding algorithm implemented on FPGA
C. FIC Implementation Process 1) Sorfware specification Table I lists software packages and their features, which are used for implementation of FIC on a Virtex 5 (XUPV5LX110T) FPGA board. 2) Implementation precedure Figure 5 describes the detailed steps to implement FIC on FPGA board.
B. Blockdiagram of FPGA implementation The module above consist of Microblaze processing connect to peripheral though bus PLB. Fractal coding algorithm is embeded into Microblaze. The Local Memory stores variables and coeffcients of fractal coding. The SRAM control is an interface between SRAM and Micoblaze processing, in order to control reading and writing data process. The SYSACE is an interface between memory card Compactflash and Micoblaze, it is use to read from and write to memory card. The RS232 control is an interface between PC and Micoblaze. It is utilized to monitor the fractal coding implement.
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Figure 5. FCIC implementation process
a) Stage 1: Creating the microblaze and the peripherals First of all, the microblaze and peripherals are created by utilizing the XPS tool to oprate at clock rate set to 100MHz. The microblaze is then configured to optimize the calculation and control of the system memory. After synthesis stage, the library for microblaze and the peripherals is generated as a .bit file for FPGA configuration and it is used finally for configuring the FPGA core and storing the specification parameters regarding to the peripherals for connection to microblaze. b) Stage 2: Creating software for the microblaze
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SDK tool is used to create software for the microblaze. SDK tool reads .c file and peripheral’s specification file and then compiles them to create .elf file. c) Stage 3: Observation of the results IMPACT tool which is integrated in SDK is used to download the .bit and .elf files to the FPGA board and the results may be observed by the terminal equipment connected to the system.
As illiustrated in Table III, the data have been performed for the set of parameters described as follow: entropy threshold ET = 6, rms error tolerance RET = 8, minimum rang size MiS = 4, maximum range size MaS = 16, number of iteration NI = 20. For the FPGA based implementation, the number of class (NC) is selected as 72 and 24 for Y compnent and Cb, Cr respectively. TABLE III. FCIC’S RESULTS OF LENA’S IMAGE
TABLE I. SOFTWARE PACKAGES USED IN IMPLEMENTATION No
1
2
Software
Xilinx platform studio version 12.4 (XPS)
Xilinx software development kit 12.4 (SDK)
Function - XPS is used primarily for mbedded processor hardware system development. - Configuration of the icroprocessor, peripherals, and the interconnection of these components, along with their respective property assignments, takes place in XPS - SDK is the recommended software development environment for simple and complex software applications. While basic software development can be accomplished within XPS, this capability will be removed in a future release.
Version
NC
ET
RET
Mis
Mas
NI
Y
72
6
8
4
16
20
Cb,Cr
24
6
8
4
16
20
12.4
The results of PSNR and compression ratios for Lena are shown in Table IV for different sampling modes. The experimental results on four sampling modes have implied the tradeoff between compression ratio and PSNR should be taken into account for different compression scenarios. 12.4 TABLE IV. FCIC’S RESULTS OF LENA’S IMAGE IMAGE INPUT
DECOMPRESED IMAGE
SAMPLING
C.RATIO
PSNR
4:4:4
11.58
25.94
4:2:2
8.69
26.09
4:2:0
14.78
23.46
4:1:1
11.58
24.48
3) Resource Table II shows the utilization of the system resource, wher one can see the number of slice LUTs required to fulfill the implementation is only about 3% over those available. This proves that the code modification for implementation of FCIC on the FPGA board has effectively exploited the given resourse. TABLE II. SYSTEM RESOURCES USED IN IMPLEMENTATION SLICE LOGIC UTILIZATION
USED
AVAILABLE
UTILIZATION
Number of Slice Registers
2,178
69,120
3%
Number of Slice LUTs
2,152
69,120
3%
Number used as Memory
162
17,920
1%
Number of bonded IOBs
97
640
15%
Number of BlockRAM/FIFO
2
148
1%
Number of DSP48Es
3
64
4%
Number of PLL_ADVs
1
6
16%
IV.
EXPERIMENTAL RESULTS AND PERFORMANCE EVALUATION In order to evaluate the performance of the proposed implementation, a 24-bit Lena color image with size of 64 × 64 has been used in the experiments. Fractal coding schemes are performed at different sampling modes of 4:4:4, 4:2:2, 4:2:0, 4:1:1 respectively, and the full searching mode have been set up to determine the optimized compression ratio.
Since JPEG is well-known compression standard, for performance evaluation, the quantum table of JPEG method has been utilized and set to 1:1024 for maximal compression ratio. As illiustrated in Table V, the performance comparison in terms of PSNR and compression ratios of the two methods in different sampling modes have shown that the fractal coding schemes could outperformed similar PSNR and compression ratio, even better in some sampling modes, eg. Lena image at 4:2:0, or fruit image at 4:2:0, or field image 4:4:4 and 4:1:1. Table VI, VII, VIII, and IX demonstrate the corresponding decompressed Lena, fruit and field images using FIC and JPEG compression methods in four sampling modes: 4:4:4, 4:2:2, 4:2:0, 4:1:1. It is obvious that the quality of decompressed
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image by Fractal method is somewhat superious over that by JPEG.
TABLE VII. DECOMPRESSING IMAGE COMPARISON BETWEEN FRACTAL BASED AND JPEG BASED IMPLEMENTATION AT 4:2:2 SAMPLING
TABLE V. PERFORMANCE COMPARISON BETWEEN FRACTAL BASED AND JPEG BASED IMPLEMENTATION INPUT IMAGES
SAMPLIN
FRACTAL
G
JPEG
FRACTAL
JPEG
COMPRESS
COMPRESS
RATIO
RATIO
PSNR
PSNR
4:4:4
25.94
25.95
11.58
11.26
4:2:2
26.09
28.42
8.69
8.88
4:2:0
23.46
21.73
14.78
14.67
4:1:1
24.48
25.95
11.58
11.26
4:4:4
23.38
20.77
11.13
12.50
4:2:2
23.63
24.20
8.31
9.91
4:2:0
21.59
20.23
14.12
13.79
4:1:1
21.39
20.77
11.13
12.50
4:4:4
34.52
31.15
11.86
11.90
4:2:2
34.68
34.06
8.86
12.25
4:2:0
30.50
25.52
15.55
16.25
4:1:1
32.43
31.15
11.86
11.90
TABLE VI. DECOMPRESSING IMAGE COMPARISON BETWEEN FRACTAL BASED AND JPEG BASED IMPLEMENTATION AT 4:4:4 SAMPLING INPUT IMAGE
FRACTAL'S DECOMPRESSING IMAGE
JPEG'S DECOMPRESSING IMAGE
INPUT IMAGE
FRACTAL'S DECOMPRESSING IMAGE
JPEG'S DECOMPRESSING IMAGE
LENA IMAGE
COLOR BLOCK IMAGE
NATURAL IMAGE
TABLE VIII. DECOMPRESSING IMAGE COMPARISON BETWEEN FRACTAL BASED AND JPEG BASED IMPLEMENTATION AT 4:2:0 SAMPLING FRACTAL'S JPEG'S INPUT IMAGE DECOMPRESSING DECOMPRESSING IMAGE IMAGE LENA IMAGE
COLOR BLOCK IMAGE
NATURAL IMAGE
LENA IMAGE TABLE IX: DECOMPRESSING IMAGE COMPARISON BETWEEN FRACTAL BASED AND JPEG BASED IMPLEMENTATION AT 4:1:1 SAMPLING FRACTAL'S JPEG'S INPUT IMAGE DECOMPRESSING DECOMPRESSING IMAGE IMAGE
COLOR BLOCK IMAGE
LENA IMAGE
NATURAL IMAGE
The promissing results have shown that fractal coding based on RGB to YCrCb color transformation and implemented on FPGA could be applied to a color image, which results excellent compression performance similar to that of JPEG. However, the advantage of FCIC decoder is so smoother and faster than JPEG coding. V.
CONCLUSION
In this paper, an implementation of fractal color image has been realized in Xilinx Virtex 5 (XUPV5-LX110T) FPGA board. The analysis of the experimental results shows that the
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COLOR BLOCK IMAGE
NATURAL IMAGE
compression ratio and PSNR of fractal coding implemented in FPGA is quite similar to JPEG coding, however the image’s quality is superior over JPEG coding. The successful implementation of FCIC on FPGA is expected to exploit the
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advantages of FCIC such as high compression ratio, faster decoding and so forth. With an increasing demand for high quality in coder/decoder techniques, the proposed approach may be further developed to apply for fractal coding for video sequences using high performance FPGA.
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