A 10 ps Time-Resolution CMOS Image Sensor With Two ... - IEEE Xplore

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 51, NO. 1, JANUARY 2016

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A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging Min-Woong Seo, Member, IEEE, Keiichiro Kagawa, Member, IEEE, Keita Yasutomi, Member, IEEE, Yoshimasa Kawata, Nobukazu Teranishi, Fellow, IEEE, Zhuo Li, Member, IEEE, Izhal Abdul Halin, and Shoji Kawahito, Fellow, IEEE

Abstract—A CMOS lock-in pixel image sensor with embedded storage diodes and lateral electric field modulation (LEFM) of photo-generated charge is developed for fluorescence lifetime imaging. The time-resolved CMOS image sensor (CIS) with twotap lock-in pixels achieves a very high time resolution of 10 ps when images are averaged over 30 frames, a very short intrinsic response time of 180 ps at 374 nm, and a low temporal random noise of 1.75e− rms with true correlated double sampling (CDS) operation. In addition, by using the LEFM and optimized process, a very high extinction ratio of approximately 94% at 472 nm laser diode is achieved. The usefulness of the proposed CIS is demonstrated for fluorescence lifetime imaging with the simulation and measurement results. Index Terms—CMOS image sensor (CIS), fluorescence lifetime imaging microscopy (FLIM), high time resolution, time-resolved imaging, two-tap CMOS lock-in pixel.

I. I NTRODUCTION

F

LUORESCENCE lifetime imaging microscopy (FLIM) [1]–[10], a time-resolved imaging method, is a powerful analysis tool in fundamental physics as well as in the life sciences, because fluorescence provides information about the presence and distribution of specific molecules (fluorophores). As the fluorescence signal is very sensitive to the local environment of molecules, it, therefore, also provides a sensing function. Conventional FLIM systems use a gated image intensifier together with charge-coupled devices (CCDs) or a timecorrelated single photon counting (TCSPC) system using a

Manuscript received May 10, 2015; revised September 18, 2015; accepted October 21, 2015. Date of publication December 07, 2015; date of current version December 30, 2015. This work was supported in part by the Grantin-Aid for Scientific Research (S) under Grant 25220905 through the Ministry of Education, Culture, Sports, Science, and Technology (MEXT), in part by the MEXT/JST COI-STREAM program, and in part by the Cooperative Research Project Programs through the Research Institute of Electrical Communication, Tohoku University and the Research Institute of Electronics, Shizuoka University. This paper was approved by Guest Editor Yusuke Oike. M.-W. Seo, K. Kagawa, K. Yasutomi, Y. Kawata, N. Teranishi, Z. Li, and S. Kawahito are with the Research Institute of Electronics, Shizuoka University, Hamamatsu 432-8011, Japan. I. A. Halin is with the Department of Electrical and Electronics Engineering, University Putra Malaysia, 43400 UPM Serdang, Selanger Darul Ehsan, Malaysia. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2015.2496788

photo-multiplier tube (PMT) as a detector and a mechanical laser scanner. Compared with these conventional systems, all-solid-state FLIM systems can be implemented compactly without laser scanners, attain new functions and advanced performance, and create new applications. For instance, an all-solid-state FLIM system may be a key device for nextgeneration endoscopy for cancer-detection based on the lifetime measurements of auto-fluorescence of molecules in living tissues [11], [12]. Electron-multiplication (EM) CCD [2], [3] is used for the advanced FLIM applications. The FLIM imager has a very high EM gain around 5000 and a high fill factor of 50% with an acceptable pixel size, and it can be operated at a high demodulation frequency of 80 MHz. However, a specialized fabrication process for only CCDs and a relatively higher voltage are required. Single-photon avalanche diodes (SPADs) are also used for time-resolved lifetime measurement [4]–[6], [13], [14]. In particular, SPAD-based time-resolved imagers have a high single-photon sensitivity and good noise robustness. However, typical SPAD-based imagers [4], [6], [14] need a large amount of in-pixel circuitry for photon detection, including time-to-digital converters (TDCs), digital counters to accumulate counts, and the readout circuitry. To implement the high photon-counting rate, a large number of TDCs and digital integrators are required. The spatial resolution of the SPAD-based time-resolved imagers is limited on this account. Recently, the development of analog-counting single-photon imagers [5], [13] has been reported. The analog counting technique enables compact in-pixel circuitry, and consequently a high fill factor of over 20%. A recently reported time-resolved CMOS image sensor (CIS) [7] using a draining-only modulation (DOM) technique has an attractive feature of being able to simultaneously attain a very simple pixel structure and twostage charge transfer without a transfer gate. However, it has a small aperture area and a comparatively low transfer speed, and multiple outputs are a challenge. This paper presents a high-time-resolution, low-noise, twotap CMOS lock-in pixel image sensor for fluorescence lifetime imaging using lateral electric field charge modulation (LEFM) and two-stage charge transfer techniques. The sensor has an extremely high time resolution due to the high electric field created by the LEFM technique, a low temporal noise using the true correlated double sampling (CDS) operation, and a high

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spatial resolution for which a large number of pixels can be used because of the compact pixel configuration. The sensitivity of the sensor is sufficiently high due to a relatively large effective fill factor using microlenses. The signal utilization efficiency for measuring the lifetime of mono-exponential decay is also almost 100%, which is achieved through the use of two time windows (TWs). This paper is organized as follows. Section II describes the high-speed charge transfer techniques using the LEFM as preliminary information for the following sections. Section III shows detailed design and operation of the proposed two-tap CMOS lock-in pixel and fluorescence lifetime measurement system. Section IV shows the experimental results. Section V presents the conclusion. II. H IGH -S PEED C HARGE T RANSFER U SING L ATERAL E LECTRIC F IELD M ODULATOR Recent CIS technologies offer many possibilities for introducing new functions to imaging devices. Lock-in pixel imaging is a new generation of imaging with CIS technologies; this can extend the application of solid-state imaging devices in the fields of real-time range imaging and biomedical imaging. In the imagers, using the conventional lock-in pixels [8], [15]–[17], each such pixel detects and transfers photo-induced charges to one or more charge accumulation regions in synchronization with the modulated light through the channel under the gate of a MOS transistor. However, the conventional lockin pixel image sensors have problems with high-speed charge transfer and low-noise signal detection, particularly because single electron transfer is required in biological applications [7], [8]. For charge transfer through an MOS gate channel, it is difficult to modulate the electric field for high-speed directional charge transfer to charge storage, and a potential barrier may be created at the edge of the MOS gate in certain pixels that must be treated as defective because of the deficiency of single-electron transfer. Another problem is a charge transfer loss due to a phenomenon by which photo-induced charge once stored in the channel of the MOS gate is fed back into the photo detector. In addition, during transfer of electrons by the gating operation, electrons are captured in traps at a boundary between silicon (Si) and silicon dioxide (SiO2 ), and the problem of charge transfer delay will occur. To solve these problems, a new approach for charge modulation is developed, as described below. A. Lock-In Pixels Fig. 1 depicts the function of the lock-in pixel with single and multiple outputs. Fig. 1(a) shows a lock-in pixel model of single-tap charge modulator. The photons arrive at the sensing area of the imager. Then photo-current (ip ) generated in the photodiode (PD) is modulated by operating and repeating the TW, and the modulated signal (S) with TW operation is integrated in an integrator or a low-pass filter. The integration is simply implemented by charge accumulation in a capacitor. This operation corresponds to the calculation of a correlation

Fig. 1. Lock-in pixels. (a) Single-tap lock-in pixel. (b) Multitap lock-in pixel.

between the input photo current and the TW function, and a time-dependent component contained in the photo signal is extracted in each pixel of the imager. Fig. 1(b) shows the model of multitap charge modulation pixel. Essentially, the operation principle of the multitap charge modulation pixel is the same as that of the single-tap charge modulation pixel. Signals which correspond to the photo-current generated by photons are modulated by several different TWs (TW1 , TW2 , . . . , TWn ) and accumulated in storage diodes, which are shielded from photons. The modulation is done in charge domain using a high electric field in a very small region of micrometer order. As a result, a very high-speed modulation is realized, allowing the observation of very high-speed phenomena with a time resolution on the order of picoseconds. As a high-speed charge modulation device for lock-in pixel imagers, the authors have proposed a CMOS-compatible charge modulator, or the so-called LEFM [18], [19].

B. Structures of Lock-In Pixels Using LEFM Fig. 2 shows the structure of a two-tap LEFM lock-in pixel with a draining function, and the potential diagrams by varying the gate voltages (TG1, TG2, and TD). This structure has two sets of transfer gates (TG1 and TG2) for applying the lateral electric field, and a set of draining gate (TD) for cleaning undesirable charges in the PPD after time-gating. Two different n-type layers (n1 and n2 ) and p+ pinning layer formed on an optimized p-type epitaxial layer for LEFM are used for making two storage diodes and low-noise readout with true-CDS operation. The gates are not used for draining photo charge, but for controlling electric field in horizontal direction. To do this, a relatively small positive voltage and a negative voltage are supplied for the operation. By applying a negative or small positive voltage to the gates, depleted potential can be modulated while maintaining the potential barrier to the drain. By the TD gate, unwanted charges are almost completely removed

SEO et al.: 10 ps TIME-RESOLUTION CIS WITH TWO-TAP TRUE-CDS LOCK-IN PIXELS

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Fig. 3. Developed two-tap CMOS lock-in pixel for time-resolved imaging. (a) Layout. (b) Equivalent schematic.

C. Pixel Structure for Two-Stage Charge Transfer

Fig. 2. Two-tap LEFM structure with a draining gate (TD). (a) 3-D charge modulator structure. (b) Charge-transfer mode. (c) Draining mode.

and also the TW for modulation (or demodulation) can be handled more flexibly, e.g., in terms of its width and period. This helps to reduce the noise and to improve the time-resolution. However, unlike the role of TG1 and TG2, which are used only to affect the electric field in the channel region, the TD gate itself is used as a channel for draining the charges. Fig. 2(b) and (c) shows the potential diagrams for understanding the operation of two-tap CMOS lock-in pixels with TD gates. As can be seen from Fig. 2(b), the electrons generated in the sensing area are transferred to PSD2 when a low negative voltage (= −1 V), high positive voltage (= 1.5 V), and medium positive voltage (= 0.5 V) are used for TG1, TG2, and TD, respectively. At this time, by using these gate supply voltages, a very steep potential slope is formed allowing high-speed charge transfer in each pixel. Fig. 2(c) shows a potential diagram of the draining mode of a lock-in pixel. When the low negative voltage sets are used for two LEFM gates (TG1 and TG2) and the high positive voltage is used for the TD, the charges in PPD are drained through a channel under the TD gate.

A pixel structure for two-stage charge transfer [7], [8], [20] is important for integrating the signal charges with low-noise signal readout because true-CDS operation is performed using this technique. To successfully design the two-stage charge transfer structure, two significant issues should be addressed: 1) charge transfer from the photo-sensing region to storage region with a short transfer time and 2) charge transfer from the storage region to the floating diffusion (FD) node with a sufficient potential height between the storage region and the FD region to avoid charge-scooping from the FD. As explained in the previous section, the generated electrons are rapidly and completely moved to the PSDs from the PPD by LEFM. The second issue for two-stage charge transfer is confirmed and optimized by a device simulator.This simulation result will be introduced in Section IV. Fig. 3 shows the layout and equivalent pixel schematic of the developed two-tap CMOS lock-in pixel for time-resolved imaging. As can be seen in Fig. 3(a), the pixel comprises a PPD, two PSDs, and three sets of gates (TG1, TG2, and TD). TG1 and TG2 control the electric fields in the diodes and transfer the accumulated signal charges to PSD1 and PSD2 from the PPD, respectively. The TD is used for draining the charge. The potential well of the PSD region is sufficiently deeper than that of the PPD. Therefore, once transferred, the photo charge in the PPD remains stored during the accumulation time. The photo charge is transferred to PSDs along the potential valley that is generated by TG1 or TG2. To do this, high (HIGH: 1.5 V) and low (LOW: −1.0 V) voltages are applied to the gates. Because of these voltages, the accumulated photo-charge in PPD moves upward or downward from the center, and the transferred photo charge is moved to PSDs. The LEFM structure helps to improve the charge transfer speed and noise performance, but limits the sensing area shape to effectively modulate the charges. Thus, a rectangular shape is connected to the proposed pixel. The two

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Fig. 4. Block diagram of the sensor architecture.

source-follower outputs (SF1 and SF2) from each pixel are connected to each of the two column readout circuits, as shown in Fig. 3(b). Photo electrons are transferred to the PSDs when the virtual switch (V_SW1 or V_SW2) is turned ON. The virtual switches are controlled by LEFM gates (TG1 and TG2). In other words, TG1 and TG2 can control the potential profile between the PPD and the PSDs. To reduce the noise, the difference between the two levels (reset and signal levels) is taken by column readout circuits and canceled by a digital CDS operation [see Fig. 5(b)]. When used in a conventional charge-integrating pixel without an in-pixel storage diode, this operation does not cancel the kTC noise because of the “uncorrelated double sampling.” In the proposed pixel, however, the storage diode is embedded with the PD, and the accumulated storage diode signal is read out by a true CDS operation to cancel the kTC noise.

Fig. 5. Noise-robust column-parallel readout circuitry. (a) Block diagram of the FI/C ADC with the analog CDS circuit. (b) Timing diagram.

III. A RCHITECTURE AND F LUORESCENCE L IFETIME M EASUREMENT A. Architecture Fig. 4 shows the block diagram of the sensor architecture. The sensor consists of a time-resolved lock-in pixel array, clock tree, and pixel driver array for controlling the gates (TG1, TG2, and TD), column-parallel folding-integration/cyclic (FI/C) ADCs [19], a logic block for digital CDS, and vertical and horizontal scanner blocks for addressing. To reduce the influence of parasitic RC (resistor and capacitor) components, the chargemodulator driver using an inverter tree is arranged at the upperand lower-sides of the lock-in pixel array, and these two sets of modulation driver blocks are very carefully laid with the clock tree to reduce clock mismatches by different RC components. In particular, in the case of a lifetime measurement method without time-window shifting described in Section III-B, the slight timing mismatch can cause a large error. In other words, these efforts for reducing timing mismatch are very important for realizing a precise lifetime measurement system. A large gain at the column is very effective for reducing the readout noise of CISs. However, the conventional

Fig. 6. Support circuit for the in-pixel charge modulator. (a) Schematic of inverter tree. (b) Modulation driver circuit.

column readout circuits [22], [23] with large gains, such as the gain-adjustable column amplifiers, have small input signal ranges because of the output saturation. This is not suitable for the FLIM applications. Therefore, we chose a FI/C ADC [24], [25]. Fig. 5 shows a schematic diagram and its timing diagram in one horizontal period of noise robust column-parallel readout


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Fig. 7. Timing diagram for operating two-tap CMOS lock-in pixel.

Fig. 9. Photograph of the microscopy setup for fluorescence lifetime imaging.

Fig. 8. Lifetime measurement system using the developed imager.

circuitry. The used readout circuitry consists of an analog CDS circuit for reducing the vertical fixed pattern noise (vFPN) component of the imager and analog core for the FI/C ADC with 1.5b (or 1b) sub-ADC. The pixel, analog CDS, and FI/C ADC are operated with the timing diagram shown in Fig. 5(b). The RT and TX are control signals for resetting the FD node and the charge transfer in the pixel, respectively. Using the clocks PHI1, PHI2, and PHI3, the analog CDS is performed at the beginning of one horizontal readout cycle. PHI1 and PHI2 are turned ON first while PHI3 remains OFF to charge the clamping voltage (VREF_CDS ) in the capacitor CCDS . Then the switch PHI3 is turned ON while the switches PHI1 and PHI2 are turned OFF again for the remainder of the horizontal period. In this operation, the reset-level of the pixel output is clamped to the high-level reference voltage VREF_CDS for the ADC at the output of the CDS circuit, in order to maximize the signal dynamic range. More specifically, it is set at a few tens of millivolts below the VREF_CDS of the ADC. This analog CDS circuit acts as a unity gain buffer to drive the sampling capacitor of the ADC. The analog CDS also helps to realize an extremely low vertical FPN together with a digital CDS technique.

Fig. 10. Chip micrograph.

Using the final output value from the analog CDS, the FIADC is carried out. One cycle of the FI-ADC is composed of sampling and charge transfer phases. In the sampling phase, the

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Fig. 11. 3-D pixel simulation results. (a) Transfer mode. (b) Draining mode.

Fig. 12. Plots of carrier transportations with equipotential lines. (a) Transfer mode. (b) Draining mode.

output from the analog CDS is sampled multiple times (M) by the control clocks PHI4 and PHI7, and then the charge transfer phase is performed by the DAC operation with the digital code (D0 ) from the sub-ADC and the control clock PHI8. The amplifier output (VOUT ) is compared with a reference voltage of [(VRH + VRL )/2], where VRH and VRL are the high- and low-level reference voltages for the ADC, respectively. After the FI-ADC mode, the operation of the analog core is switched to the cyclic ADC (C-ADC) mode to perform analog-to-digital conversion of the final integrator output in the FI-ADC mode. For obtaining 13 bit resolution in the C-ADC, the analog core performs the 12 cycles of A/D conversion. Each cycle consists of a feedback sampling phase (using PHI5 and PHI7) and a charge transfer phase using DAC operation with the digital codes (D0 and D1 ) and PHI8. At this point, reference voltages for two comparators are changed to VRCH and VRCL , where VRCH is (3VRH + VRL )/4 and VRCL is (VRH + 3VRL )/4. When the control pulse TX in the pixel is applied, photo-signal level appears at the pixel output, and then A/D conversion for the signal-level will commence. The operations for the FI-ADC and the C-ADC for the signal level are the same as those for the reset-level sampling. The FI-ADC has m bit resolution by sampling the pixel output M times, where m = log2 M . The successive FI operations with M samplings and 13 bit C-ADC have a total equivalent

resolution of 13 + m − 1 bits. High-resolution A/D conversion is applied for both the reset and photo-signal levels of the pixel output, and the digital CDS is applied to attain very high cancelation capability of vFPN and to reduce the temporal random noise of the pixel amplifier. The spatial uniformity of the lock-in pixels is determined by the parasitic RC components of the metal wires, which cause voltage-drop and clock-skew. Therefore, a clock driver circuit and its support circuits should be designed and laid out very carefully. To do this, a clock tree structure and a largesize buffer are used for the prototype sensor. Fig. 6 shows the schematic diagrams of the inverter clock tree and the modulation driver, which are located at upper- and lower-sides of the pixel array, respectively. The clock tree has five stages and the number of inverters in each stage is 1, 4, 16, 64, and 256, respectively. A final output signal from the clock tree is delivered to the charge modulation driver. As can be seen from Fig. 6(b), the driver is composed of three stages with different buffer sizes for driving the control signals, where VLEF_TGH (or VTDH ) and VLEF_TGL (or VTDL ) are 1.5 V (or 3 V) and −1 V (or −1 V), respectively. The clock bias condition of developed pixel, e.g., VTDL , is different from that of a conceptual two-tap LEFM pixel because of the different pixel structure used for achieving a large aperture. By using these circuits, the measured clock skew of the entire pixel array is approximately


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Fig. 13. Simulation results for the two-stage charge transfer from PSD to the FD node. (a) Depleted potential changes by the TX gate voltage. (b) Plot of potential barrier (ΔVB ) as a function of the TX gate voltage.

Fig. 14. Experimental results for the two-tap lock-in pixel operation with different time delays. (a) 0 ns. (b) 6 ns. (c) 9 ns. (d) 20 ns. (e) 23 ns. (f) 35 ns.

89 ps (at rms value, targeted value: less than 100 ps) without any skew compensations. This result is sufficiently small for achieving uniform two-dimensional (2-D) lifetime imaging. The fast rising and falling edges (both less than 1 ns) of the clock are achieved as well because of the driver circuits for charge modulation.

circuitry (see Fig. 5) after finishing the accumulation period. During the readout period, CK_TD is always set to high; on the other hand, CK_TG1 and CK_TG2 are set to low. To obtain the whole fluorescence decay profile, the excitation pulse timing is shifted by an external (or internal) pulse delay controller. In this case, only selected single-tap among the two time-windows is used for the measurement. Then, the frame cycle consisting the accumulation and readout periods is repeated if further accumulation of signals as digital data is necessary in an external system. Finally, a clear fluorescence decay curve of sample is obtained using each accumulated signal as a function of the amount of shifts of the TW, and we find the lifetime of the sample from the decay curve. However, obtaining the whole decay curve is a long process, because of the repeated shifting of the excitation pulse delay and signal capturing. The latency for obtaining the decaying curve causes a problem of photo bleaching. If only lifetime information is desired, the mentioned problems can be solved using the two-tap modulator as described below. In a two-tap CMOS lock-in pixel, lifetime is measured with the two time-windows per single frame, resulting in two signals (S1 and S2 ) being stored in the PSDs. Two TWs using clocks CK_TG1 and CK_TG2 control the capture timing of the accumulated signals S1 and S2 , respectively. S1 is expressed as the time-integral of charge from 0 to T . S2 is expressed as the integral from T to infinity (∞). But these signals include offset components as well as pure fluorescence signal components (S1 or S2 ), and can, therefore, be expressed as follows:

B. Sensor Operational Principle Two measurement methods are used to measure the lifetime. One is the typical solution with time-window shifting, and the other is the calculation manner using the stored signals in PSDs without time-window shifting. To obtain the whole fluorescence decay profile, the first manner should be used; on the other hand, if only lifetime information is needed, the second manner can be used. In this section, these two measurement methods for the developed CMOS imager are explained in detail. Fig. 7 shows the timing diagram for operating the two-tap CMOS lock-in pixel. The total timing consists of two parts: 1) an accumulation period and 2) readout period. In the accumulation period, high levels are given to CK_TG1 and CK_TG2 for transferring the charge to PSD1 (or PSD2) from the PPD, and CK_TD is set to high value for draining the undesirable signal when CK_TG1 and CK_TG2 are set to a low value. To obtain a high signal-to-noise ratio (SNR), many cycles of these operations are repeated. The accumulated signals in the PSDs are then read out through high-performance column readout

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Fig. 17. Input-referred temporal random noise of the developed imager (at temp. = 15 ◦ C).

Fig. 15. Measured linearity of the developed time-resolved imager as a function of the number of TWs (at 472 nm laser diode). (a) Linear scale. (b) Logarithmic scale. Fig. 18. Photo responsivity of the developed imager (at 3746 K light source with IR-cut filter).

Fig. 16. Intrinsic responses of the developed imager with different laser diodes for excitation.

S1 = S1 + background signal (offset components)

(1)

S2 =

(2)

S2

+ background signal (offset components).

The offset components come from the slow-response carrier components, a dark current of the image sensor, and a light source for excitation. To measure the precise lifetime of the fluorescent specimen, these offset components should be eliminated. They are removed by subtracting a sampled signal under dark condition and using the band-pass filter. After eliminating the offset components, the two pure signals S1 and S2 corresponding to the emitted fluorescence signals are obtained. These signals are expressed as

Fig. 19. Lifetime measurement of the three types of acrylic fluorescence screens.

T t S1 = I0 exp − dt τ 0 ∞ t I0 exp − dt S2 = τ T

(3) (4)

where I0 is the incident intensity and τ is the fluorescent object’s lifetime. From the accumulated signals of S1 and S2 ,


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Fig. 20. Relationships between the measured lifetime and the target lifetime. (a) Deconvolution results. (b) Measurement results using the two time window per single frame.

components by the excitation laser light. These unwanted components are filtered by the dichroic mirror and an optical band-pass filter to obtain the pure fluorescence emission light. Finally, the fluorescent light is introduced to the developed image sensor. Fig. 9 shows a photograph of a real fluorescence lifetime measurement setup. The total system comprises a microscope, an excitation light source with its controller, a high time resolution delay controller for shifting the trigger signal for the excitation, and the developed CMOS imager for the fluorescence lifetime imaging. The measurement system volume can be downsized and optimized using an internal delay controller (on chip or on board) and a small-sized light source module.

IV. I MPLEMENTATION AND E XPERIMENTAL R ESULTS

Fig. 21. Measured time resolution of the developed time-resolved imager.

which are obtained by the two time-windows operation, we can find the lifetime of the specimen without scanning the excitation pulse delay τ =−

ln

T S2 S1 +S2

.

(5)

As a result, we can obtain the lifetime information about fluorescent samples in a short time using (5). In other words, real-time lifetime imaging can be realized using two-tap CMOS lock-in pixel. C. Measurement Setup for Fluorescence Lifetime Imaging The microscopy setup for fluorescence lifetime imaging is shown in Fig. 8. Synchronized laser light by the sensor’s trigger signal is delivered into the microscope for the excitation. Excitation light is reflected by a dichroic mirror and irradiates on the specimen. Then, a fluorescence light is emitted from the specimen. The emission light includes other noise components such as the background light, reflected light, and parasitic

A CIS with two-tap lock-in pixels for obtaining the timeresolved imaging is implemented with pinned PD 0.11 µm 1-poly 4-metal CMOS technology. The die micrograph of the implemented sensor chip is shown in Fig. 10. The size of the chip is 7.0 (H) × 9.3 (V) mm2 . Fig. 11(a) and (b) shows the three-dimensional (3-D) potential distributions in the transfer and draining modes, respectively. From these results, we confirm that the potential barrier between the PPD and PSDs, or the PPD and the draining node, is perfectly suppressed by the LEFM and TD gate operation. In these simulations, the gate voltages are TG1 and TD = LOW and TG2 = HIGH for charge-transfer, and TG1 and TG2 = LOW, TD = HIGH for charge draining. Fig. 12 shows plots of the equipotential lines and carrier transportations for two cases of the charge transfer mode and the charge draining mode. A red-dotted circle denotes the initial position of an electron generated by a photon and a black-dotted line indicates the movement trace of an electron. The direction of the electron flow is controlled by the gate voltages of TG1, TG2, and TD. The charge transfer time from the initially generated position to the PSDs or draining node is less than 1 ns, even if the generated electron is far away from the destinations.

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Fig. 13 shows the simulation results for the two-stage charge transfer from PSD to FD, when the accumulated signals are read out. The depleted potential diagram along with X − X [see Fig. 3(a)] is shown in Fig. 13(a). VDEP_SD and VTX are the maximum depth of the PSD’s potential well and the minimum potential of the TX (transfer gate) channel, respectively. VB denotes the voltage difference between VDEP_SD and VTX . The change of the potential barrier (VB ) when supplying different TX gate voltages is plotted as shown in Fig. 13(b). In this plot, potential barriers of 0 V or negative value mean that all accumulated signal charges can be completely transferred to FD node without any loss. Also, there are no potential pockets, which can cause an image lag, as can be seen from the potential diagram [see Fig. 13(a)]. Fig. 14 shows the result of a measurement to confirm the twotap lock-in pixel operation by shifting the excitation laser pulse timing. The measurement conditions are as follows: 1) time delay range: 0 to 36 ns with 1 ns step; 2) used sample: microbeads (size: 15 µm, lifetime: approximately 2 − 3 ns); 3) width of the TWs: 12.7 ns; and 4) wavelength of the excitation light source (laser diode): 374 nm. Several captured images [(a)–(e)] with different delay times among the whole images are picked up and sequentially shown in this figure. In this measurement, the excitation light is eliminated by an optical band-pass filter and the images in Fig. 14 are due to fluorescence light components from only the sample. In Fig. 14(a), the emitted fluorescence decay profile is obtained just before entering to the first TW (CK_TG1), so that no signals appear in the images (PSD1 and PSD2). Then, by increasing the excitation pulse delay, the emitted fluorescence of the micro-beads is entered into the first time-window (CK_TG1) and the signal begins to appear in PSD1, as shown in Fig. 14(b). By continuing to increase the excitation pulse delay, the emitted fluorescence profile is perfectly entered in the first TW in Fig. 14(c), so that dense signals appear in PSD1, and the profile is then shared in the first and the second (CK_TG2) TWs, as shown in Fig. 14(d), such that relatively weak signals appear both in PSD1 and PSD2. Under this measurement condition for obtaining S1 and S2 , the two obtained signals controlled by a delay time factor of T are used for the lifetime calculation, as mentioned in Section III. In Fig. 14(e), the emitted fluorescence decay profile enters perfectly into the second TW so that dense signals appear in PSD2, and then the profile leaves the two TWs (CK_TG1 and CK_TG2) in Fig. 14(f) as the excitation pulse delay is further increased, such that signals disappear again from the images. From these measurement results obtained by scanning the excitation pulse delay, we confirm that the developed two-tap CMOS lock-in pixel with LEFM performs successfully. The linearity of the prototype imager is plotted in Fig. 15. Fig. 15(a) and (b) shows the linearity as a function of the number of TWs (or light pulses) on linear and logarithmic scales, respectively. In this measurement, the number of TWs increases from 0 to 1,100,000 and a 472 nm laser diode (pulse width: 120 ps, maximum peak power: 48 mW) is used as a light source. Two plots for the operation under the transfer mode (◦ mark) and the draining mode (× mark) are included in Fig. 15. In the transfer mode, the TWs of the gating signals (TG1, TG2, and TD) capture and integrate


the charges. In the draining mode, however, the gating signals (TG1, TG2, and TD) are set to drain the charges generated in PPD. The results show a very high extinction ratio of approximately 94%, which is a significant characteristic for achieving a high-resolution precise lifetime measurement. The parasitic sensitivities of SD1 and SD2 are also measured with the clock (TG1 and TG2) modulation and 374 nm laser diode. This parameter is a significant factor for sensor evaluation. The parasitic sensitivity of SD1 when the gate voltages are TG1 = LOW and TG2 = HIGH is approximately 0.4%, and that of SD2 when the gate voltages are TG1 = HIGH and TG2 = LOW is approximately 2.4%. Both parasitic sensitivities of PSDs are low enough to measure the fluorescence lifetime using two-tap CMOS lock-in pixel. The LEFM pixel with a finite charge transfer time has its own intrinsic response, which is determined by the dispersion of the light spot on the photo-diode, the dispersion of the transfer time, and the wavelength of the light source. In other words, the measured lifetimes without any forms of compensation such as deconvolution are bounded by the intrinsic response. Therefore, the sensor’s intrinsic response should be cared for improving the measurement accuracy. The LEFM can help to accelerate the intrinsic response, and these results can be confirmed with the different light sources by the following measurement. To measure the intrinsic responses, the excitation lights at wavelengths from 374 to 851 nm are illuminated directly and uniformly on the prototype image sensor. The specific conditions (FWHM and peak power) of light sources for the measurement are as follows: 1) 374 nm laser: 74 ps, 47 mW; 2) 443 nm laser: 72 ps, 131 mW; 3) 472 nm laser: 120 ps, 48 mW; 4) 635 nm laser: 88 ps, 152 mW; and finally, 5) 851 nm laser: 69 ps, 84 mW. The measured intrinsic responses of the imager are shown in Fig. 16. The horizontal axis is the delay time of the TW and it is shifted from 0 to 2 ns with a time step of 100 ps. As can be seen from Fig. 16, the developed imager achieves a very short intrinsic response time of approximately 180 ps with a 374 nm laser diode. Even if a laser with a longer wavelength, such as 851 nm, is used, a sufficiently fast intrinsic response of around 370 ps is still achieved. This characteristic of the imager with the two-tap CMOS lock-in pixel using LEFM helps to realize an accurate lifetime measurement system. Fig. 17 shows the input-referred noise of the developed imager. A sufficiently low noise level is achieved for the fluorescence lifetime imaging with a slight chip-cooling. The low ◦ noise level of 1.75e− rms at 15 C with an analog gain of 128, which is achieved by the column readout circuitry, is attained by the optimized pixel structure with the LEFM and the true CDS operation. The photo-responsivity of the developed CMOS imager as a function of light intensity is shown in Fig. 18. The proposed CMOS lock-in pixel imager with microlenses achieved a high sensitivity of 137 ke− /lux · s. Also, a large full well capacity of each storage diode around 2700e− is confirmed from this measurement result. The fluorescence lifetimes of three types of acrylic fluorescent screens are measured, as shown in Fig. 19. An ultraviolet laser diode with the wavelength 374 nm and pulse width 74 ps is used to excite all the fluorophores, and the total exposure


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Fig. 22. Temporal resolution distributions of the pixel array with different numbers of the averaging frames. (a) Single frame. (b) 10 frames. (c) 20 frames. (d) 30 frames. (e) 40 frames. (f) 50 frames.

Fig. 23. Color map of the measured lifetimes on the CHO cell with DAPI and quantum dot (at Ex. 374 nm laser diode).

time for obtaining the fluorescence decay profiles is 6.4 ms. The measured lifetimes of blue, green, and orange acrylics are 1.25 ns (reference value: 0.9 ns), 3.4 ns (3.0 ns), and 6.0 ns (6.7 ns), respectively. To confirm the accuracy of the measured lifetimes, the reference lifetime of each fluorescent acrylic is measured by a conventional TCSPC measurement system. The measured lifetimes are almost the same as the reference values; however, those acrylic screens with relatively short lifetimes, such as blue and green, are slightly different because of the intrinsic response of the imager. This can be compensated by a deconvolution of the intrinsic response. Fig. 20 shows the measurement lifetimes using a single time-window (CK_TG1 only) per frame [Fig. 20(a)] and two TWs (CK_TG1 and CK_TG2) per frame [Fig. 20(b)]. The measured lifetimes from which the intrinsic response of the imager is deconvoluted is also shown in Fig. 20(a). In Fig. 20(b), the lifetime is measured by (5) in Section III using two signals S1 and S2 . The target lifetime is indicated as a gray solid line with a gradient of 1. In Fig. 20(a), the deconvoluted lifetimes (+ mark) are quite close to the

reference values. The measured lifetimes in Fig. 20(b) using two TWs per frame are sufficiently accurate when compared with those of Fig. 20(a). This demonstrates the effectiveness of this measurement method, which has the advantage of being able to live imaging using fluorescence lifetime at reasonable frame rate. Fig. 21 shows the measured time resolution of the two-tap CMOS lock-in pixel. In this paper, the time (or temporal) resolution is defined as a standard deviation (στ ) of the fluorescence decay profiles which are obtained by a repetitive measurement. To measure the time-resolution of the developed imager, the intrinsic decaying curve at 374 nm is used. The intensity of the excitation light is adjusted to obtain sufficiently large numbers of electrons because the time-resolution is determined by the photon shot noise. The horizontal axis shows the number of image frames used for averaging, which reduces the influence of the temporal random noise and the photon shot noise. For frame numbers larger than 10, the time resolution is smaller than 11 ps. The best resolution of 10 ps is attained when 30 frames are used for averaging. The time resolution of 13.9 ps is attained even without averaging. Fig. 22 shows the time-resolution distributions of the pixel array averaged over different numbers of frames when the intrinsic decay profile at 374 nm is used. The sampled pixel number is 100 pixels from the center area of the entire pixel array. The time-resolution distribution including the clock skew and the temporal random noise components is slightly improved by the averaging effect. As can be seen from these results, however, the number of averaging frames does not significantly affect improvement of spatial uniformity, except in the case of single frame-use. This means that the developed imager has a good spatial uniformity without any compensation. (The worst case of temporal resolution is approximately 25 ps.)

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TABLE I P ERFORMANCE S UMMARY

TABLE II C OMPARISON W ITH S TATE - OF - THE -A RT F LUORESCENCE I MAGING D EVICES

∗ Time-resolution

is defined as a Standard Deviation (σT ) of the fluorescence decay profile

Fluorescence lifetime images of a Chinese hamster ovary (CHO)-cell with DAPI (4’, 6-diamidino-2-phenylindole) and quantum dots are plotted into a color map in which different lifetime values are represented as different colors, as shown in Fig. 23. The fluorescent samples are excited by a 374 nm laser diode (at peak power: 47 mW, FWHM: 74 ps), the total exposure time is 13.4 ms. We observed that the DAPI, which has the short decays (approximately 1–3 ns), is faster than the quantum dot, which has long decays (approximately 15 ns). In this case, the DAPI and quantum dots in CHO-cell are expressed in green and red color, respectively.

The sensor performance and characteristics are summarized in Table I. The image sensor has an effective pixel array of 256 (H) × 512 (V) and a pixel size of 11.2 × 5.6 µm2 with a relatively large fill factor of 16.7%. In addition, the two-tap CMOS lock-in pixel using LEFM achieves a very short intrinsic response time of 180 ps at 374 nm, and has a high pixel conversion gain of 85 µV/e− and a large full well capacity of the PSD of 2700e− . Table II shows the performance comparison of various detector types including a CCD, a SPAD, and the CMOS lock-in pixels for fluorescence lifetime imaging. Unfortunately, in the cases of the CCD and SPAD, many


parameters cannot be directly compared with the developed sensor’s performance because of differences of the interests and the parameter expressions. For fair comparison, the time resolution of the SPAD [4] is a value reported as the standard deviation of the time-stamping measurement with a Rhodamine 6G in water. To achieve a high time resolution of 10 ps using the developed imager, the repetition number of TWs for signal sampling in single-frame cycle (see Fig. 7) should be 250,000 and the signal sampled by in-pixel operation is averaged over 30 frames. The pulse width of TW is 6.3 ns. This table shows that the proposed two-tap CMOS lock-in pixel has a good performance for measuring the fluorescence lifetime when compared with state-of-the-art technologies for FLIM.

V. C ONCLUSION In this paper, a high time resolution two-tap CMOS lock-in pixel sensor for fluorescence lifetime imaging has been presented. A very high time resolution of 10 ps was achieved when data was averaged over 30 frames; we also obtained a very short intrinsic response time of 180 ps at a 374 nm laser diode, and a very high extinction ratio of 94%. The proposed pixel has two-tap output ports with intermediate storage for reducing the kTC noise using true-CDS operation and reducing the latency for obtaining the fluorescence lifetime. The developed two-tap CMOS lock-in pixel image sensor will be useful not only as an imaging tool for life sciences and biological study, but also for use in new medical tools based on time-resolved imaging techniques.

R EFERENCES [1] W. Becker, Advanced Time-Correlated Single Photon Counting Techniques. New York, NY, USA: Springer, 2005, vol. 81. [2] J. Bosiers et al., “MEM-FLIM, a CCD imager for fluorescence lifetime imaging microscopy,” in Proc. Int. Image Sensor Workshop (IISW), Jun. 2013, pp. 53–56. [3] Q. Zhao et al., “Modulation electron-multiplied fluorescence lifetime imaging microscope: All-solid-state camera for fluorescence lifetime imaging,” J. Biomed. Opt., vol. 17, no. 12, pp. 126020-1–126020-13, Dec. 2012. [4] D.-U. Li et al., “Real-time fluorescence lifetime imaging system with a 32 × 320.13µm CMOS low dark-count single-photon avalanche diode array,” Opt. Express, vol. 18, no. 10, pp. 10257–10269, May 2010. [5] M. Perenzoni, N. Massari, D. Perenzoni, L. Gasparini, and D. Stoppa, “A 160 × 120-pixel analog-counting single-photon imager with subns time-gating and self-referenced column-parallel A/D conversion for fluorescence lifetime imaging,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 200–201. [6] M. Vitali et al., “A single-photon avalanche camera for fluorescence lifetime imaging microscopy and correlation spectroscopy,” IEEE J. Sel. Topics Quant. Electron., vol. 20, no. 6, pp. 344–353, Nov./Dec. 2014. [7] Z. Li et al., “A time-resolved CMOS image sensor with drainingonly modulation pixels for fluorescence lifetime imaging,” IEEE Trans. Electron Devices, vol. 59, no. 10, pp. 2715–2722, Oct. 2012. [8] H. J. Yoon, S. Itoh, and S. Kawahito, “A CMOS image sensor with inpixel two-stage charge transfer for fluorescence lifetime imaging,” IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 214–221, Feb. 2009. [9] M. W. Seo et al., “A 10.8 ps-time-resolution 256×512 image sensor with 2-tap true-CDS lock-in pixels for fluorescence lifetime imaging,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 198–199.

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[10] M. W. Seo, K. Kagawa, K. Yasutomi, N. Teranishi, and S. Kawahito, “Time-resolved imaging device with high-speed modulators for fluorescence lifetime measurement system,” in Proc. Int. Image Sensor Workshop (IISW), Vaals, Netherlands, Jun. 2015, pp. 251–254. [11] J. R. Lakowicz, H. Szmacinski, K. Nowaczyk, and M. L. Johnson, “Fluorescence lifetime imaging of free and protein-bound NADH,” Proc. Natl. Acad. Sci. USA, vol. 89, pp. 1271–1275, Feb. 1992. [12] K. Kagawa et al., “Dual-band multi-aperture enhanced redox imaging of colonic adenomas for endoscopes with a high-performance CMOS imager,” in Proc. 35th Annu. Int. Conf. IEEE Eng. Med. Biol. Soc. (EMBC), Osaka, Japan, Jul. 2013, pp. 1414–1417. [13] L. Pancheri, N. Massari, and D. Stoppa, “SPAD image sensor with analog counting pixel for time-resolved fluorescence detection,” IEEE Trans. Electron Devices, vol. 60, no. 10, pp. 3442–3449, Oct. 2013. [14] N. Dutton et al., “A time-correlated single-photon-counting sensor with 14GS/s histogramming time-to-digital converter,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2015, pp. 204–205. [15] S. J. Kim, J. D. K. Kim, B. Kang, and K. Lee, “A CMOS image sensor based on unified pixel architecture with time-division multiplexing scheme for color and depth image acquisition,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2834–2845, Nov. 2012. [16] D. Stoppa, N. Massari, L. Pancheri, M. Malfatti, M. Perezoni, and L. Gonzo, “A range image sensor based on 10-µm lock-in pixels in 0.18µm CMOS imaging technology,” IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 248–258, Jan. 2011. [17] B. Buttgen, F. Lustenberger, and P. Seitz, “Demodulation pixel based on static drift field,” IEEE Trans. Electron Devices, vol. 53, no. 11, pp. 2741– 2747, Nov. 2006. [18] S. Kawahito et al., “CMOS lock-in pixel image sensors with lateral electric field control for time-resolved imaging,” in Proc. Int. Image Sensor Workshop (IISW), Jun. 2013, pp. 361–364. [19] S. M. Han, T. Takasawa, K. Yasutomi, S. Aoyama, K. Kagawa, and S. Kawahito, “A time-of-flight range image sensor with background canceling lock-in pixels based on lateral electric field charge modulation,” IEEE J. Electron Devices Soc., vol. 3, no. 3, pp. 267–275, May 2015. [20] K. Yasutomi, S. Itoh, and S. Kawahito, “A two-stage charge transfer active pixel CMOS image sensor with low-noise global shuttering and a dual-shuttering mode,” IEEE Trans. Electron Devices, vol. 58, no. 3, pp. 740–747, Mar. 2011. [21] J. Guo and S. Sonkusale, “A 65 nm CMOS digital phase imager for timeresolved fluorescence imaging,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1731–1742, Jul. 2012. [22] A. Krimski, K. Khaliullin, and H. Rhodes, “A 2e- noise 1.3Megapixel CMOS sensor,” in Proc. IEEE Workshop CCD Adv. Image Sensors, Elmau, Germany, 2003, pp. 1–6. [23] M. Sakakibara et al., “A high-sensitivity CMOS image sensor with gainadaptive column amplifiers,” IEEE J. Solid-State Circuits, vol. 40, no. 5, pp. 1147–1156, May 2005. [24] M. W. Seo et al., “A low-noise high intrascene dynamic range CMOS image sensor with a 13 to 19b variable-resolution column-parallel folding-integration/cyclic ADC,” IEEE J. Solid-State Circuits, vol. 47, no. 1, pp. 272–283, Jan. 2012. [25] M. W. Seo et al., “A low-noise high dynamic-range 17-b 1.3-megapixel 30-fps CMOS image sensor with column-parallel two-stage foldingintegration/cyclic ADC,” IEEE Trans. Electron Devices, vol. 59, no. 12, pp. 3396–3400, Dec. 2012.

Min-Woong Seo (S’11–M’13) received the B.S. and M.S. degrees in electronics engineering from Kyungpook National University, Daegu, Korea, in 2007 and 2009, respectively, and the Ph.D. degree in engineering from Shizuoka University, Hamamatsu, Japan, in 2012. From 2012 to 2014, he was a JSPS Postdoctoral Research Fellow with the same research group, Imaging Devices Laboratory (IDL), Shizuoka University, where he has been specially appointed as an Assistant Professor with the Research Institute of Electronics since 2014. His research interests include CMOS imaging devices, bioimaging, and mixed analog/digital circuit designs. Dr. Seo was the recipient of the Grand Prize at 7th IDEC Design Contest from IDEC Regional Center, Kyungpook National University, Daegu, Korea, in 2008, the Commendation by the Dean of the Graduate School of Science and Technology, Shizuoka University in 2012, and the IEEE Nagoya Section Young Researcher Award from the IEEE Nagoya Section in 2015.

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Keiichiro Kagawa (M’10) received the Ph.D. degree in engineering from Osaka University, Osaka, Japan, in 2001. In 2001, he joined the Graduate School of Materials Science, Nara Institute of Science and Technology, Ikoma, Japan, as an Assistant Professor. In 2007, he joined the Graduate School of Information Science, Osaka University, as an Associate Professor. Since 2011, he has been an Associate Professor with Shizuoka University, Hamamatsu, Japan. His research interests cover highperformance CMOS image sensors, imaging systems, and their biomedical applications.

Keita Yasutomi (S’08–M’11) received the Ph.D. degree in enginneering from Shizuoka University, Hamamatsu, Japan, in 2011. He is currently an Assistant Professor with the Research Institute of Electronics, Shizuoka University. His research interests include high-speed CMOS image sensors and low-noise pixel design. Dr. Yasutomi is a member of the Institute of Electronics, Information, and Communication Engineers of Japan and the Institute of Image Information and Television Engineers of Japan. Yoshimasa Kawata received the Ph.D. degree in applied physics from Osaka University, Osaka, Japan, in 1992. From 1992 to 1995, he was with Osaka University, as an Assistant Professor. From 1995 to 1996, he was at the AT&T (Lucent Technologies) Bell Laboratories, Murray Hill, NJ, USA, as a Visiting Researcher. From 1997 to 2005, he was with Shizuoka University, Hamamatsu, Japan, as an Associate Professor, where he has been a Professor since 2005. His research interests include optics, applied physics, and bio-imaging. Dr. Kawata was the recipient of the Excellent Paper Awards from Japan Society of Applied Physics in 1997, the JJAP Editing Award by Japan Society of Applied Physics in 2003, and the Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science, and Technology, Prizes for Science and Technology in 2007, and the OSA Fellow by the Optical Society, USA in 2013. Nobukazu Teranishi (M’96–SM’08–F’10) received the B.S. and M.S. degrees in physics from the University of Tokyo, Tokyo, Japan, in 1976 and 1978, respectively. From 1978 to 2000, he was with the NEC Corporation, Tokyo, Japan. From 1986 to 1987, he was with Arizona State University, Tempe, AZ, USA, as a Visiting Researcher, researching quantum transport required time. From 2000 to 2013, he was with the Panasonic Corporation, Kyoto, Japan, where he served as the General Manager in charge of process development, application technology, and marketing of image sensors. Since 2013, he has been a Professor with the University of Hyogo, Kobe, Japan, and Shizuoka University, Hamamatsu, Japan, and the Visiting Scientist at Riken, Hyogo, Japan. He is the author and coauthor of 102 papers. He holds 21 USA patents and 47 Japanese patents. Mr. Teranishi was selected as a Fellow of the Institute of Image Information and Television Engineers (ITE), Japan, in 2003. He was the recipient of the National Invention Awards in 1994, the Commendation by the Minister of State for Science and Technology in 1997, the Progress Medal and Honorary Fellow by the Royal Photographic society, U.K., in 2010, Niwa-Takayanagi Lifetime Achievement Award by ITE in 2013, Yamazaki Teiichi Prize by Foundation for Promotion of Material Science and Technology of Japan in 2013, and J. J. Ebers Award by IEEE Electron Devices Society in 2013. He served as a Guest Editor of the IEEE T RANSACTIONS ON E LECTRON D EVICES for the special issues on solid-state image sensors in 1997, 2003, and 2009. He cofounded the International Image Sensor Society (IISS) in 2006, where currently he is a President.

Zhuo Li (S’10–M’13) received the B.E. degree in telecommunication engineering from Xi’an University of Posts and Telecommunications, Xi’an, China, in 2004, and the M.E. and Ph.D. degrees in engineering from Shizuoka University, Hamamatsu, Japan, in 2009 and 2013, respectively. Currently, he is specially appointed as an Assistant Professor with Shizuoka University. His research interests include time-resolved CMOS image sensors.

Izhal Abdul Halin received the B.S. degree in electrical engineering from the University of Hartford, West Hartford, CT, USA, in 1999, and the M.S. degree in microelectronics engineering from the Universiti Putra Malaysia, Serdang, Malaysia, in 2002. In 2013, he was a Visiting Researcher at the Research Institute of Electronics, Shizuoka University, attached to the Imaging Devices Laboratory. Currently, he is a Senior Lecturer in Microelectronics Engineering with the Universiti Putra Malaysia. His research interests include CMOS delay line circuits and CMOS image sensors.

Shoji Kawahito (S’86–M’88–SM’00–F’09) received the Ph.D. degree in engineering from Tohoku University, Sendai, Japan, in 1988. Since 1999, he has been a Professor with the Research Institute of Electronics, Shizuoka University, Hamamatsu, Japan. Since 2006, he has been the CTO of Brookman Technology Inc., Hamamatsu, Japan, a University spin-off company for CMOS imager developments. His research interests include CMOS imaging devices, sensor interface circuits, and mixed analog/digital circuits designs. He has authored more than 300 papers in peer-reviewed journals and international conference proceedings. Dr. Kawahito is a Fellow of the ITE, a member of IEICE, and a member of SPIE. He served as a Technical Program Committee Member of the ISSCC from 2009 to 2012, and a Program Committee Chair of the 2011 International Image Sensor Workshop. He is the Chair of the SSCS Japan Chapter from 2013 to 2014. He was the recipient of several awards including the Outstanding Paper Award at the 1987 IEEE International Symposium on Multiple-Valued Logic, the Special Feature Award in LSI Design Contest at the 1998 Asia and South Pacific Design Automation Conference, the Beatrice Winner Award for Editorial Excellence at the 2005 IEEE International Solid-State Circuits Conference, the IEICE Electronics Society Award in 2010, and the Takayanagi Memorial Award in 2010 and the Walter Kosonocky Award in 2013.