A High-Sensitivity CMOS Image Sensor With Gain ... - IEEE Xplore

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 5, MAY 2005

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A High-Sensitivity CMOS Image Sensor With Gain-Adaptive Column Amplifiers Masaki Sakakibara, Member, IEEE, Shoji Kawahito, Senior Member, IEEE, Dwi Handoko, Member, IEEE, Nobuo Nakamura, Hiroki Satoh, Mizuho Higashi, Keiji Mabuchi, and Hirofumi Sumi, Member, IEEE

Abstract—A high-sensitivity CMOS image sensor using gain-adaptive column amplifiers is presented and tested. The use of high gain for the column amplifier reduces input-referred random noise, and when coupled with a column-based digital noise cancellation technique, also reduces fixed pattern noise. An experimental application of the circuit using 0.25- m CMOS technology with pinned photodiodes gave an rms random noise of 263 V and an rms fixed pattern noise of 50 V. Index Terms—CMOS image sensors, column amplifier, gain-adaptive amplifier, low readout noise.

I. INTRODUCTION

C

OMPLEMENTARY metal-oxide semiconductor (CMOS) image sensors, in contrast to charge-coupled device (CCD) image sensors, have the advantages of low power consumption, a single supply voltage, and the capability for on-chip system integration. However, the image quality of CMOS images sensors at low light levels is not yet comparable to CCD. In CMOS image sensors, photo signals are read out through a signal chain consisting of a pixel source follower buffer, a column noise canceller, and an output buffer amplifier. This configuration renders CMOS image sensors highly susceptible to random noise originating from the many sources along the signal readout chain. However, the flexibility of the signal readout architecture in CMOS image sensors may allow low-noise image sensors to be realized. One possibility is to use high-gain amplifiers for the column noise canceller of the CMOS image sensor. In this paper, the noise-reduction effect of using such high-gain column amplifiers is discussed based on noise analysis and an experimental application of the proposed circuit, incorporating gain-adaptive column amplifiers [1] and four-transistor active pixels with pinned photodiodes [2]–[4]. The use of high gain at the column amplifier may result in a reduction of the dynamic range due to saturation of the amplifier at high pixel output signal levels. However, as the signal-tonoise ratio (SNR) at high pixel signal levels is adequate without high-gain amplification, this problem can be avoided by adaptively varying the pixel gain using a comparator array on the Manuscript received October 21, 2003; revised December 7, 2004. M. Sakakibara and S. Kawahito are with the Research Institute of Electronics, Shizuoka University, Hamamatsu, 432-8011, Japan (e-mail: [email protected]). D. Handoko is with the National Agency for Assessment and Application of Technology, Jakarta 10340, Indonesia. N. Nakamura, M. Higashi, K. Mabuchi, and H. Sumi are with the Semiconductor Network Company, Sony Corporation, Atsugi, Kanagawa 243-0014, Japan. H. Satoh is with Sony LSI Design Inc., Yokohama 240-0005, Japan. Digital Object Identifier 10.1109/JSSC.2005.845969

column. A similar technique has been used for wide-dynamic range CMOS image sensors in which three-transistor pixels are employed [5]. In the previous circuits, however, the reset noise, as the dominant source of random noise at low light levels, is not reduced although the overall random noise of the readout circuit is lower. In the four-transistor active pixels where the reset level is read out first for the correlated double sampling (CDS), a special consideration is necessary in order to use the adaptive gain amplifier for the CDS circuit. The proposed gain-adaptive amplifier has a switch to isolate the amplifier input from the pixel output to accommodate the CDS operation for the charge-transfer type active pixels to the gain-adaptive amplification. Experimental results have shown that the use of high gain on the column is very effective for reducing random noise and fixed pattern noise (FPN) through column-based digital-domain noise canceling. Furthermore, the dynamic range achieved by this approach is comparable to standard CCD image sensors. In this paper, the principle of operation is introduced and described in detail. A noise analysis of the column amplifiers is then conducted to determine the effectiveness of the high-gain column amplifier. Finally, the results of an experimental implementation are described and discussed. II. PRINCIPLE OF OPERATION Fig. 1 shows a block diagram of the proposed CMOS image sensor. The major sources of random noise at low light levels are reset noise, dark current shot noise, and read amplifier noise. Reset noise and dark current shot noise can be suppressed by employing pinned photodiode technology [3]–[5]. Read amplifier noise and fixed pattern noise are reduced by introducing low-noise high-gain column amplifiers. To avoid saturation of the amplifiers at high pixel output voltage, an adaptive-gain technique is also used, by which the gain can be set at 1 or 8 as the sensor output depending on the amplitude of the amplified signal. If the sensor output is less than one-tenth of the saturation level, the gain is set adaptively to 8 to enhance the sensitivity and reduce the total input referred read noise. At higher sensor outputs, the gain is set to 1. Fig. 2 show the circuit schematic for the pixel circuit and the gain-adaptive column amplifier. Figs. 3 and 4 show the timing diagram and operation, respectively. An important design issue is the accommodation of the gain adaptation with the CDS operations. In the three-transistor active pixel circuit without in-pixel charge transfer, the operation is easier because the signal level is first read out and is sampled at the input capacitor of the column CDS amplifier and the comparator can sample simultaneously

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Fig. 1. Block diagram of proposed sensor chip (P: pixel; C: comparator; S/H: sample-and-hold circuit).

the signal level to determine the gain [5]. On the other hand, in the four-transistor active pixels with in-pixel charge transfer, the reset level is first read out and is sampled at the capacitor of the column CDS amplifier. Therefore, the comparator can not prepare for the gain adaptation at the timing of first sampling of the pixel output. To solve this problem, a switch to isolate the input capacitor of the CDS amplifier from the pixel is introduced. The reset level of the pixel output is first sampled at the input capacitor (8C) as shown in Fig. 4(a). Before the conopens the transfer gate of the pixel, the switch trol signal controlled by is turned off to isolate the input capacitor from the pixel output. The signal level appearing at the pixel output when the transfer gate is opened first passes to the comparator, as where the signal is compared with a threshold voltage is chosen to be slightly lower than shown in Fig. 4(b). The one-eighth of the saturation voltage of the sensor output so as to avoid the need for high-precision comparators. The comparator ) control the switches for the connections outputs ( , of capacitors to the feed back pass of the amplifier as shown in Fig. 4(c), and then the pixel output of the signal level is connected to the input capacitor by turning on the switch controlled for the CDS and amplification. The amplifier output is by then given by (1) where and are the reset level and the signal level of the is the short circuit voltage of the pixel output, respectively, is the common reset level. The column amamplifier and plifier functions as a correlated double sampling circuit so as to

Fig. 2.

Gain-adaptive column amplifier with CDS function.

Fig. 3.

Timing diagram for gain-adaptive column amplifier.

cancel the reset noise and fixed pattern noise. As the comparators use the common reset level, the fixed pattern noise due to the pixel transistors influences the comparison level at the comparators. However, by choosing a sufficiently small threshold level of the comparator compared to the one-eighth level of the full scale of the column amplifier, the influence of the FPN due to the deviation of the comparison level can be avoided. The output of the comparator is read out as a one-bit digital code of the applied gain. The amplified signals, each with individual gain, are sampled and held for horizontal scanning. One of the possible problems arising in a four-transistor active pixel circuit with in-pixel charge transfer is a reduction of

SAKAKIBARA et al.: A HIGH-SENSITIVITY CMOS IMAGE SENSOR WITH GAIN-ADAPTIVE COLUMN AMPLIFIERS

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Fig. 5. (a) Gain-boosted column amplifier. (b) Equivalent circuit.

The precision of digital FPN canceling deteriorates if the analog interface circuits have a nonlinear response. To achieve high linearity in the switched-capacitor column amplifier, the open-loop gain of the internal amplifier should be sufficiently high. For high open-loop gain and simple configuration, a gainboosted cascode amplifier shown in Fig. 5(a) is used [8]. This technique increases the open-loop gain by enhancing the equivalent output resistance of the amplifier. Fig. 5(b) shows the equivalent circuit. Two common source amplifiers with nMOS and pMOS transistor inputs are used for regulation of gates of cascoded nMOS and pMOS transistors, respectively, of the core cascode amplifier. MOS transistors with low threshold voltage transistors are used to attain a sufficient linear range of 1.1 Vp-p with 2.5-V supply voltage. III. NOISE ANALYSIS

Fig. 4. (a) Reset level sampling phase. (b) Signal level comparing and gain decision phase. (c) Signal amplification phase at gain 8.

the saturation voltage. To avoid this issue, a technique to increase the saturation voltage through appropriate timing of the is introduced. The timing is adjusted pixel selection signal such that the rise on occurs a little later than the fall on the reset control signal . This effectively bootstraps the reset level of the floating diffusion node to a higher voltage, increasing the resulting saturation voltage to 1.0 V. This technique contributes to the improvement for SNR by increasing the signal swing.

In order to estimate the achievable noise level using the proposed column amplifier, the random read noise was analyzed for the signal path including the source follower in the pixel, the column amplifier, and the sample-and-hold (S/H) circuits. Thermal noise component only is analyzed. The circuit for the readout signal path is shown in Fig. 6(a). The noise of this circuit consists of two components; a component due to noise charge sampled at the charge summation node of the switched capacitor (SC) amplifier and transferred to the feedback capacitor (sample-and-transfer noise), and a component sampled directly at the S/H stage (directly sampled noise) [7]. The equivalent circuits used for analyzing the sample-and-transfer noise and directly sampled noise are shown in Fig. 6(b) and (c). The two noise components are analyzed individually as a function of the . The three major noise sources gain, which is given by to be considered are the pixel source follower, the column amplifier, and the reset switch. The sample-and-transfer noise is calculated using transfer functions of these three noise sources, to the charge summation node. The resulting noise charge at the charge summation noise when the reset switch controlled by is then transferred to is opened. On the other hand, the directly sample noise is calculated by transfer functions of the pixel source follower and the column amplifier to the S/H capacitor. It is sampled at

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Fig. 6. (a) Circuit from pixel to S/H. (b) Equivalent circuit for sample-and-transfer noise. (c) Equivalent circuit for directly sampled noise.

TABLE I PARAMETERS FOR NOISE ANALYSIS

Fig. 7. Simulated rms noise.

capacitor when the switch controlled by is opened. As the sample-and-transfer noise and the directly-sampled noise are sampled at different timing, the two noise components are independent. Therefore, the total noise power is simply added. Fig. 7 shows the calculated noise as a function of the gain of the column amplifier. For comparison with the measured results,

the isolated noise for the column amplifier and S/H stage were also calculated. The circuit implemented in the experimental part of this study has switches before the switched-capacitor column amplifiers to measure the noise in the column amplifier and the S/H stage. The parameters used for the noise calculation are listed in Table I. These parameters were determined from the design of experimental circuit described later. The main effect of the high-gain column amplifier is to attenuate noises originating from the output amplifier and the external circuits connected to

SAKAKIBARA et al.: A HIGH-SENSITIVITY CMOS IMAGE SENSOR WITH GAIN-ADAPTIVE COLUMN AMPLIFIERS

Fig. 9.

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Digital canceling of offset and gain noise from the column amplifiers.

Fig. 8. Photograph of the experimental sensor chip.

the image sensor output. In addition to this effect, Fig. 7 suggests that the noise from the amplifier itself can be reduced by increasing the gain of the column amplifier. Using a gain of 8, for example, the random readout noise can be reduced to less than 80 V (rms). The total noise for the path from column to S/H is lower than that for the path from pixel to S/H because it is assumed that a stable dc source is connected to the input of . the column amplifiers via a switch with on-resistance of IV. IMPLEMENTATION AND RESULTS A CIF-size image sensor chip with area of 4.3 mm (H) 5.0 mm (V) was fabricated using a 0.25- m triple-metal double-poly CMOS with pinned photodiode technology (Fig. 8). The analog sensor output was digitized using a 14-bit 10 MS/s analog/digital converter (ADC) with a resolution of 122 V and full-scale range of 2 Vp-p. The input-referred resolution at gain of 8 is 15 V. This high resolution allows for the precise canceling of fixed pattern noise. The column noise canceller used in CMOS image sensors targets pixel-related FPN. However, the column noise canceller itself also causes FPN related to vertical stripes due to the offset and gain deviations of the column circuits. Digital-domain processing is useful for canceling FPN related to the column amplifiers. Fig. 9 shows a block diagram of the digital FPN correction circuit employed here to reduce offset- and gain-deviation noise from the column amplifiers. The offset and gain deviations are measured using a zero input and a constant voltage for both is given by gains (1 and 8). The corrected output (2)

Fig. 10.

FPN plot with and without digital FPN cancellation.

where is the output before correction, is the offset correction coefficient and is the gain correction coefficient given where is the measured gain and is the gain by deviation from the ideal gain. The gain correction coefficients and the offset correction coefficients for the gains of 1 and 8 are stored in four 1H (364) memory cells. A 1-bit gain code as a sensor output is used for choosing the offset and gain coefficients and for shifting 3 bits to set the gain to 8 when required. If a high-resolution video ADC is used, the 3-bit shift provides a sufficient digital dynamic range. In the experimental camera, the digital FPN cancellation circuits were implemented on a FPGA. Fig. 10 shows the column FPN plot at a gain of 1 without noise-canceling, and at gain of 8 with noise-canceling for dark signal level. The offset FPN only is cancelled. The rms column-to-column FPN is reduced from 1.7 mV without cancellation to 50 V with cancellation. Fig. 11(a) shows the measured transfer characteristic of the gain-adaptive column amplifier and Fig. 11(b) shows the linearized transfer characteristic in small signal level. There are two types of gain errors in the column amplifier; the gain average error and the gain deviation from column to column. The measured gain errors with and without gain error correction are summarized in Table II. With digital error correction, the

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Fig. 12.

Fig. 11.

Random noise plot with and without column gain amplification.

Input to output characteristics of column circuit.

TABLE II MEASURED GAIN ERROR ( : STANDARD DEVIATION; AVE.: AVERAGE OF THE DISCONTINUITY ERROR)

standard deviation ( ) of the gain error at the full scale is reduced to a very small value as shown in Table II. The difference of average gain between 1 and 8 causes discontinuity as shown in Fig. 11(b). The average of the discontinuity error at the switching point from 8 to 1 is approximately 5 mV without the gain error correction. Using the digital correction of gain error based on (2), the average of the discontinuity error at the gain switching point is reduced to 415 V. Fig. 12 shows the input-referred random noise plots for amplification gains of 1 and 8. The input-referred rms noise is reduced from 785 V at a gain of 1 to 263 V with an adaptive gain of 8. Sample images captured by the image sensor are shown in Fig. 13. The raw analog output is shown in Fig. 13(a). Pixel outputs of less than 100 mV are amplified with the gain of 8, resulting in amplification of the darker regions to the range of 0 to

Fig. 13. (a) Raw image without gain correction. (b) Reconstructed image with gain correction.

800 mV. The corrected image, where the pixel outputs amplified by a gain of 8 are divided by 8 in the digital domain to ensure linearity, is shown in Fig. 13(b). There is no visible degradation due to the use of two different gains in the one image. Fig. 14

SAKAKIBARA et al.: A HIGH-SENSITIVITY CMOS IMAGE SENSOR WITH GAIN-ADAPTIVE COLUMN AMPLIFIERS

Fig. 14.

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Images taken at low illumination levels of 1 to 10 lx (Gain = 8, F = 2:8, 30 frames/s).

TABLE IV MEASURED RMS NOISE

TABLE III MEASURED PERFORMANCE SUMMARY

V. DISCUSSION

shows images taken at low object illuminations of 1, 2, 5, and 10 lx. Here, the removal of FPN in the digital domain can be seen to be very effective. Fig. 15 compares the effects of column amplifier gain and digital FPN canceling at an object illumination of 1 lx. Table III summarizes the measured performance of the sensor. The pinned photodiode technology reduces the dark current to a level comparable to CCD, and the random read noise at a gain of 8 is very low compared to conventional CMOS image sensors.

The measured rms noise for two cases is compared in Table IV. The first case is random read noise measured under dark conditions, which includes noise due to the readout circuit chain of the pixel to the output (P-to-O), and the second case is when a dc signal is connected to the input of the column amplifier to eliminate the effect of pixel-related noise (C-to-O). These results confirm that the noise due to the column amplifier itself and the successive column S/H stage can be estimated. The measured mean square noise voltages for C-to-O are given by (3) (4) for the gain of 1

and 8

, where

and

represent the noises due to the column amplifier and the

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Fig. 15. Comparison of images capture under low light at gain of 1 (a) without and (b) with FPN cancellation, and at gain of 8 (c) without and (d) with FPN cancellation (1 lx, F = 2:8, 30 frames/s).

S/H stage at gains of 1 and 8, respectively, and is the sum of the output amplifier noise and quantization noise of the 14-bit ADC. From (3) and (4) (5) This can be approximated by (6) Therefore, the input-referred rms noise is calculated as follows: V

(7)

This result is in relatively good agreement with the noise analysis in Fig. 7 of 61 V . Similarly, the mean square noise for P-to-O at a gain of 8 is given by (8) (9)

The input-referred rms noise is then calculated as

V

(10)

This result is much larger than the simulation result for thermal noise components of 82 V . There are possible reasons for this discrepancy. In the noise analysis, the thermal noise component only is analyzed. However, there exist some other noise sources. One possibility is 1/f noise of the pixel circuits. Since the size of MOS transistors in the pixel is very small, the 1/f noise of the pixel circuits may contribute to the readout noise although the CDS operation significantly reduces the 1/f noise. In the noise measurement from column to output, the measured value is well agreed with the simulation for the thermal noise components. This can be understood that the 1/f noise component of column amplifier is relatively small because the transistors used in the column amplifier is relatively large compared with those for the pixel transistors, and the 1/f noise is inversely proportional to the channel area of the transistors. However, the 1/f noise only does not explain this is too large discrepancy because the readout noise of 243 V compared with the calculated 1/f noise with CDS operation for

SAKAKIBARA et al.: A HIGH-SENSITIVITY CMOS IMAGE SENSOR WITH GAIN-ADAPTIVE COLUMN AMPLIFIERS

the pixel device size used and typical flicker noise parameters [7]. Another possibility is the noise coupled from power supply, ground line or silicon substrate to the pixel source follower during the readout operation. For the noise coupled from the power supply or ground line, the situation is completely different between the two cases with and without pixel circuits. In the measurement from column to output, a stable DC source is connected to the input of the column amplifier. On the other hand, in the case of the measurement from pixel to output, the column amplifier input is connected to total of 294 pixels and long vertical metal signal line. All the transistors of 294 pixels and the long vertical signal line can be “antennas” of capacitive or conductive coupling noise from the power supply, ground or silicon substrate. In other word, it is very sensitive to the noise via power supply, ground line or substrate in the case of the measurement from pixel to output. Furthermore, switching noises due to the readout operations of the other column circuits may contribute to the readout noise of each column readout circuit. In order to include this effect in the noise analysis, total of 294 360 pixels and 360 vertical wirings have to be taken into account. The discrepancy between the noise analysis and the measurement result suggests us the importance of a new methodology of noise analysis modeling for array-type sensors.

VI. CONCLUSION A CMOS image sensor with gain-adaptive column amplifiers was presented as a sensor suitable for imaging at low light levels. The rms random noise and FPN were effectively reduced to 263 and 50 V (rms), respectively, while maintaining a dynamic range of 71 dB. The noise analysis showed that the use of high gain for the column noise canceller is very effective for reducing not only the noise after the column but also noise from the column amplifier itself. In experiments using a prototype sensor, the total input-referred random noise at an amplifier gain of 8 was about 1/3 that at a gain of 1. The discontinuity occurred at the threshold of comparators can be suppressed to the same order of random noise by a digital gain correction. Although the random noise in the experimental sensor was higher than expected, the noise should be able to be reduced further using this design through optimization of the circuit and timing.

REFERENCES [1] S. Kawahito, M. Sakakibara, D. Handoko, N. Nakamura, H. Satoh, M. Higashi, K. Mabuchi, and H. Sumi, “A column-based pixel-gain-adaptive CMOS image sensor for low-light-level imaging,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 224–225. [2] R. Guidash, T.-H. Lee, P. P. K. Lee, D. H. Sackett, C. I. Drowley, M. S. Swenson, L. Arbaugh, R. Hollstein, F. Shapiro, and S. Domer, “A 0.6 m CMOS pinned photo diode color imager technology,” in IEDM Tech. Dig., Dec. 1997, pp. 927–929. [3] K. Yonemoto, H. Sumi, R. Suzuki, and T. Ueno, “A CMOS image sensor with a FPN-reduction technology and a hole accumulated diode,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2000, pp. 102–103.

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[4] I. Inoue, H. Nozaki, H. Yamashita, T. Yamaguchi, H. Ishiwata, H. Ihara, R. Miyagawa, H. Miura, N. Nakamura, Y. Egawa, and Y. Matsunaga, “New LV-BPD (Low voltage buried photo-Diode) for CMOS imager,” in IEDM Tech. Dig., Dec. 1999, pp. 883–886. [5] M. Schanz, C. Nitta, A. Busmann, B. J. Hosticka, and R. K. Werthimer, “A high-dynamic range CMOS image sensor for automotive applications,” IEEE J. Solid-State Circuits, vol. 35, pp. 932–938, Jul. 2000. [6] S. Kawahito and N. Kawai, “Noise calculation model for high-gain column amplifiers of CMOS image sensors,” Proc. SPIE, vol. 5017, pp. 48–58, 2003. [7] N. Kawai and S. Kawahito, “Noise analysis of high-gain, low-noise column readout circuits for CMOS image sensors,” IEEE Trans. Electron Devices, vol. 51, no. 2, pp. 185–194, Feb. 2004. [8] B. Razavi, Design of Analaog CMOS Integrated Circuits. New York: McGraw-Hill, 2001.

Masaki Sakakibara (M’03) was born in Aichi, Japan, in 1979. He received the B.E. and M.E. degrees in electrical and electronic engineering from Shizuoka University, Hamamatsu, Japan, in 2001 and 2003, respectively. He is currently pursuing the D.E. degree at Shizuoka University, Hamamatsu, Japan. His research interest is in low-noise image sensors and column parallel analog/digital converters. He is a member of the Institute of Image Information and Television Engineers of Japan.

Shoji Kawahito (M’86–SM’00) was born in Tokushima, Japan, in 1961. He received the B.E. and M.E. degrees in electrical and electronic engineering from Toyohashi University of Technology, Toyohashi, Japan, in 1983 and 1985, respectively, and the D.E. degree from Tohoku University, Sendai, Japan, in 1988. In 1988, he joined Tohoku University as a Research Associate. From 1989 to 1999, he was with Toyohashi University of Technology. From 1996 to 1997, he was a Visiting Professor at ETH, Zurich. Since 1999, he has been a Professor with the Research Institute of Electronics, Shizuoka University. His research interests include CMOS smart image sensors, signal processing circuitry for integrated sensors, and mixed analog/digital LSI circuits. Dr. Kawahito received the Outstanding Paper Award at the 1987 IEEE International Symposium on Multiple-Valued Logic, and the Special Feature Award in LSI Design Contest at the 1998 Asia and South Pacific Design Automation Conference. He is a member of the Institute of Electronics, Information and Communication Engineers of Japan, the Institute of Image Information and Television Engineers of Japan, and the International Society for Optical Engineering.

Dwi Handoko (S’01–M’01) received the B.E. and M.E. degrees in electronic engineering from Miyazaki University, Miyazaki, Japan, in 1994 and 1996, respectively, and the D.E. degree in electronic engineering from Shizuoka University, Hamamatsu, Japan, in 2001. He was a Postdoctoral Fellow in the Research Institute of Electronics of Shizuoka University from April 2001 to March 2002. He was an Indonesian Goverment Scholarship Fellow from 1989 to 1994 and from 1998 to 2001. He is now working for The Agency for Assesment and Application of Technology, Indonesia. His research interests include integrated circuit design, image processing, and computation and simulation technology.

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Nobuo Nakamura was born in Kumamoto, Japan, on November 30, 1964. He received the B.E. and M.E. degrees in electrical and electronics engineering from Toyohashi University of Technology, Aichi Prefecture, Japan, in 1987 and 1989, respectively. He joined the ULSI Research Center, Toshiba Corporation, Kawasaki, Japan, in 1990, where he has been engaged in the research and development of DRAM and CCD image sensor. He has also been developed of CMOS image sensor from 1995. He changed to the image sensor business group of SONY Corporation in 2000. He is now developing the CMOS image sensor and managing the business of the CMOS image sensor. Mr. Nakamura is a member of the Institute of Image Information and Television Engineers of Japan.

Hiroki Satoh received the B.E. and M.E. degrees in electronic condensed matter physics from Tokyo Metropolitan University, Tokyo, Japan, in 1995 and 1997, respectively. In 1997, he joined Sony LSI Design inc., Kanagawa, Japan, where he was engaged in the research and design of delta-sigma ADC. Since 2000, he has been engaged in the design for CMOS image sensor. His research interest is also in analog CMOS integrated circuits.

Mizuho Higashi joined Sony Corporation in 1985, Kanagawa, Japan, where she was engaged in the development of design environment for CMOS and CCD devices in the CAD department. Since 2000, she has been engaged in the development of design environment for CMOS image sensor at the Imaging Devices Business Group, Semiconductor Network Company, Sony Corporation.

Keiji Mabuchi was born in Ehime, Japan, in 1967. He received the B.E. degree in applied physics from the University of Tokyo, Japan, in 1990 and the M.S. degree in physics from Nagoya University, Japan, in 1992. He joined the ULSI Research Center, Toshiba Corporation, Kawasaki, Japan, in 1993, where he worked on soft error of dynamic RAM, then fabrication process for amorphous silicon stacked CCD, and then development of CMOS image sensors. In 1998, he joined Semiconductor Company, Sony Corporation, Atsugi, Japan, where he has been engaged in the research, development, and mass production of CMOS image sensors.

Hirofumi Sumi (M’03) was born in Yonago, Tottori, Japan, on February 14, 1960. He received the B.E., M.E., and Ph.D. degrees in electronic engineering from Tottori University, Tottori, Japan, in 1983, 1985 and 1997, respectively. In 1985, he joined Sony Corporation, Atsugi, Kanagawa, Japan, where he was engaged in the development of CMOS system LSI devices and processes in the ULSI Laboratory. Since 1998, he has been engaged in the development of device architecture for CMOS image sensor at the Imaging Devices Business Group, Semiconductor Network Company, Sony Corporation.