A fully digital architecture for trigger circuits in programmable logic ...

3314

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 6, DECEMBER 2002

A Fully Digital Architecture for Trigger Circuits in Programmable Logic Andrea Di Odoardo, Angelo Geraci, Member, IEEE, Giancarlo Ripamonti, and Matteo Seminari

Abstract—A digital trigger module for high-resolution nuclear spectroscopy, composed of three filters operating in parallel and a resolver, is introduced. The single filters are optimized so as to allow low-level discrimination as well as high time-resolving capabilities. Particular care is taken in order to minimize hardware resources. In the case of a high-resolution gamma spectroscopy system based on quasi-coaxial HPGe detectors, the lower threshold discrimination level can be as low as 4 keV while measuring the 1.17-MeV 60 Co line. The capability of discriminating gamma photons impinging almost at the same time is limited in practice only by the intrinsic charge-collection time of the detector. The circuit is implemented in a programmable device (field-programmable gate array) and exploits at best hardware resources already allocated to the filter for energy estimate. A built-in calibration circuit is also implemented, which allows easy setting of discrimination thresholds. It is shown that the devised architecture can be easily upgraded to accommodate a higher number of parallel filters if a further increase of circuit performance is required. Index Terms—Digital filters, nuclear physics, programmable logic devices, trigger circuits.

I. INTRODUCTION

I

N THE last few years, many digital signal processors (DSPs) for nuclear spectroscopy have been designed and commercialized, e.g., Canberra—InSpector 2000 and ORTEC—DSPEC Plus, as an alternative to the classic analog systems [1]. The use of DSP methods allows the fabrication of weighting functions (WFs) of almost arbitrary shape [2]. These can therefore be customized for yielding the optimum filter in the experimental noise conditions. Further constraints in the WF can also be enforced, such as a flat top to cope with a finite charge-collection time, and a finite duration, important for pileup rejection [3]–[10]. One of the most important advantages of digital processing in comparison with analog processing is therefore the possibility of implementing the optimum WF and of modifying it with no hardware change, in order to optimize the resolution of the measurement to the actual experimental conditions. Many methods for processing nuclear data with DSPs have been proposed [11]–[19]. Among them, the multiple-delay-line Manuscript received April 30, 2002; revised July 30, 2002. This work was supported by the Italian MIUR and INFN. A. Di Odoardo, A. Geraci, and G. Ripamonti are with the Department of Electronics, Politecnico of Milano, MI 20133 Milan, Italy, and the National Institute for Nuclear Physics INFN (e-mail: [email protected]; [email protected]; [email protected]). M. Seminari is with the Department of Electronics, Politecnico of Milano, MI 20133 Milan, Italy (e-mail: [email protected]). Digital Object Identifier 10.1109/TNS.2002.806203

DL method (Fig. 1) consists of an analog (pre) filter followed by an ADC and a digital finite impulse response (FIR) filter, and is here considered as the reference setup [18], [19]. With a proper design of the weights of the digital filter, overall (analog filter FIR filter) WFs can be obtained, which fulfill these requirements: 1) finite duration, i.e., WF identically zero outside of a given time interval; 2) flat top of arbitrary duration with very good flatness, and 3) almost arbitrary shape of the rise and fall of the WF. The peculiarity of the DL method is the very low necessary sampling frequency, due to the presence of the analog prefilter. We have already proposed the architecture of the DL processor to be particularly suited for implementation in a programmable device [field-programmable gate array (FPGA)]; in fact, spatial computing allows improvements both in hardware resource economy and in working frequency. In this paper, we show that the aforementioned peculiarities of digital processing, adaptive filtering, and spatial computation can be effectively employed for the fabrication of a trigger signal. This is not surprising, since, in practice, a trigger circuit should filter the same data stream fed to the main energy filter, but with a different WF, suited to the purpose. Fabricating a trigger signal means satisfying at best different, sometimes conflicting, requirements. Although the problems are well known, it is worth recalling them here, in order to appreciate how a digital implementation can address each issue. 1) Signal discrimination: A good trigger circuit should be able to distinguish an incoming signal on a noise floor. This requirement is just the same as an energy measurement filter. The only difference is that after a trigger circuit there is a threshold, which assesses whether a pulse has been detected at that time or not. In order to maximize the probabilities of discriminating a low-energy event from the noise, the longest possible WF should be used. In the following, we refer to this requirement as “reliability.” 2) Multiple hit detection: If the detector captures two or more closely spaced events, the trigger circuit should be able to appreciate such multiplicity. In fact, the energy filter in this case would pile up and thus its output should be discarded. This requirement conflicts with the previous one: in fact, in order to maximize the capture of low-energy events, the trigger should filter out the noise (i.e., a low-pass action), but in order to allow multiple hit detection, the filtering WF duration should be kept to a minimum. In the following, we refer to this requirement as “robustness.”

0018-9499/02$17.00 © 2002 IEEE

ODOARDO et al.: FULLY DIGITAL ARCHITECTURE

3315

Fig. 1. Measurement setup for multiple-delay-line (DL) processor. The cascade of an analog filter F (s) and a numeric filter H (z ) perform the filtering action. The latter can be easily modified to optimize the noise filtering while fulfilling arbitrary constraints. The analog stage is made of a charge preamplifier and an amplifier, which is called a shaper or prefilter. Except for the ADC, all the digital stage is implemented into a programmable device (FPGA). Note that signal flows from right to left.

3) Finite charge-collection time: If the detector has a significant charge-collection time, the current pulse is spread over time. If too short a trigger WF is established, there is a chance that single events are considered as a multiple hit, or even that no event at all is detected. In fact, a very short WF does not integrate the entire detector signal but only a portion of it, and consequently the filter output can be too close to the noise floor to be detected. Of course there is a fundamental difficulty in distinguishing a pulse with a long charge-collection time from two or more very close events. Unless pulse-shape analysis is introduced, the two cases are indistinguishable. A reasonable choice is that the WF duration of the trigger filter be at least the maximum charge-collection time of the considered detector. 4) Drifting baseline level: Since the detection of an event is obtained by comparing the trigger filter output against a threshold, any drift in the baseline level (due, e.g., to a preamplifier slow pole poorly compensated) translates to a change of the minimum energy detectable by the trigger. If the minimum energy is reduced, the chance increases for a false trigger on a noise peak, while if it is increased, low-energy events could remain undetected. A solution for this problem, used also in analog setups, is to employ a baseline restorer in the trigger detection circuitry. Although some provisions of this kind are used in this paper, this point deserves more study in order to assess whether or not there is an “optimum” approach to the problem. 5) Timing precision: Of course it is necessary that the arrival time of each detected event be correctly evaluated. If a lack in timing precision is present, the main energy filter should present a flat top long enough to accommodate the entire charge under it, independent of timing error. If the duration of the flat top is increased, however, the energy resolution of the instrument is reduced. In the following, we refer to this requirement as “precision.” In this paper, we propose an architecture suited for spatial computing implementation, which is devoted to full digital trigger of incoming digitized pulses. The major advantages of this approach are: 1) no additional discrete circuitry is needed; 2) possibility to embed trigger generation and digital processing section into the same device;

Fig. 2. The detection system for trigger signal generation is a bench of three parallel stages. Sampled data from ADC are simultaneously fed to the stages. Each ith stage is the cascade of a digital filter h (n) followed by an elaboration logic section. The outputs of the stages meet in a processing block called a resolver, which generates the final trigger signal.

3) reconfigurability of the trigger stage. We shall show that additional savings in the hardware resources can be achieved by using portions of the main energy filter for trigger purposes. For the sake of clarity, the architecture is discussed referring to its implementation into the cited DL processor. However, the presented solution is fully general, i.e., a technology independent design source, which is easily portable into other digital processors. II. ARCHITECTURE The proposed architecture of the digital trigger system is shown in Fig. 2. Sampled data from the analog-to-digital converter (ADC) are sent to a bench of three parallel filtering banks (called stages), each one devoted to address one or more of the different requirements cited in the previous section, and, in practice, to process different spectral regions of the incoming signal. In other words, the digitized signal undergoes a rough spectral decomposition in a number (three in this case) of windows, which are treated separately: the number of windows is the result of the compromise between achievable performances and system efficiency. The outputs of the stages are combined by a resolver that generates the output trigger signal.

3316

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 6, DECEMBER 2002

A. Stage 1 Stage 1 maximizes precision and robustness. To these purposes, the high-frequency components of the detector signal should pass through the filter, i.e., a very short WF is generated. In order to do this, we revert the conditioned signal at the output of the analog shaper stage to a shape close to the current signal at the detector output, which can be considered to be delta-like if charge-collection problems are disregarded. In our setup [11], [19], the cascade of the preamplifier and the analog shaper filter (see Fig. 1) before the ADC has a transfer function characterized by three real, coincident poles of time constant . Its impulse response, normalized to unit area, may be expressed in the time domain as (1) Sampling the signal with frequency sequence is obtained:

, the following

(2) whose

Fig. 3. Simulation of a stream of sampled data at the output of the filter h (n) of Stage 1. The considered detector is a large-volume HPGe quasi-coaxial detector [20]. The duration of the signal generated at the electrodes of this detector is strongly dependent on the drift path of the charge cloud generated in the interaction between the impinging photon and the detector. The time constant of the shaper poles is set at 330 ns (which corresponds to a shaped pulse of about 3 s for a detector signal of negligible time duration), and a rectangular shape at the detector output is supposed. The plot shows an example of three isoenergetic signals at the output of the h (n) filter, which last 100, 200, and 400 ns at detector output.

-transform is Therefore, this filter recovers the high-frequency components of the input signal shaped by the preamplifier analog shaper cascade (3) (7)

To reconstruct an almost delta-like sequence from the sampled shaped pulse (1), a digital system whose transfer function is the inverse of (3) must be considered. We arrange the inverse of (3) to put in evidence an FIR and an infinite impulse response (IIR) component. To obtain a signal of rigorous finite time duration, we neglect the IIR component of the inverse filter but maintain the true dc gain: that means to reconstruct a “delta-like” signal instead of a precise digital delta

To get a better efficiency in selecting high frequencies, it would be possible even to increase the relative weight of high frequenfilter by cascading it with a high-pass filter, cies in the e.g., (8) where (9)

(4) This transfer function corresponds to a system with temporal impulse response

(5) which means that the reconstructed delta-like signal will be

(6)

, which is fed by Fig. 3 shows the output of the filter sampled pulses from the analog processor referred to above. Note that in (9) has to be chosen in order to keep continuous frequency components of the signal passing through filter , which prevents hard malfunctions due to rate change during operation. filter is fed to a logic that generates The output of the output crosses a a signal of “event detected” when the suitable threshold. The overall structure of Stage 1 is shown in Fig. 4(a). The considerable capability of this stage in resolving piled-up events should be noted, as Fig. 5 shows. There are of course various limits connected to the use of Stage 1. Being a wide-band filter, this filter does not filter the electronic noise very effectively (which has in general a spectral density referred to the input that increases with frequency). Therefore, this filter is poorly sensitive to low-energy events. Furthermore, the quantization noise introduced in the analog-to-digital conversion process is also enhanced. Finally,

ODOARDO et al.: FULLY DIGITAL ARCHITECTURE

3317

Fig. 4. Block diagrams of (a) Stage 1, (b) Stage 2, and (c) Stage 3. Depicted waveforms are simulated.

pulses exhibiting a long collection time and consequently low amplitude at the filter output may be undetected. The main advantage of this filter in its physical implementafilter is already present tion is given by the fact that the in the setup as the first digital stage of the main energy filter. Therefore, it can be implemented with very limited hardware resources.

B. Stage 2 Stage 2 tries to overcome some of the drawbacks of Stage 1 by introducing some low-pass action in its WF. To this purpose, , i.e., the same filter Stage 2 is the cascade of a filter of Stage 1 followed by a low-pass frequency filter, and a logic section. In our implementation, the low-pass frequency filter is a simple four-sample rectangular filter. The motivation of such

3318

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 6, DECEMBER 2002

1

Fig. 5. Capability of Stage 1 of resolving piled-up events, as a function of relative amplitudes A and A and of temporal separation t. Three areas are defined by the probability P of correctly resolving pulses by Stage 1. Referring to the experimental setup of Fig. 1, the time constant of the shaper poles is set at 330 ns and the sampling frequency at 10 MHz. The presented results are simulated.

Fig. 7. Resource saving implementation of a rectangular filter of length equal to N samples.

C. Stage 3

() ()

Fig. 6. Same data simulated in Fig. 3 but with the filter h n replaced by the filter h n . It is evident that at the output of the h n filter, the pulse amplitudes are no more sensitive to the charge-collecting time into the detector. Depicted waveforms are simulated.

()

choice is that, sampling at 10 MHz and supposing 400-ns maximum charge-collection time (the case of a quasi-coaxial HPGe gamma-ray detector), such a filter will not suffer ballistic deficit and thus will not attenuate the amplitude of the output pulses (see Fig. 6) (10) with (11) filter is fed to a discrimAs in Stage 1, the output of the inator that generates a signal of “event detected” on the basis of output. The zero at a threshold crossing check over the lowers the contrithe Nyquist frequency introduced by rect bution of high-frequency noise. Therefore, this threshold can be set at a lower level than that of Stage 1. Of course, the increase of the WF duration introduced by the rectangular filter implies that this filter is more prone to trigger only once if two really close events happen to be detected. A schematic representation of the structure of Stage 2 is shown in Fig. 4(b).

Stage 3 is devoted to “reliability,” i.e., to detect events having energies as low as possible. To this purpose, the noise contribution should be minimized, which of course means that a filter conceptually similar to the main WF should be used. For the sake of simplicity and resource optimization while implementing the architecture in a programmable device [11], with a trapezoidal we have designed this low-pass filter shape. In fact, a digital trapezium of total length and flat top is the convolution of two rectangles of lengths of length round (12) As is well known, the rectangle is particularly suited to be implemented in programmable devices, as it involves elemental building blocks, i.e., summing nodes and digital integrators (see Fig. 7). The timing of the slow filter output performed by measuring a threshold crossing time is not suited to this case, since crossing times depend heavily on the amplitudes. This is the reason why is followed by a logic section that in Stage 3, the filter obtains the time position of the pulse from that of its top. Of course, implementing the equivalent of a constant fraction discriminator is still possible, but it turns out to be not necessary and more resource consuming than peak time detection. In this way, the capability to detect low-energy events, i.e., the main feature of this stage, is fully addressed: experimentally, we were able to trigger on 4-keV events when working on Co 1.17-MeV peaks. Also in this case, reasonably good timing is maintained: a mean error within two sampling intervals. On the

ODOARDO et al.: FULLY DIGITAL ARCHITECTURE

3319

Fig. 8. Flow chart of the “resolver” block, which synthesizes the output signal TRIGGER from the partial input signals “detected event” from each stage. For the sake of clarity of the plot, the signals “detected event” from stages have been named trigger1 at the output of Stage 1, trigger2 at the output of Stage 2, and trigger3 at the output of Stage 3. The resolver performs a hierarchical process that generates the output global trigger signal by giving priority to Stage 1 output over Stage 2 and Stage 3 outputs and priority to Stage 2 over Stage 3 output. This, in addition to the adopted criterion (see Section II-D) that distinct events are separated at least by two sampling intervals, leads to conditions 1 and 2 in the flow chart.

contrary, as expected, the capability of discriminating adjacent events turns out to be very poor. Fig. 4(c) shows the block diagram of Stage 3. D. Resolver The outputs of the three stages meet in a processing block called a resolver, which generates the trigger signal from its partial input information. The resolver architecture merges the output of the stages, i.e., “event detected,” with a priority criterion. First, output from Stage 1 is considered. Stage 2 and Stage 3 outputs are subsequently merged to Stage 1 output. The resolver considers distinct events detected by different stages if they are separated at least by two sampling intervals, which is a confident statistical upper limit of the maximum relative timing error of the three stages in experimental conditions. Figs. 8 and 9, respectively, show the flow chart of the resolver activity and the timing diagram of the combination of the outputs of the stages in order to build the final trigger signal. III. THRESHOLD CALIBRATION Even if all the digital blocks of the processor can be updated by the user, the only parts that need frequent calibration are the trigger thresholds of the stages. Unless the user specifies otherwise, the threshold values are set higher than the sum of the baseline BL and a multiple (three or four) of the root mean square value of the noise at the output of each filter Threshold

(13)

The baseline value, but in principle also the noise intensity, can change during operation. In order to allow threshold tracking, an iterative procedure has been implemented to update the threshold values every 10 ms. Initialization of these values

Fig. 9. The timing diagram shows an example of synthesis of the output signal TRIGGER from the status of the partial signals “detected event.” For the sake of clarity of the plot, the signals “detected event” from stages have been named trigger1 at the output of Stage 1, trigger2 at the output of Stage 2, and trigger3 at the output of Stage 3. The two sets of signals above highlight that the position of the event is set by the highest priority output of the parallel stages and that trigger pulses at distances lower than 2 T are referred to the same event.

1

is performed by a tracking mechanism that starts with very high thresholds. Then, by successive estimations of baseline and noise, the corresponding threshold values tend to the final value, obtained as mentioned above. The initialization procedure takes a few hundred milliseconds and is fully implemented into the same programmable device as the main architecture. Note that this architecture is easily adapted to different analog prefilters. In fact, in case of analog setup modification, the only filter. From this point of view, part to be updated is the filter is the general structure of the deconv

(14)

is the deconvolution filter of the shaped samwhere deconv is a suitable filter of shape indepled signal [see (6)] and pendent of the analog prefilter. IV. EXPERIMENTAL RESULTS A set of experiments has been performed to validate the trigger signal generator. The digital architecture has been implemented into a Xilinx XCV100 FPGA. To verify if closely spaced events are singularly resolved, synthetic signals were generated, which consisted of couples of pulses separated down to 200 ns, i.e., two sampling intervals. The corresponding waveshapes are shown in Fig. 10. It is clear from the lower trace that the filter corresponding to Stage 1 correctly resolves the two events. Fig. 11 shows an experiment aimed at verifying if the timing is correct in the case of pulses of different amplitude: a set of 500 pulses with a 1:100 amplitude spread (from less than 1% of dynamics to full scale) have been detected and superimposed in the figure. The single traces start at the trigger time of each event, as obtained by our circuit. The timing accuracy is more than sufficient for our purposes. Finally, we present in Fig. 12(a) and (b) a Co spectra obtained from our digital setup with analog [Fig. 12(a)] and digital

3320

IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 49, NO. 6, DECEMBER 2002

Fig. 10. Hardcopy of a digital sampling scope that is monitoring the signal at the input of the ADC (top) and the correspondent trigger signal at the output of the trigger (bottom). In the specific case, the signal is the superposition of two shaped events, which are separated in time by two sampling intervals (200 ns). The isoenergetic signals have peak values that are about 5% of the full-scale range (300 mV over FSR 5 V). The two pulses are resolved.

=

Fig. 11. Superposition of 500 experimental pulses at different energies (i.e., amplitudes). The corresponding trigger signal occurs at the same time for all pulses. The timing accuracy of the trigger circuit is clearly sufficient for correct operation of the spectrometer.

[Fig. 12(b)] trigger circuits. The digital trigger produces a much better spectrum at low energies, as clearly visible by comparing the insets of the two figures. V. CONCLUSION Analog spectroscopy setups employ analog trigger circuits, which filter the detector signal using a WF obtained as a compromise among different requirements. By substituting the analog circuitry with a digital one, such compromises can be relaxed, since it is possible to employ at the same time multiple filters with just a slight increase in circuit complexity. This allows extending the performance of triggers to cope for closely spaced events as well as for low-amplitude pulse detection. Properly employing adaptive procedures, the calibration of the thresholds of each stage can be made simple or even automatic. This result in lower skills required for the experimenter in order to trim the instrument to the particular measurement.

Fig. 12. (a) Spectrum of a Co source obtained by the pulse processor referred to in the text (analog shaping by three real coincident poles of time constant set at 330 ns and sampling frequency at 10 MHz). In this case, the trigger signal detecting incoming pulses is generated by analog circuitry. The source activity corresponds to 5 kpps of input rate, and the resolution of the 1.17-MeV peak is 1.87 keV. The analog trigger detects pulses of energy down to 50 keV. (b) Same experimental conditions but with the digital trigger circuit. The spectra have been collected simultaneously. By comparing the two insets showing the low-energy regions of the spectra, an improvement of an order of magnitude in the minimum detectable event energy (about 5 keV) can be observed. The significant increase in counts at low energies is due to noise counts. With a lower trigger threshold, also the analog energy spectrum would exhibit the same increase.

The digital trigger is built in a stand-alone module that can be fully implemented into a programmable device. In particular, the structure has been designed to be technology independent and to allow easy modification and migration toward different digital pulse processors. Further improvement in trigger circuits can be foreseen: now that digital circuits are fast, cheap, and easily available, optimum filters—a bench of them—can be used.

ODOARDO et al.: FULLY DIGITAL ARCHITECTURE

ACKNOWLEDGMENT The authors would like to thank Prof. E. Gatti and Dr. S. Riboldi for interesting discussions. REFERENCES [1] G. Ripamonti, A. Pullia, and A. Geraci, “Digital vs. analogue spectroscopy: A comparative analysis,” in Proc. IEEE Instrumentation and Measurement Technology Conf. (IMTC/98), vol. 1, St. Paul, MN, May 18–21, 1998, pp. 666–669. [2] A. Geraci, G. Ripamonti, and A. Pullia, “An automatic initialization procedure for real-time digital radiation spectrometry,” Nucl. Instrum. Methods, vol. A403, pp. 455–464, 1998. [3] E. Gatti, A. Geraci, and G. Ripamonti, “Automatic synthesis of optimum filters with arbitrary constraints and noises: A new method,” Nucl. Instrum. Methods, vol. A381, pp. 117–127, 1996. [4] A. Geraci, “Asymmetrical optimum filters for charge measurements in presence of 1=f current noise,” Nucl. Instrum. Methods, vol. A386, pp. 487–491, 1997. [5] E. Gatti, A. Geraci, and G. Ripamonti, “Lorentzian noise spectral density: Optimum filter,” Nucl. Instrum. Methods, vol. A385, pp. 561–562, 1997. , “Optimum filter for 1=f current noise smoothed-to-white at low [6] frequency,” Nucl. Instrum. Methods, vol. A394, pp. 268–270, 1997. , “Optimum time-limited filters for input signals of arbitrary [7] shape,” Nucl. Instrum. Methods, vol. A395, pp. 226–230, 1997. , “Optimum filters for experimentally measured noise in high res[8] olution nuclear spectroscopy,” Nucl. Instrum. Methods, vol. 417, pp. 131–136, 1998. [9] A. Castoldi, E. Gatti, A. Geraci, C. Guazzoni, and A. Longoni, “Nondestructive repetitive readout in high resolution silicon detectors,” IEEE Trans. Nucl. Sci., vol. 47, pp. 1346–1352, Aug. 2000.

3321

[10] E. Gatti, A. Geraci, and G. Ripamonti, “Timing of pulses of any shape with arbitrary constraints and noises: Optimum filters synthesis method,” Nucl. Instrum. Methods, vol. A457, pp. 347–355, 2001. [11] A. Geraci, A. Di Odoardo, S. Riboldi, and G. Ripamonti, “Adaptive digital spectroscopy in programmable logic,” IEEE Trans. Nucl. Sci., vol. 476, pp. 2765–2772, Dec. 2000. [12] A. Georgiev and W. Gast, “Digital pulse processing in high resolution, high throughput gamma-ray spectroscopy,” IEEE Trans. Nucl. Sci., vol. 40, pp. 534–536, Aug. 1993. [13] A. Georgiev, W. Gast, and R. M. Lieder, “An analog-to-digital conversion based on a moving window deconvolution,” IEEE Trans. Nucl. Sci., vol. 41, pp. 1116–1124, Aug. 1994. [14] V. T. Jordanov and G. F. Knoll, “Digital pulse processor using a moving average technique,” IEEE Trans. Nucl. Sci., vol. 40, pp. 764–769, Aug. 1993. , “Digital pulse shape analyzer based on fast sampling of an inte[15] grated charge pulse,” IEEE Trans. Nucl. Sci., vol. 42, pp. 683–687, Aug. 1995. [16] T. Lakatos, “Adaptive digital signal processing for x-ray spectrometry,” Nucl. Instrum. Methods, vol. B47, pp. 307–310, 1990. [17] M. Sampietro, G. Bertuccio, A. Geraci, and A. Fazzi, “A digital system for optimum resolution in X ray spectroscopy,” Rev. Sci. Instrum., vol. 66, pp. 975–981, Feb. 1995. [18] A. Geraci, M. Zambusi, and G. Ripamonti, “A comparative study of the energy resolution achievable with digital signal processors in X-ray spectroscopy,” IEEE Trans. Nucl. Sci., vol. 43, pp. 731–736, Apr. 1996. [19] A. Pullia, A. Geraci, and G. Ripamonti, “Quasioptimum and X spectroscopy based on real-time digital techniques,” Nucl. Instrum. Methods, vol. A439, pp. 378–384, 2000. [20] E. Gatti, G. Casati, A. Geraci, A. Pullia, and G. Ripamonti, “A pulseshape analysis approach to 3-D position determination in large-volume HPGe detectors,” in Proc. IEEE Nuclear Science Symp., vol. 1, Seattle, WA, Oct. 23–30, 1999, pp. 346–351.