A Functional Test Generation Technique for RTL Datapaths Bijan Alizadeh School of Electrical and Computer Engineering, College of Engineering, University of Tehran, Iran
Masahiro Fujita VLSI Design and Education Center (VDEC), University of Tokyo and CREST, Japan
[email protected]
[email protected] backtracking is needed to select another set of Boolean assignments. RTL ATPG algorithms in [4][5] are based on a data structure named Assignment Decision Diagram (ADD). In this method each element in the circuit is symbolically represented by ADD representation and then tested by justifying test vectors to their inputs from a primary input and propagating the responses from their outputs to a primary output. Although justification and propagation are done symbolically on ADD representation, it requires backtracking similar to most other ATPG methods. This can lead to an exponential increase in the complexity of the algorithm. So, the applicability of the algorithm to deep sequential circuits becomes crucial. Another testing technique that has been successfully used for software programs is fault-based testing which is also called mutant analysis [6]. It supposes that the program under test is correct. Then a set of mutant programs which are very similar to the program under test but are not equal, is generated. Each mutant program has a single change in its syntax to represent a programming error. After that, test patterns capable of provoking behavioral disturbance between the program under test and its mutants must be generated. This paper presents an ATPG technique applicable to RTL data-intensive circuits which are usually very hardto-test due to the presence of complex loop structures. Fig. 1 shows our proposed functional test generation methodology to obtain functional test patterns from RTL design. We have defined a fault model at behavioral level of abstraction which consists of two sorts of faults: (1) bit failure, (2) condition failure. As can be seen, a Finite State Machine with Datapath (FSMD) model [7] is synthesized which is then symbolically simulated to extract all execution paths. In order to reduce the size of formulae to be checked by SMT solvers, after injecting high level faults into the assignments or condition parts, case splitting is done. Finally, based on a canonical representation called Horner Expansion Diagram (HED) [8][9][10] functional test constraints are generated and then converted to real test patterns using SMT solvers. In summary, our contributions in this paper compared to [8][9][10] are as follows:
Abstract – This paper presents an automatic test pattern generation (ATPG) technique applicable to register transfer level (RTL) datapath circuits which are usually very hard-to-test due to the presence of complex loop structures. Although to achieve high fault coverage it is essential to symbolically simulate all possible execution paths, we have come up with a case splitting mechanism which makes use of path sensitization information from the faulty location to primary outputs so that the size of formulae to be solved is significantly reduced. Experimental results show robustness and reliability of our method compared to the state-of-the-art RTL ATPG techniques. In addition, the results indicate that, in comparison with [8], with case splitting the ATPG time has been reduced by 22%-41%.
I. INTRODUCTION As the complexity and size of modern embedded application is continuously increasing, designing hardware at higher levels of abstraction for faster design adjustments and higher simulation speed is necessary. Although system on a chip design flow is moving toward higher levels of abstraction, ATPG are still based on gate level techniques. On the other hand, it is obvious that scan-based techniques have the disadvantage that the test application time is very large compared to non-scan designs because the test vectors in such testing methodologies have to be shifted through the scan chains. Hence, a suitable non-scan high level ATPG technique is required to test manufacturing faults at the early stages of the design process. Several ATPG approaches have been proposed for detecting manufacturing faults. Some of them rely on Binary Decision Diagram (BDD)-based and satisfiability (SAT) tools [1][2]. Since both BDD and SAT-based methods require the design to be flattened into bit level, they cannot deal with large industrial benchmarks efficiently, either in terms of memory or run time. On the other hand, hybrid satisfiability approach (HSAT) [3] which generates functional test vectors for RTL designs, is applicable to the ATPG problem. However, if variable assignments that satisfy the Conjunctive Normal Form (CNF) clauses cause the linear programming constraints in the arithmetic domain to become infeasible,
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As an example, suppose the description in Fig. 3(a) is given where variable C in line 1 (else statement) has been affected by a fault, FAULT. Fig. 3(b) illustrates the HED representation of primary output D. It is interesting to see that const-child of variable FAULT indicates the fault-free behavior, while the linear-child represents required conditions for observing this fault at the output D. Let the variable ordering be FAULT>X>Y>Z>b1>b2. After writing symbolic value of D in terms of primary inputs as shown in (3), and replacing C from (4), we thereby obtain (5).
• Adjusting the decision procedure in [8][9] to split the cases in RTL datapath circuits which significantly reduce the size of formulae to be solved by SMT solvers. • Applying the proposed ATPG technique to dataintensive designs and showing its reliability and robustness in comparison with HTest [5] as a RTL ATPG program. The rest of this paper is organized as follows. Section II, describes the HED-based high level test generation technique in [11]. A polynomial model of sequential circuits as well as proposed ATPG methodology are discussed in Sections III and IV, respectively. Experimental setup and results and a brief conclusion are given in Sections V and VI, respectively.
RTL datapath circuit High Level Fault Injection
High-level Test Generation
Case Splitting
C = (X+Y)×b1 + (X×Y+FAULT)× (1-b1)
(4)
D = FAULT× (TP) + FFB
(5)
TP = Z[(1-b1)b2]+(1-b1)(1-b2)
Using HED
HED-based test generation
(3)
In (5), TP and FFB stand for TestPattern and FaultFreeBehavior respectively and their equations are as follows:
FSMD Model
Symbolic Simulation
D = (C×Z)×b2 + (C-Z)× (1-b2)
FFB = X[Y(Z(1-b1)b2+(1-b1)(1-b2))+ Z×b1×b2+b1(1b2)]+ Y[Z×b1×b2+b1(1-b2)] - Z[1-b2]
Extract all execution paths Simplify execution paths
Const Portion
Linear Portion Test Pattern
Fault-independent Behavior
Figure 2. HED representation for test generation
Figure 1. Functional test generation for RTL datapath circuits.
II. HED-BASED HIGH LEVEL TEST GENERATION APPROACH
1 if (b1) 2 if (b2)
The HED is a canonical, ordered, normalized and reduced binary graph-based representation which supports polynomial functions by factorizing variables based on Horner form as shown in (1), where const is a term which is independent of variable X, while linear is another term which is served as the coefficient of variable X [12]. F(X,…) = const + X×linear
FAULT
C = X+Y; D = C*Z;
else else
C = X*Y + FAULT; D = C-Z;
(a) D FAULT
X Y
(1)
Z
Since each polynomial function in the HED is decomposed based on Horner form as shown in (1), the linear part indicates under what conditions the function will be dependent to the related variable. Now suppose the top variable is a faulty variable (FAULT) as shown in Fig. 2, so the linear portion expresses conditions caused the FAULT variable to be observed at the output while the const part is equivalent to the fault-independent behavior [11]. Indeed, the HED representation has an inherent property of automatically separating faultindependent behavior from the faulty part of a faulty design.
Test Pattern
Y
Z
Z
-1 b1
b1
b1
b1
-1 b2
-1
b2
b2
-1 b2
-1 1 (b) Figure 3. (a) A simple behavioral code, (b) HED-based test generation
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In order to detect FAULT on D output, TP should not be zero. In other words, the TP indicates that the injected fault can be tested if ((1-b1)≠0 & b2≠0 & Z≠0) or ((1b1)≠0 & (1-b2)≠0) is satisfied. Otherwise TP becomes zero and therefore that fault will be undetectable.
( 0 ≤ m ≤ n − 1 and m ≠ k ), then (PS-2m) term in (6) becomes zero which results Pn(PS,k)=0.
III. POLYNOMIAL MODEL FOR SEQUENTIAL CIRCUITS
According to this definition, the transition function TRANS(PS, I) as well as output function OUT(PS, I) are expressed in a summation of polynomial functions as equated in (7), where fns(PS, I, k): S×I×AR→U and fout(PS, I, k): S×I×AR→U show operations in each state of the FSMD to generate next state and output functions, respectively.
n −1
PS ≡ S k :
P n ( PS , k ) =
∏ ( PS − 2 i=0 n −1
∏ (2
k
i
) where i ≠ k
(6)
− 2i )
i=0
In this section, we introduce a formal model which describes sequential circuits as a set of polynomial functions so that our HED-based functional test generation technique, discussed in Section II, can be applied to RTL datapath circuits. Although data path components can be directly represented in HED, control behavior needs to be taken into account as a word level transition relation in HED. Polynomial Model of a sequential circuit is a set of algebraic functions that describe a given circuit based on a Finite State Machine with Datapath (FSMD) model. The FSMD is formally defined by a universal specification model, proposed in [7], that can represent all hardware designs.
n −1
TRANS ( PS , I ) = ∑ P n ( PS , k ) × fns ( PS , I , k )
(7)
k =0
n −1
OUT ( PS , I ) = ∑ P n ( PS , k ) × fout ( PS , I , k ) k =0
Definition 3 (execution path: ExePath): An execution path is defined as a sequence of transitions s0→s1→…→sn where s0∈InitS, for all i, si∈S, si→si+1 is a valid transition according to the transition function TRANS, and sn is a state in which at least one of primary outputs is updated according to the output function OUT.
Definition 1: The FSMD is defined as a 7-tuple M = (InitS, I, S, V, Z, TRANS, OUT), where 1) InitS is the initial state 2) I is the set of primary input signals 3) S is the finite set of control states 4) V is the set of storage variables 5) Z is the set of primary output signals 6) TRANS: S×AR → S, is the state transition function 7) OUT: S×AR → U, is the update function of the output and the storage variables, where AR and U are defined below: (a) U = {x ⇐ e | x ∈ Z ∪ V and e ∈ E} represents a set of storage or output assignments and E = {g(x, y, z, …) | x, y, z, … ∈ I ∪ V} represents a set of arithmetic expressions over the set I ∪ V of input and storage variables. (b) AR = {R (a, b)| a, b ∈ E and R is any arithmetic relation} represents a set of status signals as arithmetic relations between two expressions from the set E.
Definition 4 (transition condition: TransCondi→j): Suppose a valid transition si→sj is given. A set of relational expressions (∈AR) that cause a transition from si to sj, are defined as the transition condition and denoted by TransCondi→j. Definition 5 (execution-path assumptions: PathAsm(ExePath)): For a given execution path, ExePath: s0→s1→…→sn, all transition conditions TransCondi→i+1 where i=0 to n-1, are considered as execution-path assumptions and denoted by PathAsm(ExePath). Definition 6 (assignments associated with a transition: Assigni→j): Suppose a valid transition si→sj is given. A set of assignments (∈U) associated with the given transition is denoted by Assigni→j. Note that the left hand side of an assignment must be a variable, while the right hand side of the assignment can be a simple or conditional expression.
In order to describe an FSMD with a set of polynomial functions, TRANS and OUT functions should be expressed based on a set of polynomial functions. For this purpose, each Sk ∈ S is encoded by a polynomial Pn(PS,k) which is defined as follows:
Definition 7 (assignments associated with an execution path AllAssigns(ExePath)): For a given execution path, ExePath: s0→s1→…→sn, all assignments Assigni→i+1 where i=0 to n-1, are denoted by AllAssigns(ExePath). In other words, for a given execution path, the design can be modeled by a sequence of assignments. As an example, let us consider the FSMD illustrated in Fig. 4. To describe the transition function TRANS, and output function OUT, in terms of the present state PS,
Definition 2 (state condition): Consider an FSMD which has n states S = (S0, S1, …, Sn-1). If one-hot encoding is used, each present state PS ≡ Sk ∈ S ( ) can be described as a polynomial Pn(PS,k) in (3). In other words, after replacing PS in (3) by 2k, Pn(PS,k) is computed as 1 and therefore we say that Pn(PS,k) represents the present If PS is replaced by 2m state S k.
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and primary input I, each state is encoded based on an initial state. In this example, Sinit as initial state, is encoded by 1 (001), and Scnt and Sfin are encoded as 2 (010) and 4 (100), respectively. Based on Definition 2, the present states 1, 2 and 4 are described as shown in (8). Furthermore, TRANS and OUT functions are computed as illustrated in (9) and (10) respectively. Note that, in (9), according to each present state defined by P3(PS,k), it is only necessary to determine the appropriate next state value. For example, the second term in (9), i.e. P3(PS,1)×[C1×4+C2×2], indicates that if the FSMD is in state Scnt (encoded by 2), the next state depends on C1 and C2. If C1=1, i.e. i==2, then Scnt has a transition to Sfin (encoded by 4). If C2=1, i.e. i
