A High-Speed Memory Interface Circuit Tolerant to PVT Variations and Channel Noise Joon-Young Park, Yido Koo, Deog-Kyoon Jeong, Wonchan Kim, Changsik Yoo*, Changhyun Kim* Seoul National University, Seoul, Korea * Memory Division, Samsung Electronics Co., Kiheung, Korea
[email protected] Abstract A high-speed I/O circuit for the memory interface is implemented in a 0.25µm CMOS technology. To increase the sensitivity of the input circuit, the receiver employs the positive feedback. For driving of signal with the proper slew rate and specified voltage level under PVT variations, the pro-posed output circuit includes the novel level detection circuit and slew rate control scheme.
proposes a high-speed I/O interface circuit which improves the data sampling and driving capability under noisy channel and PVT variation.
1. Introduction The speed of modern microprocessor continues to increase dramatically, which causes the bandwidth of memory I/O to be a limiting factor in overall system performance. Various high-speed DRAM architectures have been previously reported[1][2], and most of them employ a limited-swing signalling, large bus width. Figure 1 shows the Rambus memory system[1], one of the commercial high-speed memory architectures. Through a data bus, the limited-swing signal that has 0.8V swing and 1.4V common mode voltage is transferred between a single master(controller) and slaves. The common mode voltage is determined by the reference voltage supplied from the external source, and a master and all slave chips are connected to the same reference line. Therefore, reference voltage has large fluctuation during data transfer due to the signal feedthrough from the interface circuit of the master and slave chips. Because a receiver compares a data signal with a reference signal, reference fluctuation reduces the voltage margin of a receiver. In an output driver circuitry, the control of output swing level is important to guarantee a timing and voltage margin at the receiver and reduces the needless power consumption regardless of process, voltage and temperature variation. In addition, the inductive overshoot or undershoot of data signal not only reduces an I/O timing margin but generates ground bouncing which disrupts a data read at a receiver. The slew rate should be determined by considering the fluctuation at data bus and the voltage margin at the receiver regardless of PVT variation. This paper
Figure 1. Rambus memory system architecture.
2. Receiver circuit Generally a receiver is made up of a simple latch. In previous work[3], an emitter-coupled logic amplifier stage is added in front of a latch to convert input signals to differential signal. Because the amplifier must operate in high speed, bandwidth should be wide. Therefore, the amplifier has unity gain. In this case, the voltage margin of receiver depends only on that of a flip-flop. To increase voltage margin, the proposed circuit employs a positive feedback transistors at the amplifier. Figure 2 shows the proposed circuit.
Figure 2. Input receiver circuit.
The transistors in the shaded box make a feedback path. Through the positive feedback, the difference between reference and data signal becomes larger at the amplifier output. This results in the increase of voltage margin. If these transistors are larger than main transistors, the bandwidth of an amplifier decreases to causes the mal-operation of a receiver. Therefore, the size of feedback transistors must be determined with the consideration of trade-off between bandwidth and voltage-margin.
In this scheme, Voh and Vol are stored in each capacitor. Then, Vm, the average of Voh and Vol, is compared with Vref. Like the previous work, the current level is controlled to make Vol to 2Vref-Voh by the control signals from controller.
CV oh + CV ol = 2CV m V m − V ref =
Voh + Vol − V ref 2
3. Output driver architecture Generally, a high-speed I/O interface employs an open-drain type output driver. To control the output current level to have the proper output signal voltage level and slew rate, an output driver architecture consists of level detection block, data slew rate control block, process variation detection block, and nMOS array block.
3.1 Level detection circuit The level detection circuit makes the common mode of output signals to be the reference voltage. In the previous work[4], level detection is achieved with resistive voltage divider. However, there is the mismatch of poly resistors for voltage division and the offset errors of a comparator. In addition, the resistance of switch influences the output swing level in receiver part. These factors changes the common voltage detected and cause the detection error.
Figure 4. Voltage divider offset with PVT variation. Generally, capacitor variation is smaller than that of the resistor. So the level detection error from the resistor mismatch can be reduced by using the capacitors as a voltage divider. Moreover, the parasitic resistor of nMOS transistors for switching has little effect on voltage division because output voltage is only transferred to capacitors through switch. Figure 4 is the simulation result of voltage divider offset under PVT variation. The offset variation of capacitive division method is 41% smaller than that of resistive division method. In addition, with these capacitors, the offset cancellation circuit for a comparator can be easily implemented as shown in Figure 3(b). The comparator is in offset cancellation state during voltage sampling state and after offset cancellation operation, comparison begins. Symmetric switch design in both sides of comparator minimizes the clock feed-through and charge injection in switching operation.
3.2 Output driver
Figure 3. Proposed level detection circuit: (a) Capacitive voltage division. (b) Offset cancellation circuit. As shown in Figure 3(a), the proposed architecture uses capacitors as a voltage divider instead of resistors.
To obtain the uniform current level in an nMOS array, all transistors in the array have to operate in saturation region. However, the channel voltage level can be lower due to the continuous data transfer and reflection between master and slave. Therefore, transistors might operate in linear region. In this case, the current level is not constant any more. To avoid this situation, the ouput driver employs a current feedback[5]. In this circuit, additional transistors
monitor the output level to compensate the decreased current level due to the changed operation region of nMOS array transistors.
Figure 5. Proposed output driver tolerant to supply fluctuation. However, if there is a supply voltage fluctuation caused by noise or any other factors, this affects on the output driving current directly. To reduce this effect, an nMOS transistor, M7, is connected between Vdd and pMOS, M6, to monitor the output voltage level. Figure 5 shows the proposed circuit to reduce the effect of supply noise. In stead of pMOS at M7, nMOS is used to suppress a supply fluctuation. Figure 6 is the current level at output node under the supply voltage fluctuation. As shown in the figure, proposed circuit is less sensitive to a supply fluctuation.
detecting the process condition. To control the slew rate more precisely, the activation time of the predriver is also controlled in the proposed scheme. Figure 7 shows the proposed slew rate control scheme. In the figure, data signals are connected to L_buf(left buffer) and R_buf (right buffer) respectively. To control the slew rate by timing difference, L_buf and R_buf operate independently. Due to the different fanouts between L_buf and R_buf, the slew rates of each buffers are different. This difference makes the timing difference between the outputs of the left and right predrivers. Through this timing difference, the output slew rate is controlled. But the large difference between predrivers generates an output distortion. So the output current is distributed by the different capacitive loading of predrivers to reduce the distortion. In general, the process variation of pMOS and nMOS has the same tendency. From the information of buf_en signal, the state of nMOS process can be determined. Therefore, process detection can be easily achieved over the whole nMOSes size in the array. buf_en [6:0] 7
Vg 0 data
control block
nMOS array
7
buf6 Vg_en
buf5 60W
buf0
32W
W
predriver
predriver_en
Vg_en
16W
16W
L_buf[6:5] L_buf[4:0]
data
L_buf5
R_buf5
R_buf[6:5] R_buf[4:0]
Figure 7. Slew rate control scheme.
4. Measurement
Figure 6. Current level with supply voltage fluctuation.
3.3 Slew rate control scheme As the operation frequency increases, the effect of inductive overshoot or undershoot of data signal raises a serious problem to an I/O timing margin. Therefore, the slew rate of output signal needs to be controlled to be constant in various environments. In the previous work[3], the slew rate can be determined by the number of the active predrivers. The number is determined by
The test chip was fabricated in a 0.25um 1-poly, 5metal CMOS technology. Test results described were measured with the DLL operating at 400MHz. The chip microphotograph is shown in Figure 8. Figure 9 shows the output waveform of conventional and proposed input receiver. When the input signal is at the correct level, sampling data is clock waveform. But low level of incoming signal goes close to reference signal (Figure 9(a)), a conventional circuit cannot sample the low signal. Otherwise, when high level of incoming signal is close to reference signal(Figure 9(b)), high signal cannot be sampled in a conventional circuit. By controlling the input voltage level and reference voltage level, the voltage margin of the receiver is measured(Figure 10). The proposed circuit has the
increased input voltage margin by 17% than the conventional receiver. Output circuitry achieves an 800Mbps data rate. The output signal has 1.4V common mode voltage and 0.8V swing. The data eye is 670mV and 1.1ns. Signal reflection is found which is caused by termination mismatch of measuring instrument and various capacitive stubs on channel.
5. Conclusion The I/O circuitry for memory interface tolerant to PVT variations is presented in this paper. For more accurate signal generation, output circuits are designed to be immune to PVT variation and supply noise. This can be achieved by level detection and slew rate control having less mismatch errors. At the receiver side, voltage margin is improved by the positive feedback, and this makes possible a correct data sampling under noisy environment. With this I/O interface circuit, more robust data transfer is possible regardless of PVT variations and noisy environment.
Figure 8. Chip microphotograph.
6. References [1] Kevin S. Donnelly, et al., “A 660MB/s interface megacell portable circuit in 0.3-0.7um CMOS ASIC,” ISSCC Dig. Of Tech. Papers, pp. 290-291, Feb. 1996. [2] Yoshikazu Morooka, et al., “Source synchronization and timing vernier techniques for 1.2GB/s SLDRAM interface,” ISSCC Dig. Of Tech. Papers, pp. 160-161, Feb. 1998. [3] Benedict Lau, et al., “A 2.6-Gbyte/s multipurpose chip-to-chip interface,” ISSCC Dig. Of Tech. Papers, pp. 162-163, Feb. 1998. [4] Mathew Griffin, et al., “A Process Independent 800MB/s DRAM Byte wide Interface Featuring Command Interleaving and Concurrent Memory Operation,” ISSCC Dig. Of Tech Papers, pp.156-157, Feb. 1998. [5] Stefanos Sidiropoulos, et al., “Circuit design for a 2.2GB/s memory interface,” ISSCC Dig. Of Tech. Papers, pp. 70-71, Feb. 2001.
(a) (b) Figure 9. Receiver output waveform (upper traces are with conventional scheme and lower traces with the proposed scheme): (a) when Vol is close to Vref. (b) when Voh is close to Vref.
Figure 10. Measured voltage margin.
