Microprocessor-based System Design. Ricardo Gutierrez-Osuna. Wright State
University. 1. Lecture 15: Memory and I/O interface g Address space g Memory ...
email: {nikolov, stefanov, edd}@liacs.nl. ABSTRACT ..... by blocking write/read on these fifos. The External Data Memory Controller (EDM CTRL) is responsible.
nas habilidades de linguagem, o que deve ser levado em conta para reabilitação. PALAVRAS-CHAVE: .... examination). Demographic data are shown in Table 1; .... information recovery using common action sequences and it is sensitive to ...
Many-Core Platform with 3D stacked DRAM ... core computing platforms. .... IOs. To tackle it, the output impedance of the drivers must be matched with the ...
They have the option of stepping. 1 Android - http://www.android.com. 334 .... the image of plumping a pillow on the mobile interface, he/she could replicate the ...
Sep 21, 2010 - Xilinx does not assume any liability arising out of the application or use ... The Design is not designed or intended for use in the development of ...
We show it's application to the parallelization of a sparse matrix computation. Keywords: parallel programming interface, shared memory parallelization, NUMA ...
Figure 1 shows the Rambus memory system[1], one of the commercial high-speed memory architectures. Through a data bus, the limited-swing signal that has.
Sep 21, 2010 - Xilinx does not assume any liability arising out of the application or use of the Design; ...... Batch mo
VIA(sockets, MPI) have been announced[24]. In this paper, we ..... cessor which is available on most UNIX systems. ... Page fault - When the application tries to ... Get the ID assigned to this thread by the DSM system .... mprotect system call, and
This course teaches hardware designers who are new to high-speed memory I/O
... introduces designers to the basic concepts of high-speed memory I/O design ...
address space of remote memory without inter- mediate copies, VIA appears to offer adequate communication support for software DSM. To our best knowledge ...
Abstract. In this paper we present a new programming environ- ment for distributed memory parallel computers con- sisting of a Fortran 77 compiler enhanced ...
Keywords: parallel programming interface, shared memory parallelization, NUMA ... machines scale to a higher degree of parallelism than traditional bus-based ...
to achieve minimal software message passing overhead, ... virtual memory mapping in software [5]. ... mapped memory as send and receive bu ers, and can.
Testing High Speed Memory Interface: A case for FPGA based Test systems ?
Mathieu Duprez. MuTest. [email protected]. OSCILLOSCOPE.
Sep 7, 2010 - The IEEE 1394 interface is a serial expansion bus found on many personal computers. ...... URL http://citp
This wide selection of SATO modular interfaces enables your SATO Printer ...
Interfaces. Centronics Parallel. For all SATO printers that support plug-in
interfaces.
rate in iterative solution of the large, coupled nonlinear equation system involved. ..... class of problems, where it is more effective to use an interface-tracking technique to .... We propose to accomplish this by adopting Eq. (12) for use in the
S. Joslyn, Box 351525, Department of Psychology, University of Wash- ington ... with the correct answer and tested again, the participants' performance improved somewhat, espe- ... These pioneering studies imply that memory for mem- ... We will focus
Memory is any indication that learning has persisted over time. It is our ... Alan
Baddeley (2002) proposes that working memory contains auditory and visual ...
This coursework is developed in the open on GitHub, at www.github.com/CodeClub. Come and join us! Activity Checklist. Te
Memory class12.ppt ... Nonvolatile memories retain value even if powered off.
Read-only memory (ROM): ... Smart cards, embedded systems, appliances.
chip. 11 Address bits. A10-A0. 9 to 1. Decoder. CS/. BA0-19. 9 Selector bits .... Example 9: Interfacing EEPROM ... The
Memory Interface CEN433 King Saud University Dr. Mohammed Amer Arafah
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Address Decoding n
n
When interfaced to a microprocessor with 20 address signals there is a mismatch.
n
The extra 9 address pins (A11-A19) are decoded using a decoder such that they select the memory device for a unique position in the memory map of the processor.
n
n
BA0-19
19
11
10
0
Memory chip A10-A0
For example, the 2716 is 2 K x 8 memory device has 11 (= 1 + 10) address inputs (A0-A10).
n
LS (11 bits)
MS (9 bits)
Memory devices interfaced are usually of smaller storage capacity than the full address space of the processor
11 Address bits
9 Selector bits
9 to 1 Decoder
FFFFFH 511 MS (9 bits)
LS (11 bits)
.. .
00FFFH
Decoding A11-A19 and using them for selecting the memory chip fixes the position of the memory locations in the mP address map
High Memory (ROM)
510
000000001 xxxxxxxxxxx
Here the mP address space is 29 times the size of the memory chip
CS/
00800H
211 = 1 2048
00000H 0
29 = 512 times
Low Memory (RAM)
mP Memory Map CEN433 - King Saud University
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Example 1: Exhaustive Address Decoding (Simple NAND Gate Decoder)
Memory locations:FF800H-FFFFFH CEN433 - King Saud University
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Example 2: Exhaustive Address Decoding
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Example 3: Exhaustive Address Decoding (Simple NAND Gate Decoder) n
32 K x 8 memory device: 15 bit address: 215 locations
U2A BA19
n
Selector address: 20 – 15 = 5 bits
n
If we want the memory locations to start at 10000H, What is the selector address to decode?:
Memory locations:F0000H-FFFFFH CEN433 - King Saud University
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Example 5: Exhaustive Address Decoding (74LS138) 64 KB EPROM Starting at F0000H Answer: à F0000 – FFFFFH. à BA0-BA15: Location Addressing. à BA16-BA19: Space Addressing.
BA16 BA17
1 U1A 2
BA18 BA19
4 5
6
CS/
74LS20
Assume that 64 KB EPROM is not found! We can replace it with 8 of 8KB EPROM. Starting address is F0000H. Answer: à BA16-BA19: Space Addressing. à 8KB EPROM
U2
BA16 BA17
1 U1A 2
BA18 BA19
4 5
BA13 BA14 BA15 6
1 2 3 6 4 5
A B C G1 G2A G2B
15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 7 Y7
CS0/ CS1/ CS2/ CS3/ CS4/ CS5/ CS6/ CS7/
74LS20
à
à
BA0-BA12: Location Addressing
74LS138
BA13-BA15: 8KB Module Addressing
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Example 6: Exhaustive Address Decoding (74LS139) 64 KB EPROM Starting at F0000H Answer: à F0000 – FFFFFH. à BA0-BA15: Location Addressing. à BA16-BA19: Space Addressing.
à
1 U1A 2
BA18 BA19
4 5
6
CS/
74LS20
Assume that 64 KB EPROM is not found! We can replace it with 4 of 16KB EPROM. Starting address is F0000H. Answer: à BA16-BA19: Space Addressing. à 16KB EPROM à
BA16 BA17
U2A BA16 BA17
1 U1A 2
BA18 BA19
4 5
BA14 BA15 6
2 3 1
A B G
4 Y0 5 Y1 6 Y2 7 Y3
CS0/ CS1/ CS2/ CS3/
74LS139 74LS20
BA0-BA13: Location Addressing
BA14-BA15: 8KB Module Addressing
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Exhaustive Address Decoding (PLD Decoders ) n
Many modern systems use programmable logic decoders in place of integrated decoders
n
They give total freedom in decoding different addresses for individual memory devices
n
Programmable logic devices have may be called: ¨ ¨ ¨ ¨ ¨ ¨
They are all programmable logic devices. Nowadays they can be programmed using VHDL (Verilog Hardware Definition Language)
n
Some types are programmed only once (fused links), similar to PROMs Some types are erasable like EPROMs
n n
The next slide shows one of the most common low cost devices: the PAL16L8
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PAL16LR
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PAL16LR
xx
yy
zz
xyz xyz x x x x x
F = (xyz)+(xyz)
x
y
z
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Example 7: Exhaustive Decoding
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Example 7: Exhaustive Decoding library ieee; use ieee.std_logic_1164.all; entity DECODER_10_17 is port ( BA19, BA18, BA17: in STD_LOGIC; Input declaration ROMCS/, RAMCS/ : out STD_LOGIC; output declaration ); end; architecture V1 of DECODER_10_17 is begin ROMCS/