A low power 10 Gbps voltage mode output driver with

2008 International Conference on Microelectronics

A Low Power 10 Gbps Voltage Mode Output Driver with Good Return Loss Performance Khaldoon Abugharbieh1,2, Shoba Krishnan2, Jitendra Mohan1, Devnath Varadarajan1 1

National Semiconductor Corporation, Santa Clara, CA 95051, USA 2 Santa Clara University, Santa Clara, CA, 95053 USA voltage swing, the driver needs to supply a load current, I_load, to Rload in the block diagram below. Both the predriver and the output stage consume current. Very often the pre-driver consumes a large amount of power to switch the output stage. Equation (2) describes the current breakdown in the driver.

Abstract-This paper describes a new topology and implementation of a 10 Gbps voltage mode output driver designed for high speed data transfer applications. Using a positive feedback technique, the low power driver achieves the proper internal chip impedance required for matching the line impedance. As a result, return loss is minimized and good signal integrity is achieved. The driver, which consists of a pre-driver and an output stage, consumes a total of 17mW at speed power and S22 return loss performance better than 15dB. It provides a single ended output swing of 400mV. In measurements, the driver, which was a part of an equalizer chip, achieved peak to peak jitter of 11psec at 10Gbps. The chip is fabricated in a standard 2.5V/1.2V SiGe BiCMOS technology with 100 GHz peak ft, and packaged in a commercial LLP package.

I _ driver = I _ predriver + I _ outputstag e + I _ load

(2)

Keywords: low voltage differential signaling, output drivers, low power, impedance matching, return loss Fig 2. Driver block diagram and current breakdown.

I. INTRODUCTION

II. TYPICAL TRANSMIT DRIVER TOPOLOGIES

Point to point data transfer systems consist of a transmit driver, a receiver and the transmission line as shown in figure 1.

Transmit drivers can be current or voltage mode drivers. Figure 3 shows a typical current mode (CML) driver[1]. The bipolar differential pair devices are used as switches that switch current from one leg of the output stage to the other. The internal 50 ohms resistors provide the proper matching to the transmission line and result in good return loss performance. However, this results in the output stage burning four times the load current to generate a swing = 100*I_load. In addition, the bipolar transistors in the output stage present a large base to emitter capacitance to the predriver, not shown in figure 3. Therefore, the pre-drivers which are likely to be emitter followers have to burn a lot of current to fully switch the output stage bipolar devices. In general, current mode drivers achieve low return loss at the expense of high power consumption.

Zo TX

RX Zrx

Ztx

Zo

Fig 1. Point to point data transfer system. Achieving low power operation and maintaining signal integrity are two key challenges in transmit driver design. To maintain minimal return loss, good signal integrity and minimize reflections, the driver needs to provide internal impedance that matches the transmission line impedance, Zo. Ideally, both the transmit driver and the receiver should have differential internal termination = 2*Zo, 100 ohms in most data transfer applications. Equation 1 describes the return loss (RL) performance of a transmit driver. Ztx should equal 2*Zo for best performance. RL ( dB ) = − 20 * log(

| ( 2 * Zo ) − Ztx | ) ( 2 * Zo ) + Ztx

(1)

A transmit driver consists of an output stage and a predriver as shown in figure 2. To generate the proper output

1-4244-2370-5/08/$20.00 ©2008 IEEE

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I_load flows to generate the desired output signal swing. In most data transfer applications, R_load would be the termination impedance of the receiver. The following three sections will detail the operation of the new topology.

VDD - Supply

50 ohms

I_load 3*I_load

50 ohms

out

VDD_Supply I_load

100 ohms

PreDriver

outb inb

4*I_load

Rp

Output Stage

Ip

Rp

in

Q4

2*VOD

out = VDD – 50*I_load outb = VDD – 50 *3*I_load VOD = out – outb = 2*I_load*50 VOD = 100*I_load

Q3

b

a Rterm

inb

Q1

Q2

Fig 3. CML mode driver output stage (pre-driver not shown)

Rterm

in

I_leak out

outb b

M5

Rload

M6

a

Ip

Figure 4 shows a typical voltage mode driver. The NMOS and PMOS transistors are operated as low impedance switches. They are sized so that their impedances are very small compared to the 50 ohms linear resistors in series with them. This provides ~ 100 ohms differential internal chip termination which matches the line impedance. As a result, the linear resistors act as a voltage divider where the output swing is half the difference between Vhigh and Vlow. While the output stage only needs to consume I_load. One major drawback of this topology is that the NMOS and PMOS transistors are very large sizes to achieve low impedance. As a result, the predriver, not shown in figure 4, will burn a lot of current to drive the gate capacitance of the switches. Further, when the inputs are switching, all four FETs can transiently be turned on. This causes undesirable shoot-through current and often results in line impedance mismatch and increased signal reflection. This has an adverse effect on the quality of the eye-diagram.

I_load

Fig 5. New voltage mode driver topology (pre-driver included) A. Driver output signal swing - VOD The output stage consists of emitter followers, termination resistors, and two NMOS devices that switch the load current from one leg to the other. The outputs of the emitter followers (a and b) are used to switch the gates of the NMOS transistors (M5 and M6). This is a positive feed back technique that saves power, because no extra circuitry is needed to switch the NMOS transistors. Further, the load current, I_load, is used by either Q3 or Q4 depending on the pre-driver output. So, no extra current is needed to load the emitter followers. As a result, the output stage current consumption is very comparable to I_load. The output stage acts as a voltage divider. Assuming that Q3 and Q4 are ideal emitter followers, Rterm=50 ohms, and Rload = 100 ohms, the differential output voltage is half the pre-driver swing. The pre-driver swing is Rp*Ip. The pre-driver load is Rp in parallel with the input impedance of emitter followers, Zin_Q3_Q4. Because Q3 and Q4 are emitter followers, Zin_Q3_Q4 >> Rp. As a result, the pre-driver load impedance is dominated by Rp. This is a major advantage over the previous topologies where the pre-driver needs to burn a considerable amount of power to directly drive the highly capacitive switches of the output stage. Figure 6 shows a half circuit model for Vout = VOD/2.

Fig4. Typical output stage of voltage mode driver (predriver not shown) The new proposed topology improves on the drawbacks of the previous topologies by offering good return loss performance at low power consumption. III. NEW CIRCUIT TOPOLOGY

Fig 6. Simplified half circuit model for VOD/2.

Figure 5 shows a schematic of the proposed driver. The Rload, 100 ohms, resistor is an external resistor where

The half circuit pre-driver swing is modeled as a voltage source with amplitude = (Ip*Rp)/2. The non-idealities

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related to the emitter follower (1/gm3 and Rp/β) are also included. Equation (3) describes the single ended output voltage as function of Rload and other circuit elements.

Rload Rp * Ip *( ) VOD 2 2 Vout = = Rload 1 Rp 2 + Rterm + + 2 gm 3 β

other. As a result, the output impedance of Q3 or Q4 (1/gm4 and Rp/β) would be very high and can have an adverse effect on the chip termination. A small leakage or keep alive current, I_leak, is added to the output stage. Its purpose is to insure that both Q3 and Q4 are always on during operation[2]. For example, if Q3 is passing a high signal and is supplying the full load current, Q4 would still burn a small keep alive current. As a result, the output impedance of Q4 (1/gm4 and Rp/β) does not go to a high value which helps maintain good signal integrity. The keep alive current value is very small when compared to the load current, so its effect on power consumption is not significant. Results show that increasing the value of the keep alive current would improve return loss performance at low frequencies. At high frequencies increasing the keep alive current does not add much value because Q3 and Q4 don’t fully switch off.

(3)

B. Achieving matched internal termination Figure 7 shows how the chip internal termination can be matched to the transmission line impedance. The emitter follower parasitic impedance, Rterm, and the NMOS transistor effects are included in the small signal model. The NMOS transistor, M6, is modeled as a voltage controlled current source. If it’s kept in saturation, its output impedance, ro6, is high enough (~ few hundred Kilo ohms) that its effect on internal chip termination is negligible. Also, the small signal current of M6 is dependent on the small signal component of the voltage at node a, va. Equation (4) shows that the output impedance is dominated by Rterm, 50ohms, if gm6