A LOW-POWER EFFICIENT DIRECT DIGITAL FREQUENCY SYNTHESIZER
BASED ON NEW TWO-LEVEL LOOKUP TABLE Kun-Tse Lee Jin-Jia Chen Chien-Hung Lin Shu-Chung Yi Department of Department ofElectrical Department ofElectrical Graduate Institute of Engineering, NCUE Electrical Engineering, Engineering, NCUE Integrated Circuit Design, NCUE Changhua, Taiwan Changhua, Taiwan 500, Changhua, Taiwan 500, NCUE Changhua, ROC ROC Taiwan 500, ROC 500, ROC email:
[email protected] Abstract This work presents a low power direct digitalfrequency synthesizer (DDFS) by using a new two-level lookup table algorithm. The algorithm uses trigonometric double angle formula to divide ROM lookup table into two parts. The ROM size of the proposed architecture is 25% less than that of conventional two-level table. The hardware complexity of the new DDFS architecture compared to the traditional two-level table DDFS can be omitted one multiplier. A synthesized 0.35-pm DDFS with a SFDR of 80dB, runs up to 100MHz and consumes 81-mW at 3.0v. The power efficiency is 0.81-m W/MHz, which represents an enhancement of more than 38% compared to the conventional DDFS.
Keywords. DDFS, Synthesizer.
Low power,
VLSI,
The ROM size of DDFS increases exponentially by the input bits of sine/cosine lookup table. It is generally considered that the ROM causes both power and performance drawbacks in DDFS design. Recent researches of DDFS are focused mainly on reducing the power consumption to meet portable communication system.
Frequency
INTRODUCTION
Figure 1 Conventional architecture of the ROM-based DDFS
Direct digital frequency synthesizer (DDFS) is an important device for wireless communication systems. DDFS is very much preferred in some modern communication system owing to their advantages, e.g., fast switching, fine frequency resolution, low phase noise, continuous-phase frequency switching.
The other architecture of DDFS replaces the lookup table ROM with non-linear digital to analog converter (DAC). This type of DDFS is usually called ROM-less DDFS [6]. The ROM-less DDFS consumes less power and chip area than the ROM-based DDFS. But the mixed-signal design often causes low-SFDR and high-phase noise. The nonlinear DAC also requires much more design time owing to full custom design procedure. If the technology of foundry is upgraded, it must consume extra time to design a new non-linear DAC to meet product specifications.
Most DDFS architecture can be divided into two types, i.e., ROM-based DDFS and ROM-less DDFS. The conventional architecture of ROM-based DDFS usually consists of a phase accumulator, ROM lookup tables for the generation of sine and cosine function, and a digital to analog converter (DAC), as shown in figure 1, where Fetri deciding the accumulating step in the phase accumulator and where Fclk being the operation frequency of the DDFS. Assume phase accumulator is M-bit. The output frequency of DDFS can be written as
~dO dt
-
cik*F o
1-4244-0038-4 2006 IEEE CCECE/CCGEI, Ottawa, May 2006
ctrl
In the proposed DDFS, we implemented the architecture of DDFS with cell-based standard cell to reduce design time and it may be ported to different processes of technology in short time.
(1)
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Table 1 Approximation tanOk by ok New TWO-LEVEL LOOKUP TABLE ALGORITHEM
9sin
sin
=
Sil
9cos
2
-O0i)
Os *(O-O)
FsinOl
(2)
*(O Oi)2(5 22c s6s( -6 )
Oi
cos
Oi
1
cos
Oi
sin
0i
(O - Oi)j
=
Cos
Ftan
tan(a
L
+,83)
=-(O+j
-01i
-=h
FI
tan OiL(O Oi)
1
tan + tan 1 - tan tan
,
a
a
(8)
(9)
(10)
,
In equation (10), a and f3 are two successive phase. Let c»>> and f3_ 0, tan(ac + J) _ tan a + tan/,. ca is the MSB address of phase (u+j3), while f3 is the LSB address of phase (u+j3). In table 1, we can find that Ok = (a tan 2 k)/2f and tan 2 k 2 k when k >7. By the reason, we only require to store tana data in lookup table ROM, tanf /1. Then the following equation can be deduced:
(5)
tano+ C
sin max
'I
OiI
Lcos
(4)
= -1 Col osO
Note that: (O
sin
sin
The equation (8) also can be rewritten as:
sin O = sin Oi + cos Oi (O- Oj) + 5c;, (3) where 0 E [S,iO i+j] , 0 i and 0 1+1 are two successive stored phases. This represents the MSB address of the phase Oi , while the (0 - Oi) represents the LSB address of the phase 0. The maximal sine and cosine error function can be estimated by Taylor-series as:
.sin
0
cos
First, the algorithm uses trigonometric double angle formula to divide cosO, sin 0 into two parts as:
0,) +,5si.
(7)
2
max
The equations (2) and (3) can be rewritten as:
This paper provides a new algorithm to reduce further the size of lookup table ROM for low-power purpose. The proposed DDFS is implemented based on the ROM-based architecture of DDFS.
cos 0 = cos 0i - sin Oi (O -
max
cos
(6)
COSL
1
tanob+ CJL(O-0i)]
(1 1)
The maximal error function can write as: The proposed DDFS only requires two ROM tables, three multipliers, and three adders. The sine/cosine symmetry approach also is used to compress the size of
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ROM. It requires only 0 to wT /4 angle data stored in ROM table.
The ARCHITECTURE OF THE PROPOSE DDFS This section presents the architecture of the DDFS based on the new two-level lookup table algorithm. Figure 2 shows the architecture of the proposed DDFS. In this architecture, the DDFS is implemented by three multipliers and three adders. The new DDFS uses less one multiplier and 25% lookup table ROM size than [1] in the same operation environment. We compare the result in table 2. In Ref [1], the paper doesn't show their power consumption. We compare power consumption of the propose DDFS with Ref [2] and Ref [3]. Table 2 Performance summary of the new DDFS
Ref. [1]
Output word length System clock SFDR ROM table size Adders (Computation
block)
Multiplier (Computation block)
16 bits for sine & cosine 100MHz
10ldB
512 bits
Onel6 +16(bits) One 16+12(bits) One 12+8(bits) One 17*17(bits) One 16*16(bits) One 16*12(bits) One 8*4(bits)
The popose
DDFS 16 bits for sine &
Figure 2 The architecture of the proposed DDFS The SFDR (Spurious Free Dynamic Range) of the proposed DDFS is generated, shown in figure 3, and compare output cosine waveform than ideal cosine waveform in the same frequency, shown in figure 4.
cosine
100MHz 80dB
384bits OM +16(bite) O1ne6 + 16(bits)
One 16+1 (bits) One 16*16(bits) One 16*12(bits) One 16*12(bits)
SIMULATION Modelsim of Mentor and MATLAB of Mathworks are the simulation tools to proceed the system-level simulation. The simulation step as follows: (1) We use Verilog code to translate the propose algorithm for system-level hardware. The architecture of system-level hardware is simulated by Modelsim. Then, we collected the output data of Modelsim.
(2) We use the date which is collected by Modelsim to feed into MATLAB. The fast Fourier transform (FFT) command is executed to attain the spectrum. Figure 3 Simulation SFDR of the proposed DDFS
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system. In addition to, it uses cell-based standard cell to reduce design time. It can be changed different technology process in short time. A synthesized 0.35pm DDFS with a SFDR of -80dB, runs up to 100MHz and consumes 81mW. The power efficiency of our work is 0.81 mW/MHz and 38% less than that of conventional DDFS. The new twolevel look-up table algorithm is proven by the simulation result. The algorithm can efficiently save ALU cells and power consumption in DDFS.
In figure 4, black dotted line represents real cosine output waveform and red line represents ideal cosine output waveform.
Acknowledgements Authors are grateful to National Chip Implementation Center for the chip fabrication.
References
[1] Jen-Chuan Chih, Jun-Yei Chou, Sau-Gee Chen, "An efficient direct digital frequency synthesizer based on two-level table lookup," The 2001 Proceedings of IEEE International Frequency Control Symposium and PDA Exhibition, pp.824-827, 6-8 June 2001. [2] Jinn-Shyan Wang, Shiang-Jiun Lin and Chingwei Yeh ,"A low-power high-SFDR CMOS direct digital frequency synthesizer," 2005 IEEE International Symposium on Circuits and System, Vol. 2, pp.16701673, pp.23-26 ,May 2005. [3] Yongchul Song and Beomsup Kim ,"A 16 b quadrature direct digital frequency synthesizer using interpolative angle rotation algorithm," 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp.146-147, 1315 June 2002. [4] Madisetti, A., Kwentus, A.Y., Willson, and A.N., Jr., "A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range," IEEE Journal of Solid-State Circuits on Volume 34, Issue 8, pp.l1034-l1043, Aug. 1999. [5] Bellaouar, A., O'brecht, M.S., Fahim, A.M.and Elmasry, M.I.," Low-power direct digital frequency synthesis for wireless communications," IEEE Journal of Solid-State Circuits, Volume 35, Issue 3, pp.385390, March 2000. [6] Xuefeng Yu, Dai, F.F., Yin Shi and Ronghua Zhu, "2 GHz 8-bit CMOS ROM-less direct digital frequency synthesizer," 2005 IEEE International Symposium on Circuits and System, pp.4397-4400, on 23-26 May 2005
Figure 4 Real cosine output waveform v.s. ideal cosine waveform
(3) The verilog code is synthesized to gate-level by synopsys tools. We synthesize the new architecture of DDFS by TSMC 0.35pim cell-based standard cell. The simulation result is shown in table 3. VDD
Technology process ( g m) Frequency(m ax) Sin/Cos SFDR(dBc) Output(bits) Power Dissipation
Ref. [2] 3.3V 0.35
Ref. [3] 3V 0.35
100MHz
15OMHz
Yes 100 16 1.32mW/MHZ
Yes 96 16 4.5mW/MH z
Table 3 Performance comparison of different DDFS's
CONCLUSIONS The proposed DDFS has the advantages of low-power, small chip area and low computational complexity. It is very sufficient for low-power wireless communication
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