A wide-range programmable frequency synthesizer ...

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A wide-range programmable frequency synthesizer based on a finite state machine filter a

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Mohammed H. Alser , Maher M. Assaad & Fawnizu A. Hussin

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Department of Electrical and Electronic Engineering, University Technology of Petronas, 31750 Tronoh, Perak, Malaysia Version of record first published: 11 Dec 2012.

To cite this article: Mohammed H. Alser , Maher M. Assaad & Fawnizu A. Hussin (2012): A widerange programmable frequency synthesizer based on a finite state machine filter, International Journal of Electronics, DOI:10.1080/00207217.2012.751322 To link to this article: http://dx.doi.org/10.1080/00207217.2012.751322

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International Journal of Electronics 2012, 1–11, iFirst

A wide-range programmable frequency synthesizer based on a finite state machine filter Mohammed H. Alser*, Maher M. Assaad and Fawnizu A. Hussin

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Department of Electrical and Electronic Engineering, University Technology of Petronas, 31750 Tronoh, Perak, Malaysia (Received 21 October 2011; final version received 30 September 2012) In this article, an FPGA-based design and implementation of a fully digital widerange programmable frequency synthesizer based on a finite state machine filter is presented. The advantages of the proposed architecture are that, it simultaneously generates a high frequency signal from a low frequency reference signal (i.e. synthesising), and synchronising the two signals (signals have the same phase, or a constant difference) without jitter accumulation issue. The architecture is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC). The proposed circuit is designed using Verilog language and synthesized for the Altera DE2-70 development board, with the Cyclone II (EP2C35F672C6) device on board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8 MHz to 440 MHz is synchronized to the input reference clock with a frequency step of 0.12 MHz. Keywords: Field-programmable gate array (FPGA); system-on-chip (SoC); all-digital phase-locked loop (ADPLL); all-digital delay-locked loop (ADDLL); frequency synthesizer; clock synchronizer

1. Introduction In serial data communication systems, the transmitter and the receiver must be synchronised to reliably access the transmitted data. The transmitter starts normally with converting the data from parallel to serial by multiplexing multi low-frequency parallel data streams into a single higher frequency data stream. An internal frequency generation circuit is required to generate multiple clock frequencies and clock the multiplexers. The high-frequency serialized data is then transmitted through the channel to the receiver. On the other hand, the receiver uses a clock and data recovery circuit (CDR) to extract the clock signal from the received data and demultiplexes the data by the recovered clock, to become a low-frequency parallel data again (Assaad and Alser 2011). Typically, phase-locked loops (PLLs) and delay-locked loops (DLLs) are widely utilised in the implementation of the frequency synthesiser, clock synchronisation, and clock and data recovery circuits (Maillard, Devisch, and Kuijk 2002; Mesgarzadeh and Alvandpour 2009; Choi et al. 2011). Conventional implementations of such PLLs/DLLs

*Corresponding author. Email: [email protected] ISSN 0020–7217 print/ISSN 1362–3060 online ß 2012 Taylor & Francis http://dx.doi.org/10.1080/00207217.2012.751322 http://www.tandfonline.com

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are analogue; however, the rapid advances in integrated circuit technology cause their analogue implementations to operate in a very noisy environment (Chung and Lee 2003). Furthermore, considering the progress in improving the overall system performance, stability, and programmability, fully-digital implementations of PLLs/DLLs have become more attractive in many applications than their analogue counterparts. Fully-digital implementations of PLLs/DLLs offer the possibility to achieve low voltage operation, low power consumption, and less sensitivity to noise (since there is no analogue control). Unfortunately, given an identical noise environment and circuit components, PLL has higher jitter than DLL due to phase noise accumulation process (Helal, Straayer, Wei, and Perrott 2008; Casha, Grech, Badets, Morche, and Micallef 2009). Consequently, several fully-digital implementations of PLLs reported in the literature (Chung and Lee 2003; Olsson and Nilsson 2004) aims noticeably at reducing the clock jitter. In Chung and Lee (2003), two digitally controlled oscillators (DCOs) are used to decrease the clock jitter. The first DCO is used for tracking the reference clock and the other is used for generating the output clock. However, the power consumption and chip area are greatly increased. In Olsson and Nilsson (2004), a time-to-digital converter (TDC) is utilised as a digital filter to increase the resolution of the phase error measurement and hence decrease the jitter. On the other hand, fully-digital implementations of DLLs suffer as well from two major drawbacks. First, the multiplication ratio depends mainly on the number of delay cells in the delay line. Second, any mismatch in the edge combining logic will be translated directly into a duty-cycle error and fixed-pattern jitter (Helal et al. 2008; Liang, Yang, and Liu 2008; Casha et al. 2009; Zlatanski, Uhring, Le Normand, and Mathiot 2011). In this article, an FPGA-based design and implementation of a fully-digital wide-range programmable frequency synthesiser based on a digital finite state machine filter is presented. This paper is organized as follows. Section 2 describes the proposed architecture and Section 3 illustrates the key building blocks. Section 4 shows the circuit implementation and experimental results and Section 5 gives the conclusions.

2. Proposed architecture The proposed architecture of the fully-digital frequency synthesiser circuit is shown in Figure 1. The circuit is composed of a frequency locked loop (FLL) and a delay locked loop (DLL) that share a common reference clock, FREF. In summary, the FLL provides a frequency comparison through the frequency detector (FD) and hence maintains the frequency of the reference signal FREF equal to the feedback signal (FDCO/64), whereas the DLL leads to a phase locking (i.e. phases are equal or have a constant difference) between the output clock signal FDCO and the input reference signal FREF through the phase detector (PD). The proposed architecture provides the ability to select integer multiples of the reference signal frequency (e.g. FREF, 2FREF, 4FREF, 8FREF, 16FREF, 32FREF, and 64FREF) that are synchronised to the reference clock signal. The primary benefits of the proposed architecture are that it does not have the jitter accumulation issue of a PLL-based implementation as discussed earlier and the dual-loop architecture provides a more stable system (Ming-ta and Sobelman 2008). The proposed circuit is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits, to get higher multiplication factor of the reference clock frequency. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC).

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REF OUT

OUT

. . . .

REF

OUT

REF

1 DCO

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DCO

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DCO

0 1

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DCO c

Figure 1. Block diagram of the proposed frequency synthesiser.

3. Building blocks description The basic operation of the frequency synthesiser circuit requires six key building blocks to provide frequency and phase locking.

3.1. Digitally controlled oscillator (DCO) The DCO in the proposed architecture is a challenging block to design. It must be able to provide a high frequency resolution and at the same time provide very good frequency stability. Good frequency stability is normally achieved by designing a stable and fast controller, whereas a high frequency resolution is achieved in this work by combining two main blocks: ring oscillator and fractional divider.

3.1.1. Ring oscillator The structure of the ring oscillator (Stefo and Schreiter 2004) is shown in Figure 1. The ring oscillator consists of one NAND gate and a chain of AND-OR delay elements (DEs),

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Ring oscillator frequency FOSC (MHz)

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450 400 350 300 250 200 150 100 50 0

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9 10 11 12 13 14 15 16 17 18 19 20

Ring oscillator chain length

Figure 2. Measured ring oscillator output frequency versus chain length.

each element has a time delay tDE. The NAND gate enables/disables the oscillation. The number of the DEs in the ring is equal to the chain length (L) and is defined by a one-hot coded control word. The signal must go through each of the DEs twice to provide one period of oscillation, whereas reducing the number of DEs in the ring gives higher frequency and vice versa. Therefore, the frequency of the ring oscillator, FOSC is given by equation (1) (Docking and Sachdev 2003). FOSC ¼

1 2LtDE

ð1Þ

Consequently, changing the ring oscillator chain length (L) via a one-hot coded word provides a coarse frequency resolution as shown experimentally in Figure 2 (Assaad and Alser 2012). In the existing designs, several techniques have been reported aimed at providing a fine frequency resolution. First, a multi-stage ring oscillator was used to provide both coarse and fine frequency resolution (Olsson and Nilsson 2004). Second, an integer divider was used to divide the output of the RO into four clock-rates (Moorthi, Meganathan, Janarthanan, Praveen Kumar, and Raja Paul Perinbam 2009). In this work, a fractional divider is used to provide a fine frequency resolution. 3.1.2. Fractional divider The fractional divider comprises an adder-accumulator as shown in Figure 3. The MSB of the signed register is used to switch the input of the adder between signed integer value N and its two’s complement N-M, where the number of bits of N is equal to the number of bits of the signed register. The fractional divider is also used to switch between two adjacent ring oscillator chain lengths, (L1) and (L1þ1). The DCO output clock frequency, FDCO is given by Equation (2). FDCO ¼

N FOSC ðL1Þ

M MN þ FOSC ðL1þ1Þ

ð2Þ

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N[8] N-M[8] Register[8]

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Register[8]

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N[0] N-M[0] Register[8]

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begin if (Register == 0) Register