2011 17th IEEE Pacific Rim International Symposium on Dependable Computing
A Method of Gate-level Circuit Reliability Estimation Based on Iterative PTM Model Jie Xiao1 Jianhui Jiang1,2 Xuguang Zhu1 Chengtian Ouyang1 1
College of Electronics and Information Engineering, 2School of Software Engineering Tongji University, Shanghai 201804, CHINA
[email protected];
[email protected] contained in a circuit. It has the same precision as the PTM method, but has lower time overhead for large circuits.
Abstract—The rapid development of nanotechnology has opened up new possibilities and introduced new challenges for circuit design. It is very important to study new analysis methods for accurate circuit reliability. Few methods for evaluating circuit reliability were proposed in recent years. For example, the original probabilistic transfer matrix (PTM) model has large time and space overhead, so it can only calculate small scale circuits; the improved PTM model proposed in [2] can handle large scale circuits but it also has large time overhead. In this paper, the concept of macro-gate is defined and an iterative PTM model based on macro-gate is proposed. Based on this model, a circuit reliability evaluation algorithm that can calculate the circuit reliability from primary input to any level of the circuit is given. The complexity of the proposed algorithm related to the number of macro-gates contained in the circuit is linear. Experimental results show that the proposed method has the same accuracy as the PTM model, but it has lower time overhead for large circuits.
II.
MACRO-GATE
In this paper, a macro-gate is defined as an elementary gate or a group of gates from the fanout point to convergent gates or the primary outputs (POs) of the circuit. An example circuit constituted by four macro-gates (A, B, C, D) is shown in Fig.1. Where circuit Li ( ͳ) means the ith level; X means the macro-gate’s sign; wXLi means the width of macro gate X in level Li; the width of macro-gate X means the maximum width in any wXLi; dX means the depth of macro gate X, and dXLi means the depth of macro gate X in Level Li, it satisfies dXLi=dXLi-1+1; LIPXLi and UIPXLi mean the lower and upper exterior input of X in level Li separately; RXLi means the reliability of the macro gate X from PIs to the level of Li.
Keywords-Gate-level reliability estimation; macro-gate; iterative PTM model; logical partition
I.
INTRODUCTION
As the scale of integrated circuits expands and the feature dimension shrinks, it is important to pay attention to the circuit reliability. The reliability of a logic circuit is a measure of its susceptibility to permanent, intermittent and transient faults. Several methods for evaluating circuit reliability were proposed in recent years. For example, a model based on probabilistic transfer matrix (PTM) can accurately measure the reliability of the circuit [1]. But the matrix size increases exponentially with the increment of the number of the circuit signals, which leads to immense time and space complexity. [2] given another method that a circuit is partitioned into modules firstly, and then calculates each module’s reliability by employing the PTM method. The reliability of the overall circuit is multiplied by every module’s reliability. It causes damages of the circuit structure and does not consider the dependency between modules, so the precision of calculation suffer a loss. The probabilistic gate model (PGM) [3] takes gate as unit, and uses outputs whose probability is correct as the reliability of the circuit by iterative method. [4] presented a probabilistic model checking (PMC) method based on the Markov chain of district time, which has considerable similarity with the PGM. Based on the weighted averaging algorithm (WAA) method [5], and combined with the correlation method proposed by Ercolani [6], Choudhury considered the circuit’s fanout, which enhanced the WAA method’s rationality [7].
Figure 1. An example circuit constituted by four macro-gates
III.
FOR CIRCUIT RELIABILITY EVALUATION
A. Reliability of a fanout-free circuit It is supposed that the jth macro-gate at ith level could be noted as elementary gate ୧୨ with two inputs and single output. The PTM and ideal transfer matrix (ITM) of ୧୨ are represented as PMij and IMij, respectively. The probability distribution of the two-input are ଵ୧୨ and ଶ୧୨ , the output reliability of ୧୨ is Rij, and the probability distribution of the output is goij. The reliability add-matrixes of ୧୨ areୖଵ ౠ and ୖଶ ౠ . The reliability calculation of circuit is conducted by theorem 1. Theorem 1: It is assumed that an elementary gate has independent failure probability p, the circuit reliability can be calculated by iterative PTM model, which is operated by adding macro-gate reliabilities to the next macro-gate level by level. The Rij and goij of a macro-gate can be expressed as follows. ୧୨ ൌ ൫ଵ୧୨ ۪ଶ୧୨ ൯ ൈ ሺ൬ቀୖଵ ౠ ۪ୖଶ ౠ ቁ ൈ ୧୨ ൰ Ǥൈ ୧୨ ሻ (1a)
To evaluate reliability of the large-scale circuit accurately, this paper puts forward a concept of macro-gate, and provides an algorithm based on iterative PTM model for evaluating the reliability of combinational circuits. The complexity of the algorithm is linearly related to the number of macro-gates
୧୨ ൌ ሺଵ୧୨ ٔ ଶ୧୨ ሻ ൈ ୧୨
The National Natural Science Foundation of China under Grant No. 60903033 and The Research Fund for the Doctoral Program of Higher Education.
978-0-7695-4590-5/11 $26.00 © 2011 IEEE DOI 10.1109/PRDC.2011.45
AN ALGORITHM BASED ON ITERATIVE PTM MODEL
276
(1b)
B. Reliability of a macro-gate with fanout For a macro-gate with fanout, we have the following theorem.
results obtained by PTM, the proposed method and the method proposed in [2] on circuits are given in Table I. Reliability of 74X-Series, C432, C1355, C2670, C5315, C7552 circuits listed in Table I can’t be obtained by PTM method.
Theorem 2: It is assumed that an elementary gate has independent failure probability p. By employing the propagation matrixes ୧ and ୧ , the reliability of a macro-gate ୧ from fanout point to the ith level can be calculated by the following formula.
TABLE I.
EVALUATION RESULTS FOR CIRCUITS USING THE PROPOSED METHOD, THE METHOD IN [2] AND PTM (P=0.0001 AND 50 RUNS)
Circuit C17 Fulladder Schneider Fig.1 circuit Fig.2 circuit 74148 74157 C432 C1355 C2670 C5315 C7552
୧ ൌ ୧ ൈ ሺ୧ Ǥൈ ୧ ሻ ୧ ൌ ሺሺ୳୧ ٔ ୧ିଵ ٔ ୢ୧ ሻ ൈ ୧ ሻ ୧ ൌ ሺሺ ୳୧ ٔ ୧ିଵ ٔ ୢ୧ ሻ ൈ ሻሺʹሻ ୧ ୨ ൌ ሺሺ୳୨ ٔ ୨ିଵ ٔ ୢ୨ ሻ ൈ ୨ ሻǡ ʹ ୧ ൌ ୳୧ ٔ ሺሺ୧ିଵሻ ൈ ୧ିଵ ሻ ٔ ୢ୧ Where, i1. ୧ means the probability distribution of the input of a macro-gate’s ith level; ୧ is the propagation matrix from fanout point to the ith level; ୧ is the ideal propagation matrix from fanout point to the ith level; ୧ is the PTM of the ith level; ୧ is the ITM of the ith level; ୧ is the ith level’s output probability distribution; the propagation matrixes of the upper and lower exterior input of a macrogate’s ith level are presented as ୳୧ andୢ୧ separately, their corresponding ideal propagation matrixes are presented as ୳୧ and ୢ୧ separately, and their corresponding probability distribution are ୳୧ andୢ୧ separately.
The calculation algorithm of circuit reliability
1. Partitioning the circuit into levels and making that the circuit is constituted by macro-gates;
PTM Reliability Time (s) 0.999525 0.078
0.999575
0.578
0.999513
0.031
0.999575
0.063
0.99945
0.579
0.999418
0.187
0.99945
0.218
0.999382
0.609
0.999261
0.328
0.999382
0.25
0.999613
0.593
0.999013
0.109
0.999613
0.297
0.999412 0.999738 0.999276 0.999405 0.990504 0.992778 0.982561
0.719 0.625 2.875 6.203 11.391 25.625 31.641
0.996905 0.998501 0.984135 0.949931 0.905342 0.819697 0.742944
0.296 0.218 8.141 21.11 23.422 129.945 106.75
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V.
CONCLUSIONS
The concept of macro-gate and iterative PTM model are proposed in the paper. For macro-gates with fanout, ADDs and logical partition strategy are adopted. The propagation matrix is used to implement circuit reliability calculation from PI to any macro-gate in a circuit. Based on the iterative PTM model, the paper constructs a circuit reliability evaluation algorithm. Its complexity is linear to the number of macro-gates. The experimental results show that the proposed method has the same accuracy as the PTM but has lower time overhead for large circuits.
1) From primary input (PI) to PO, identifying the level index of each macro-gate and calculating its width in each level; 2) Traversing each level and calculating the corresponding width and depth of each macro-gate; 2.Calculating the reliability and the output probability distribution of each macro-gate at the ith level of the circuit; 1) Calculating the macro-gate’s reliability and the output probability distribution by Theorem 1 if the width and the depth of the macro-gate are 1, otherwise by the Theorem 2;
REFERENCES
2) Go to the (i+1)th level; [1]
3. Calculating the reliability of the overall circuit; For POs with single macro-gate, output the reliability directly or the product of these reliabilities.
[2]
Fig. 2 illustrates an another circuit for experiments. It is partitioned into 7 levels and macro-gates are marked by dotted lines.
[3]
[4]
[5]
[6]
[7]
Figure 2. Another example circuit
IV.
The method in [2] Reliability Time (s) 0.999425 0.046
It can be seen from Table I that for small circuits, PTM is faster than the proposed method and sometimes the method in [2] is faster than the other two methods because the proposed method adopts algebraic decision diagram (ADD) to compress the matrix blocks and logic partition method to partition the circuit. But for large circuits, such as C432 and C1355, the proposed method is faster. The reliabilities of the circuits list in Table I calculated by the proposed method are larger than that obtained by the method in [2], but it has the same accuracy as the PTM model, this is because the method proposed in [2] partitions a circuit into independent modules which usually appear overlap, and it takes the product of all modules’ reliabilities as the reliability of a circuit.
C. Reliability of a circuit To calculate the reliability of a circuit constituted by fanoutfree or fanout macro-gates, we give the following algorithm. z
The proposed method Reliability Time (s) 0.999525 0.593
EXPERIMENTAL ANALYSIS
Experiments are conducted on a DELL PC (CPU: Core
[email protected] and the memory: 1.98GB). The experimental
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