A Minimized DC-Bus Capacitor with Active Combinational Decoupling ...

A Minimized DC-Bus Capacitor with Active Combinational Decoupling Method for DC-AC Application Xiaofeng Lyu, Yanchao Li, Ze Ni and Dong Cao Sustainable Power Electronics and Electric Drive Lab (SPEED) Department of ECE, North Dakota State University Fargo 58102, USA Email: [email protected], [email protected] Abstract—This paper shows a combinational decoupling method to minimize dc-bus capacitance and improve power density for DC to AC applications, especially for single-phase inverters. The proposed method is combined with in-series structure and in-parallel structure together with power equations analyzed. The detailed control strategy is given. The simulations are conducted via PLECS software to prove the theoretical proposal. Furthermore, a 2kW prototype is built. The power density of this prototype is ~55W/inch3. The decoupling capacitance is minimized ~2/3 that of traditional series voltage compensator method. The experiments are further finished and the efficiency of the prototype is ~ 95%. Besides, the issues for 2nd order decoupling method is investigated and an instantaneous pulse decoupling method is discussed in this paper. A brief comparison of these two methods are summarized.

Another extra circuit or passive component is normally taken for active power decoupling methods. Depending on the position for these decoupling circuit, it can be classified DCside methods and AC-side methods. In-series voltage compensator methods [3]-[5] and in-parallel methods [6] belong to DC-side methods. A 2nd order voltage circuit is connected in-series on the dc-bus line [3]. For this method, there is low voltage stress for the extra device. The dc-bus capacitors are placed by long-lifetime film or ceramic capacitors. However, the extra capacitance is still extremely large and they are usually taken by electrolytic capacitors. [5] proposed 2nd current compensation method with full-bridge inparallel. This is the dual structure compared with voltage compensation in-series method [3]. [6] proposed in-parallel interleaved method to reduce 2nd order component.

Keywords—single-phase inverter; high power density; power decoupling; dc-bus capacitor;

The ac-side technique for inverter applications contains 3 legs [7]-[8] and 6-switch method. The principle of this kind of method is to transfer the ripple power to third-port on the ACside. 3-phase controls can be applied for this situation. The control method is complex and flexible. Also, [9] reduced dclink capacitor from the system structure. In a word, most papers are focused on topology parts, which introduced another decoupling port to absorb 2nd order harmonic component.

I.

INTRODUCTION

Single-phase inverter with small-size and high-density is the hot topic recently. Google/IEEE Little Box Challenge [1] also promoted it with many novel ideas appeared. The density issues for inverters are how to minimize the passive filter and dc-bus capacitance. In order to minimize the passive filter, one solution is to increase the system switching frequency. However, increasing switching frequency means high switching loss. What’s worse, fast switching is also a challenge for Si device. Another solution to increase switching frequency is to apply Silicon Carbide (SiC). SiC [2] devices have better characteristics than Si devices. For dc-bus capacitance, the function of the large-size capacitor is applied to absorb the pulsating power at twice the fundamental frequency shown in Fig.1. Increasing switching frequency has little contribution on reducing this part. This is because the dc-bus capacitance has little relationship with high-frequency parts. Normally, these dc-bus capacitors can cause short lifetime and large size. For the sake of reducing the dc-link capacitance, there are lots of decoupling methods presented and summarized. Among these methods, active power decoupling methods are widely used and popular.

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Fig.1 Key waveforms of power decoupling analysis

This paper combines series-structure dc-side method with parallel ac-side method together called combinational method so that it can further reduce capacitance in the extra decoupling circuit as presented in Fig.2. Besides the introduction part, section II shows the topology of this combinational method. Control strategy, simulation and experimental results for combinational method will be presented in section III. A further discussion and comparison on instantaneous pulse power compensator method are presented in section IV. The conclusion is drawn in the final part. B

A

MOS_1

Rs

C_bus C

MOS_2

Value

Parameters

Value

Vin

450V

Rs

10Ω

Vo

240V

Po

2kW

1uF Cf Fig.3 shows the 3-D plot for voltage ripple with dc-link capacitance and power factor angle without any power decoupling method. The parameters are followed in Table.1. L_n

R

L_2

MOS_3

Parameters

240uH

Paper [3] utilized an series-structure compensation method to create the ac voltage between A and B to cancel dc-bus 2nd order voltage ripple. Considering that the phase angle is the same to dc-bus voltage ripple, the AB voltage and AB current can be shown by (2) and (3), respectively,

MOS_4 L_1

DC

TABLE.1 PARAMETERS FOR SINGLE-PHASE INVERTER

v AB (t ) = V AB sin 2ω t

(2) (3)

i AB (t ) = I AB sin(2ω t + ϕ AB )

MOS_1'

Where VAB and IAB are values of the series-structure voltage and current. The load is just a capacitor Cb then the current IAB can be derived by (4).

MOS_3'

MOS_5'

L3 a A

B

A

i AB (t ) = 2ω CbV AB sin(2ω t + π / 2)

Cb

Ca b

MOS_2'

MOS_6'

Lb

c

B

So the instantaneous power provided by the extra circuit is given by (5).

MOS_4'

For the decoupling part, the equations can be got from (5) and (6)

Fig.2 Combinational decoupling Schematic.

II.

 va (t )=v AB (t ) = V AB sin 2ω t   vb (t ) = Vb sin(2ω t + ϕ vb )  v (t ) = 0  c

THEORTICAL ANALYSIS

Fig.1 shows basic waveforms for single-phase inverter and Fig.2 shows the proposed schematic with combinational decoupling system structure. Fig.2 illustrates the schematic of combinational circuit to minimize the dc-bus capacitance and further minimize the extra decoupling capacitance.

Cdc =

Pdc ωVdc ΔVdc

(4)

ia (t ) = iAB (t ) = 2ω CbVAB sin(2ωt + π / 2)   ib (t ) = I b sin(2ω t + ϕib )  i = −i − i a b  c

(1)

Where Po is the power rating of the system, Vdc is the dc-

(5)

(6)

Depending on space vector relationship, the instantaneous power can be shown in (7).

link voltage and Δ Vdc is the ripple of the dc-link voltage.

V 1 2 cos(4ω t + π / 2) + Vb b cos(4ω t + ϕvb + ϕib )] = 0 P (t ) = [2ω CbVAB 2 2ω Lb

(7) th

In order to minimize decoupling capacitance, 4 order voltage component could be moved to another decoupling inductor. Equation (8) gives how to evaluate the capacitance and decoupling inductor value. Vb = 2ωVAB Lb Cb

(8)

ϕvb = π

Fig.3 3-D plot for voltage ripple with capacitance and power factor angle

The decoupling inductor can be designed with small-size with planar inductor. This inductor just deals with small reactive power compared with the main power loop.

2240

III.

SIMULATION AND EXPERIMENTAL RESULTS

With In-series power decoupling method

As the theoretical analysis is shown above, Fig.4 (a) shows the inverter main part control diagram. Fig.4 (b) presents decoupling control diagram. Firstly, the main circuit dc-link voltage VB is sampled.

ΔV=5.38V

ΔV=1.72V

With the proposed method

Fig.6 Decoupling capacitor voltage ripple waveform for in-series method and combinational method

Fig.4 Control block diagram (a) main circuit part and (b) combinational decoupling part

The simulations are conducted to verify the proposed combinational method with PLECS software. The source is assumed the 450V dc voltage source. A 10Ω resistor is connected in-series in order to amplify the voltage ripple. The power rating is 2kW. And the ac output voltage is ~240V. Fig.5 shows DC-bus voltage ripple and ac output voltage waveforms. For the main power voltage ripple, both in-series compensation method [3] and the proposed combinational method can achieve to ~11% voltage ripple of no power decoupling method. Fig.6 presents decoupling capacitor voltage ripple waveform for in-series method and combinational method, respectively. Besides the main power processing, the combinational decoupling voltage ripple can be reduced by 68% when compared with [3], which means under the same ripple condition, the capacitance comparisons are shown in Table.2. Under the same condition, combinational method can further minimize the decoupling capacitor ~68%.

Fig.7 Comparison of spectral analysis for extra capacitor voltage TABLE.2 CAPACITANCE EVALUATION AND COMPARISON Parameters

Without Any decoupling method

Cbus Ca

Series [3]

Combination

920uF

100uF

100uF

-

1000uF

320uF

And the spectrum analysis for both methods are shown in Fig.7. Both 2nd order component and 4th order component are minimized shown in the figure. ΔV=87.5V ΔV=10.5V Without Power Decoupling Method

With In-series or Proposed Method

AC Output Voltage

Fig.8 2kW inverter 3-D prototype of the combinational method Fig.5 DC-bus voltage ripple and ac output voltage waveforms

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MOS_1

MOS_2

Scope

MOS_3

DSP Program MOS_4

DC Source

Fig.10 (a) 100 kHz Silicon Carbide device gate signal waveform (20V/div, 5us/div)

Prototype Input in-series resistor

DC-link Voltage

Load

AC Output Voltage

Fig.9 Overview of the test bench

A 2kW prototype is built to verify the combinational decoupling method. Fig.8 presents the front and back view of 3D picture for the prototype with a density of ~55W/inch3. The prototype here used 8 SiC device with 2 in-parallel structure. Actually, it is still full-bridge structure. Fig.9 shows the overview picture of the experimental test bench. The dc source and input resistor are shown in the figure. The controller is used with DSP28335 onboard. 100 kHz Silicon Carbide device gate signal waveform is presented in Fig.10 (a). In order to achieve fast switching characteristics, positive 20V for turn-on and negative 5V for turn-off are applied in the gate driver circuit. Fig.10 (b) shows the ac output voltage and current waveforms. Beside output waveform, dc-bus voltage ripple is also presented in the figure. As measured in the figure, average dc-bus voltage value is ~390V because of series 10Ω resistor. Over 12% voltage ripple can be got without any decoupling method here. Fig.10 (c) also shows the same ac output voltage and current waveforms, which makes the comparison under the same situation. With combinational decoupling method or series compensation method [3], most of 2nd harmonic voltage ripple can be cancelled. The dc-bus voltage ripple achieves ~3%. Fig.10 (d) presents the decoupling capacitor’s voltage ripple waveforms. The combinational method have ~60% lower voltage ripple than series method [3]. Fig.11 (a) shows 2kW evaluated efficiency curves for combinational method and [3]’s series compensation method. The efficiency for combinational method decreases when compared with just series-structure method [3]. This is mainly because decoupling circuit has more power loss for 6-switch devices and decoupling inductor. Evaluated and detailed experimental efficiency for combinational decoupling method for 2kW inverter are shown in Fig.11 (b). About 0.5% difference exists for evaluations and experiments, because auxiliary circuit and parameter’s loss consume are not calculated for estimation.

AC Output Current

Fig.10 (b) dc-bus voltage (60V/div) with ac output voltage (120V/div) and current (10A/div) without any decoupling. Time scale: 5ms/div DC-link Voltage

AC Output Voltage

AC Output Current

Fig.10 (c) dc-bus voltage (60V/div) and ac output voltage (120V/div) and current (10A/div) with combinational method

Voltage Ripple for Extra Capacitor with In-series Method

Voltage Ripple for Extra Capacitor with Proposed Method

AC Output Voltage

Fig.10 (d) Comparison of decoupling capacitor voltage (20V/div) and output ac voltage (140V/div). Time scale: 4ms/div

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Fig.12 Comparison of traditional theory calculation and simulation

Fig.11 (a) 2kW evaluated efficiency for combinational method and [3]’s series compensation method

Fig.13 shows the pulse analysis method waveforms for high-power-density single-phase inverter application. Compared with traditional 2nd order method with various power decoupling topologies, pulse method proposed a totally new theoretical analysis from a pulse-power point of view [10]. For dc-link voltage ripple evaluation, traditional theoretical analysis is not suitable for small-capacitance power decoupling applications, however, pulse theoretical analysis can be applied in the whole range. Although pulse waveform is highfrequency components, uundoubtedly, wide band-gap device can promote pulse method in these power decoupling applications in the future.

Fig.11 (b) Evaluated and detailed experimental efficiency for combinational decoupling method for 2kW inverter

IV.

DISCUSSTION ON PULSE INJECTION DECOUPLING METHOD

Actually, the traditional active power decoupling methods only consider 2nd order harmonic component. They transfer the reactive power from dc-link capacitors to other extra inductors and capacitors via different topologies and controls. This is mainly because 2nd order harmonic is the domain component and its theoretical analysis is easy to achieve. Therefore, most of papers proposed another port, namely, third port to absorb 2nd reactive power. However, few papers investigate other higher harmonics effect for the dc-bus capacitor and how to cancel them to further eliminate the dcbus capacitance. From Fig.12, it shows that when dc-link capacitance is small enough, the traditional dc-link voltage ripple is quite different from the simulation results. The comparison shows that equation (1) is just a briefly evaluated for large-size dclink capacitor selection without any power decoupling consideration. For power decoupling method with small-size dc-link capacitor, traditional equation has not much consideration in details. Actually, the current on the dc-link side is pulse current waveform and pulse current contains different-order harmonic components.

Fig.13 Schematic and issues for traditional 2nd order method

Fig.14 shows the comparison for traditional power decoupling method [3] and pulse power decoupling method with combinational decoupling circuit. Without any power decoupling method, the voltage ripple is both 76.5V under dclink capacitor 100uF. With power decoupling methods, respectively, in-series method reduces the dc-link voltage ripple to 15V, while pulse power decoupling method can achieve 9.1V under the same condition. ~1.5% improvement is achieved compared with 2nd order method, because pulse injection method considers other higher order harmonics effect. Furthermore, at the time 0.1s, the dc-link capacitor is changed from 100uF to 10uF, it is obvious the traditional method is not suitable under this discontinuous mode but pulse power injection method is still working with the voltage ripple 12.6V.

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In conclusion, for traditional method, it is not suitable under so small-value dc-link capacitor.

injection method applied in the combinational decoupling circuit, voltage ripple can be cancelled more, especially under small dc-bus capacitance condition.

REFERENCES [1]

Fig.14 Comparison of traditional 2nd order method [3] (red line) and proposed method (blue line) with pulse injection control under dc-link capacitance 100uF and 10uF

V.

CONCLUSION

This paper shows a series and parallel combinational decoupling method to minimize dc-bus capacitance and improve power density for DC-AC application. With basic power equation derivation, the proposed method is analyzed and compared with other methods in theory. With basic power equations, 2nd order compensator method is proposed first and detailed control diagram are given. Both simulation and experimental results verify the proposed combinational method very well. Besides, the issues for 2nd order decoupling method is further investigated. Furthermore, an instantaneous pulse decoupling method is discussed in this paper. A brief comparison of 2nd order component injection and pulse injection method are shown. It is concluded that with pulse

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