A Multi-Core Signal Processing Platform with ...

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REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < Other approaches that leverage on the trade-off between cost and performance rely to the utilization of regularity. In the past, in the field of multi-processor systems, regularity has commonly been used for the implementation of processor arrays [17][18] allowing designers to focus on a small portion of silicon and replicating the tiles many times over the die surface. Another class of devices that deals with regularity to reduce the mask costs is that of structured ASICs, also known as gate arrays. Gate arrays are integrated circuits that are partially fabricated using a set of generic masks that can be further programmed with a set of custom mask. They are mainly divided into via-programmable (VPGA) [19] and metal-programmable (MPGA) [20][21] gate arrays. From this perspective, Field Programmable Gate Arrays (FPGAs) [22][23] can be considered as structured ASICs with maximum flexibility. B. Overview With respect to most of commercially and research ASSPs, which tend to increase the flexibility of their accelerators in order to extend their application portfolio, the platform proposed in this paper reduces the design time by implementing custom hardware accelerators with a design flow that starts from a high-level description language, and leverages structured ASIC technologies to achieve the required flexibility. Considering the design methodology, a main objective of the platform is to fill the performance gap between the fully automatic customization (utilizing HLS-ELS techniques) and manual customization (utilizing standard ASIC design methodologies) [25] by exploiting a design flow that allows to design and implement algorithmic-specific, coarse-grain, pipelined hardware accelerators, and a design platform that allows to calibrate the architectural parameters over the specific features of the implemented accelerators. From an implementation standpoint, the proposed platform targets the reduction of design and manufacturing costs joining the regularity at architectural level and physical level, adopting a tile-based implementation methodology and structured ASIC technologies as silicon platform for the hardware accelerators. With respect to most of reconfigurable and configurable technologies that target the general-purpose implementation of digital circuits, the ones proposed in this work are specifically designed and optimized for signal processing, as they target the direct mapping of data flow graphs into configurable pipelined datapaths. Considering specific platforms for embedded signal processing based on multi-processors augmented with hardware accelerators, configurable either at run-time or design-time, few of those targets the specific research domain proposed in this work. In a previous work [24], the authors present Morpheus: a multi-core digital signal processor with three reconfigurable computing units featuring different granularities. With respect to Morpheus the proposed platform overcomes its intrinsic heterogeneity with the advantage of providing benefits in terms of application mapping ease through the exploitation of high level programming models.

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Moreover, the proposed platform provides a higher computational density as at any time it can guarantee that all the computational units can run concurrently by exploiting either homogeneous or heterogeneous computational models. Finally, this work provides different configurable technologies for the implementation of accelerators targeting the different trade-offs between NRE costs, TTM and computational efficiency. In [25] an exploration of the trade-offs in the customization through the automated instruction set extension of a multi-processor system on chip is described. The exploration was performed utilizing the Tensilica’s Xtensa Modeling Platform as its base. Although the automated flow for realizing tightly coupled accelerators provided good results, the next step consisting of the implementation of coarse-grained extensions attached to the memory subsystems had to be done implementing custom blocks. A key objective of the proposed work is to overcome these kinds of limitations by providing the accelerators with a flexible but efficient memory access subsystem. In [26] a multi-core cluster with shared hardware accelerators is presented. The accelerators have been designed with Mentor Catapult C [13]. Although the accelerators have dedicated ports connected to the shared memory subsystem, the address patterns are hardwired within the custom blocks, thus limiting their flexibility. On the contrary, in the proposed work only the inner loop of kernels are hardwired within custom blocks, while the addressing and memory accesses are performed through programmable blocks on a separate interface. Summarizing, the main contributions of this work are: a) A design-time configurable computational platform aimed at the implementation of multiprocessor systems-on-chips augmented with (re-) configurable hardware accelerators. b) A design framework that assist the user in the exploration of the architectural parameters of the platform and in the design of application-specific hardware accelerators utilizing high-level programming models. c) The evaluation of the adopted programming, architectural and technological techniques through the exploration of their impact on flexibility, performance, energy efficiency and manufacturing costs. d) The establishment of the proposed platform novelty through a comparison with respect to the state-ofthe-art devices that define its design space boundaries. The paper is structured as follows. Section II gives an overview of the platform. Section III provides a description and an evaluation the computational paradigm of the platform. Section IV provides a quantitative analysis of the platform. Section V gives the comparison of the proposed platform with established state-of-the-art solutions. Section VI provides some final considerations.

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REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) < respect to a multi-processor system on chip with no specialization, the platform have been proven able to provide up to 3 orders of magnitude of improvement in performance and energy efficiency in several signal processing applications delivering an average of 90 GOPS and 130 GOPS/W. When compared with the devices that define its design space boundaries, the proposed platform has been proven competitive in both area and energy efficiency. With respect to these devices, a key advantage of the proposed platform is to target the applications performance and energy efficiency through the hardware/software migration of kernels, and acutely reducing NRE costs through exploitation of configurable technologies for the implementation of application-specific hardware accelerators. REFERENCES [1]

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Davide Rossi received the electronics engineering degree from University of Bologna, Bologna, Italy and M.Sc. from Tampere University of Technology, Tampere, Finland in 2007. In 2012 he received the Ph.D. degree with the Advanced Research Centre on Electronic Systems (ARCES) from the University of Bologna, Bologna, Italy. From 2008 to 2012 he has also been a consultant for STMicroelectronics in the field of reconfigurable computing. Dr. Rossi is currently a senior member of the ERC MULTITHERMAN laboratory, Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy. His main research interests include VLSI system on chip design, configurable systems based on run-time and metal programmable devices, multi-processor systems, and ultra-low-power platforms. He is co-author of about 15 publications on international conferences and journals in the same fields.

Claudio Mucci received the Electronics Engineering degree from the University of Bologna, Italy, in Feb. 2003 and the PhD degree at the same university in 2007. Since 2003, he has been with the Advanced Research Center on Electronic Systems “E. De Castro” (ARCES), Bologna, and during that period he has been an STMicroelectronics consultant in the field of reconfigurable computing. Since 2009, he joined STMicroelectronics Technology R&D, Agrate Brianza, Italy. His main research interests include configurable platforms based on run-time and metal-programmable technologies, digital signal processing, application development and related methodologies applied to embedded programmable system. He is co-author of about 30 publications on international conferences and journals in the same field.

Matteo Pizzotti received the electronics engineering degree from the Polytechnic University of Milan, Italy in 2005. Since 2005 he is an ST Microelectronics consultant in several fields of digital electronics including high level modeling, reconfigurable embedded systems and related design flows, low power design and microcontroller programming. He is currently working on low power systems for energy harvesting sensor networks.

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Luca Perugini received the electronics engineering degree from the University of Bologna, Italy in 2006. Since 2006 he is an ST Microelectronics consultant in the field of digital reconfigurable systems and 3D chip-to-chip wireless interconnects. He is currently working on low power systems for energy harvesting sensor networks.

Roberto Canegallo received the degree in electrical engineering from University of Pavia, and PhD from University of Bologna, Italy. He worked for five years in Central R&D on multilevel Flash memories. Since 1998, Dr. Canegallo has been working at the joint ST research Lab with University of Bologna. His work has focused on integrated, innovative designs of system on chip and he is author of many scientific papers and holds European and US patents. Dr. Canegallo is currently a senior member of Technical Staff in the Smart Power Technology R&D in STMicroelectronics and the project coordinator at STMicroelectronics lab which is jointly managed with ARCES the advanced research center on electronic systems of the University of Bologna. His main activities are in the field of advanced hardware design and three-dimensional silicon integration.

Roberto Guerrieri received the M.S. and Ph.D. degrees from the University of Bologna, Bologna, Italy. Since 1986, he has been visiting the Department of Electrical Engineering and Computer Science, University of California, Berkeley, for four years and the Department of Electrical Engineering, Massachusetts Institute of Technology, Boston. During his scientific activity, he has published more than 90 papers in various fields, including numerical simulation of semiconductor devices, numerical solution of Maxwell’s equations, parallel computation on massively parallel machines, and reconfigurable architectures. In 1998, he became the Director of the Laboratory for Electronic Systems, a joint venture of the university of Bologna and STMicroelectronics for the development of innovative designs of systems-on-chip. He is currently a Full Professor of electrical engineering with the University of Bologna. Dr. Guerrieri was the recipient of the Best Paper Award in the IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING in 1992, for his work in the area of process modeling, and the “ISSCC Best Paper Award” in 2004, for his work on sensor system designs.