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A Nonlinear Wide-Bandwidth Digital Current Controller for DC–DC and DC–AC Converters Simone Buso, Member, IEEE, and Tommaso Caldognetto, Student Member, IEEE
Abstract—A fully digital, nonlinear, wide-bandwidth current controller for dc–ac and dc–dc voltage source converters is presented in this paper. Exploiting oversampling, the controller mimics an analog hysteresis current controller, but it does not employ analog comparators, digital-to-analog converters, or any other analog signal pre- or postprocessing circuitry. Indeed, it fully virtualizes the hysteresis controller’s operation and, based only on a nonlinear, efficient current error processing algorithm, drives the power converter at almost constant switching frequency. Overall, it offers the same excellent dynamic performance of the analog hysteresis controller and, at the same time, solves most of the related problems. Because the current error sample processing algorithm is inherently parallel in structure, the controller is suited for VHDL synthesis and field-programmable gate-array implementation, which guarantees flexibility and low cost, together with minimum computation and signal conversion delays. Its intended application areas include active filters, uninterruptible power supplies, microgrid distributed energy resource controllers, laboratory battery testers, and welding machines. Index Terms—Current control, digital control, hysteresis control, nonlinear filters.
I. I NTRODUCTION
W
IDE-BANDWIDTH current control loops represent the backbone of a large variety of switching converter applications. Different wide-bandwidth current control solutions have been proposed in numerous technical papers, but the hysteresis current controller, due to its excellent dynamic characteristics, is the one that found the widest application. Indeed, its small- and large-signal responses are practically ideal, which guarantees minimum phase lag and residual reference tracking error. In dc–dc converter applications such as welding machines and fuel cells or in battery forming converters [1]–[6], [8], these properties are shown to allow fast and controlled current transients. In current-mode-controlled dc–ac converters, the wide-bandwidth current regulation is particularly effective in active filter applications, where it allows higher order harmonic compensation, but it is sometimes employed also in highperformance electrical drives [9], [10], as well as in multilevel Manuscript received November 5, 2014; revised February 16, 2015 and April 28, 2015; accepted July 22, 2015. Date of publication August 6, 2015; date of current version November 6, 2015. The authors are with the Department of Information Engineering, University of Padova, 35131 Padua, Italy (e-mail: simone.buso@ dei.unipd.it;
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2015.2465351
converters [11]–[13], both for drive and grid-tied applications. Even when the ultimate objective of the control system is to regulate a converter’s output voltage, a fast inner current control loop is highly desirable for protection purposes and/or to allow current limitation during large voltage reference or load transients. On the other hand, the hysteresis controller operation always results in variable switching frequency, unless the voltage conversion ratio (or the inverter modulation index) and the current reference are both constant, which is seldom the case, at least in dc–ac converter applications. Constant or limited switching frequency solutions such as those proposed in [5]–[7] or [14]–[22] are often sensitive to variations of system parameters (e.g., dc-link voltage and inductance value), to dead times, and to sampling delays. These factors, altogether, limit the practical effectiveness of the frequency regulation. In addition, these solutions employ additional analog hardware, which makes them relatively complex and sensitive to offsets, drifts, tolerances, and aging effects. For instance, operational amplifiers are needed in [4], whereas low-latency comparators and/or digitalto-analog converters (DACs) are used in [5], [6], and [15]–[22]. Likewise, frequency-to-voltage converters are adopted in [23] and [24]. Monolithic highly effective implementations have been also proposed [3], which, however, offer no flexibility, being tailored to very specific applications. In this paper, a new digital current controller is presented that operates as a virtual analog hysteresis current controller, taking advantage of a high-performance analog-to-digital converter (ADC) and a field-programmable gate-array (FPGA) circuit implementation. It is designed as a nonlinear current error filter and requires a considerable oversampling factor, as compared with the natural synchronous sampling of pulsewidthmodulation (PWM)-based current controllers. It overcomes the typical limitations of conventional hysteresis controllers, guaranteeing regulated switching frequency, with a few percent accuracy in the steady state, together with minimum sensitivity to dead times, sampling, and computation delays. The paper organization comprises, in the first place, the detailed explanation of the algorithm operation and of its design criteria. Successively, the effectiveness of the proposed solution is verified, first through simulations and then on a 3-kVA single-phase fullbridge inverter. Experimental results are presented that allows assessing the static and dynamic performances of the controller. II. C URRENT C ONTROLLER O PERATION In this section, the operation of the proposed current controller is explained. As shown in Fig. 1(a), the controller
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the converter’s output (i.e., no three-level modulation is considered). Suitable dead times have to be applied to prevent cross conduction, whose impact on the current controller’s performance is analyzed in one of the following sections. It is worth mentioning that application to three-phase inverters is possible as well, requiring only to separate the common-mode interacting current from the measured current for each phase, as discussed, for example, in [15], [17], and [20]. Converter output voltage vO is considered to be an exogenous input; it is typically ac, but a dc output voltage is possible as well. In the former case, its frequency can be considered varying in a range between 50 and 400 Hz. This comprises several inverter applications, including controlled rectifiers, active filters, electrical drives, and grid interface converters for renewable energy sources. In the latter case, the inverter is functionally equivalent to a bidirectional dc–dc converter. A. Fixed-Frequency Hysteresis Current Control Referring to Fig. 1(a) and (b) and considering a single modulation period of duration Ts = 1/fs , the following current error dynamic equation can be written: 1 d iLREF (t) d iL (t) = (vI (t) − vO (t)) − dt L dt
(1)
where iL (t) = iL (t) − iLREF (t) is the current error, vI (t) = ±VDC is the inverter applied voltage, and t ∈ [0, Ts ]. Assuming that both current reference iLREF and output voltage vO are slowly varying during the modulation period, the expression of the current error slope can be written as ±VDC − vO (0) d iLREF (t) ± ± ∼ − (2) s (t) = s (0) = L dt t=0 Fig. 1. Basic organization of controller and converter hardware. (a) Current error acquisition and processing circuit structure. (b) Basic schematic of the considered full-bridge inverter test bench. (c) Simplified schematic of the FPGA circuit organization with main control signals.
operates on continuously acquired current error samples. The sampling period Tclock is N times smaller (with N even) than the desired switching period Ts∗ , which defines N as the oversampling factor of the controller. Samples are processed by a digital FPGA synthesized circuit to generate the logic switching commands for the power converter. No other analog input signal or analog processing, either at the input or at the output, is required to operate the controller. Indeed, differently from several previous approaches, such as [4], [14]–[17], and [20]–[22], the solution presented in this paper is fully digital and has a minimum component count. At the same time, it retains the flexibility of programmable logic hardware, which allows easy adaptation to different dc–dc and dc–ac converter topologies. In the following discussion, a single-phase full-bridge inverter, schematically represented in Fig. 1(b), is taken into account as an application example, in both the simulations and the experimental tests. It is assumed that the switches are controlled to impose either +VDC or −VDC voltage at
where all variable quantities are assumed to be well approximated by their initial values (i.e., taken at t = 0, the beginning of the modulation period). Defining the instantaneous modulation index as m(t) =
d iLREF (t) dt
vO (t) + L VDC
(3)
at any modulation period, the current error slopes (2) can be rewritten as VDC (±1 − m(0)) . s± ∼ = s± (0) = L
(4)
From (4), it is now immediate to prove that the current error peak amplitude or threshold β ∗ that determines the desired duration of the modulation period Ts∗ is given by β∗ =
VDC Ts∗ 1 − m2 (0) . 4L
(5)
Equation (5) proves that, if constant switching frequency is desired, the current error threshold β ∗ has to be continuously adjusted to compensate the modulation index variations determined by nonconstant current reference and/or output voltage, as per (3). We will now see how this general principle is exploited in the proposed controller.
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update circuit. The subcircuit calculates the new threshold level according to the following equation: β − (k − 1) = −
Fig. 2. Internal variable evolution and control algorithm operation in ideal conditions (i.e., with no errors in threshold application). The sampling clock period is Tclock = Ts∗ /N , where N is the oversampling ratio of the controller. Synchronization pulses occur at each counter’s midcount value, i.e., with a period equal to Ts∗ /2.
B. Proposed Controller’s Operation The logic of the control algorithm can be explained referring to Figs. 1(c) and 2. The former shows the simplified internal organization of the FPGA circuit that implements the algorithm. The latter instead shows the current error signal evolution in a few control cycles around the generic kth iteration of the algorithm, determined by a wrong hysteresis threshold positioning at instant t0 = (k − 2)Tu∗ /2. To explain, as simply as possible, how the controller brings the current trajectory back to its ideal course, represented by the dashed line, Fig. 2 assumes that no switch dead times or other errors induced by data quantization affect the circuit operation. As aforementioned, the algorithm’s purpose is to mimic an analog hysteresis controller. In addition, it is designed to synchronize the current error zero-crossing instants with a predefined pulse sequence, i.e., the synch pulses in Fig. 2, whose frequency is twice the desired converter switching frequency. To achieve this, at any sampling clock front, occurring N times in a Ts∗ period, a new current error sample is acquired and processed in parallel by the two detection blocks of the FPGA circuit, as highlighted in Fig. 1(c). Their purpose is to verify if either a zero- or a threshold-crossing condition has occurred. If neither has taken place, the circuit state remains unaltered, and it just keeps waiting for a new sample. Otherwise, the appropriate subcircuits are triggered, as explained in the following. 1) Zero-Crossing Detection: If a zero crossing is detected, one of the two threshold update subcircuits is triggered, depending on the current error slope. Indeed, a key feature of the proposed control strategy is the use of independently regulated positive and negative hysteresis thresholds. Differently from [17] and due to the FPGA hardware capabilities, at the time of current error zero crossing, only the threshold the current error is directed to is adjusted. As an example, in Fig. 2, at instant t1 , the zero-crossing detector triggers the negative threshold
Ts∗ − 2 Terr (k − 1) ∗ ·β Ts∗
(6)
that can be derived immediately from simple geometrical considerations on the similarity of triangles. In (6), Terr (k − 1) represents the synchronization error of the last completed switching half-period, which is the time distance between the zero-crossing instant and the most recent synchronization pulse. In order to measure Terr , the threshold update circuit takes advantage of two timers, both with clock period equal to Tclock = Ts∗ /N , respectively associated to the positive [run-up (RU)] and negative [run-down (RD)] slope zero crossings. The timers’ setting is such that: 1) they are reset when the target modulation period Ts∗ has elapsed; and 2) there is a half-period Ts∗ /2 delay between them. When the zero-crossing condition occurs, both timers are read and the synchronization error is calculated, as an integer number of clock periods, according to the following relation: Ts∗ Terr (k − 1) = CountRD (k − 1) − Tclock 2 Tclock
(7)
where CountRD (k − 1) is the reading of the timer at the (k − 1)th algorithm iteration, as indicated in Fig. 2. To finalize the calculation of (6), the threshold β ∗ , which is actually unknown, has to be determined as well. Because β ∗ experiences only negligible variations in a Ts∗ /2 interval, the most recently adjusted value of the opposite current error threshold can be used to determine it. Indeed, again for the similarity of triangles, we find β ∗ = β + (k − 2) ·
Ts∗ + 2 THP (k − 1)
(8)
+ where THP (k − 1) represents the measured duration of the last completed switching half-period, which is the time distance between two consecutive zero crossings of the current error (the superscript indicating that it is occupied by the positive phase + (k − 1), the timers are of the current error). To determine THP used once again. Indeed, + (k − 1) THP = CountRU (k − 1) − CountRU (k − 2) Tclock
(9)
where CountRU (·) is the reading of the timer at the indicated + algorithm iteration. Once THP (k − 1) is measured, substituting (8) into (6) yields the following final relation: β − (k − 1) = −
Ts∗ 2
− Terr (k − 1) + · β (k − 2). + THP (k − 1)
(10)
As can be inferred from Fig. 2, (10) guarantees that the next current error zero crossing will be synchronized with the following synch pulse at instant t2 = kTs∗ /2. A perfectly symmetrical expression is used by the other subcircuit to calculate, at the next iteration, the adjusted value of the positive current error threshold β + (k) based on the RU phase synchronization error (i.e., Terr (k) ∼ = 0) and the half-period duration in the negative
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4) threshold saturation; 5) sampling noise;
Fig. 3. (a) Internal variable evolution and control algorithm operation in the presence of dead times and quantization effects, determining applied threshold amplitude errors. (b) Details of (a) where the deadtime-induced threshold error is magnified. − error phase (i.e., THP (k)). When the algorithm reaches the steady state, the current error zero crossings are in phase with the corresponding synchronization pulses, and therefore, the switching period matches the target value Ts∗ . A remarkable advantage of (10) with respect to other frequency regulation strategies, such as [18] and [22], or others directly based on (5) is that it is completely insensitive to possible variations of system parameters (e.g., VDC and L). Indeed, it totally relies on time interval measurements. 2) Threshold-Crossing Detection: The thresholdcrossing subcircuit is in charge of checking the relation between the current error sample and the hysteresis thresholds β + and β − . When the current error sample crosses one of them, the appropriate switching action is commanded to determine the current error slope reversal. At the same time, the measurement of the threshold error is initiated. Indeed, in the practical implementation, the current error slope reversal can be delayed with respect to the threshold crossing instant, basically due to the acquisition delay and to inverter dead times, as shown in the insets in Fig. 3. The measurement of the threshold error is used by the threshold update circuits to correct the threshold level, as explained in the following.
C. Compensation of Controller’s Nonidealities The previously explained frequency regulation algorithm is exposed to different systematic and random error sources. The main ones are represented by: 1) ADC delay; 2) inverter dead times; 3) finite counter resolution;
that will now be examined in more detail. 1) ADC Delay and Dead Times: The virtualization of the hysteresis comparator, replaced by a numerical comparison between the current error and hysteresis threshold values, introduces uncertainty in threshold-crossing detection and a randomly variable delay in switch commutations. Both effects are due to the quantization of the current error. A similar effect is caused by dead times, which, however, determine a more systematic and much larger error. Altogether, these effects can be indicated as threshold errors. Their compensation is mandatory to achieve high-quality switching frequency regulation and to keep zero average current error. To this purpose, when a threshold is crossed, the detector starts calculating and storing the difference between the new incoming current error samples and the last crossed threshold level until it detects a slope reversal. The last measured difference represents the threshold error, indicated as Δβ ± (·) in Fig. 3. From this standpoint, the digital implementation of the hysteresis controller is advantageous with respect to the analog one, where the threshold error due to dead times has to be determined through interpolation [17] or approximated estimation [20]. The calculated error Δβ ± (·) is then passed to the appropriate threshold update subcircuit, which uses it, at its next activation, to correct the threshold level. As an example, the negative threshold adjustment algorithm, taking into account threshold errors, is modified as −
β (k − 1) = −
Ts∗ 2
− Terr (k − 1) + THP (k − 1)
· β + (k − 2) + Δβ + (k − 2) − Δβ − (k − 3).
(11)
A symmetrical expression applies to the positive threshold. Equation (11) is the one actually calculated by the threshold update circuit. Referring once again to Fig. 3, it is possible to see the different corrections, with respect to Fig. 2 (dashed trace), necessary to compensate for the same initial perturbation of the positive threshold. As shown, the presence of a dead time TD makes the first negative threshold adjustment ineffective in correcting the synchronization error. Threshold error Δβ − (k − 1) is generated that, in turn, generates the synchronization error Terr (k). However, the measurement of Δβ − (k − 1) and Terr (k) allows the algorithm to adjust the positive threshold β + (k) and, in the absence of random threshold errors, to get the synchronization error to zero at the following (k + 1)th zero crossing. Because the last positive half-period duration is still not equal to its reference value, at the (k + 1)th zero crossing, the circuit will actually adjust the negative threshold once again, this time taking into account the dead-time-induced error Δβ − (k − 1). As a result, the negative threshold will be set to a less negative value, with respect to the ideal one, fully compensating the dead-time effect on the average current error. This unsymmetrical threshold positioning allows the current error to keep zero average value, which cannot be guaranteed by setting β + (·) = −β − (·). In this case, the regulation would be
BUSO AND CALDOGNETTO: WIDE-BANDWIDTH DIGITAL CURRENT CONTROLLER FOR CONVERTERS
maintained at the expense of an average current error. Instead, keeping the current error zero crossings synchronized with the reference pulses, zero average current error is guaranteed together with frequency regulation. Finally, it is possible to notice how the disturbance (i.e., the wrong initial positive threshold value) is compensated in one and a half modulation periods, after which the average current error and the frequency error are both back to zero (neglecting the effects of small random threshold errors). 2) Finite Counter Resolution: The choice of Tclock is crucial to the algorithm operation. Indeed, the algorithm time measurements (7) and (9) are obtained as integer multiples of this period, which also represents the uncertainty in the ± . As a result, the algorithm inherently measurement of THP generates limit cycle oscillations (LCOs) even in ideal conditions (no dead times, no quantization or threshold errors). In order to limit the LCO amplitude, the ratio between the target switching period Ts∗ and the clock period must not be set too low. Provided that β ± (·) is represented on more bits than the timing measurements, the minimum oscillation amplitude is easy to predict using (8). It is given by the following relation: ΔβLCO = ±
2 Tclock ∗ 2 · β = ± · β∗ ∗ Ts N
(12)
that can be used as a basic guideline to choose the maximum applicable Tclock . Because β ∗ and the switching period are proportional to each other, (12) proves that the best case cycleby-cycle relative error on frequency regulation is ±2/N . In general, a certain amplification of the LCO amplitude can take place due to threshold errors or other nonlinear effects (e.g., saturations), particularly when the inverter operates close to the maximum modulation index. Therefore, (12) gives just a best case estimation of the steady-state frequency regulation error. On the other hand, increasing the sampling rate and clock resolution beyond a maximum limit, which depends on the slope (4) of the current error and on the resolution of its numerical representation, results in multiple samples falling into the same ADC bin. When this happens, there is no real advantage in further increasing the clock frequency; the uncertainty in zeroor threshold-crossing detections will become higher than Tclock. A criterion to estimate the upper limit of the controller’s clock frequency is given by max fclock =
1 min Tclock
=
VDC 2nbit · Ksense,i · L F SR
(13)
where F SR is the ADC full-scale range and Ksense,i is the current sensor gain; hence, the second term of the product represents the value in amperes of the ADC least significant bit (LSB). The meaning of (13) is that, when the modulation index is zero, the current error slope will be such that one LSB will be added for each clock period to the current error representation. As a result, zero or threshold crossing will be detected with a single clock period uncertainty. Of course, when the modulation index differs from zero, only the steeper (i.e., most critical) zero crossing or threshold crossing in each modulation period will be detected with minimum uncertainty. However, this is generally enough to ensure an excellent performance.
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3) Threshold Saturation: When the converter operates at high modulation index, the conduction interval of either S1 − S3 or S2 − S4 becomes relatively short. The FPGA circuit takes a definite amount of time, which we denote as latency time Tlat , to compute and adjust the current error threshold after each zero crossing of the current error. Therefore, if the RU (or the RD) phase becomes too short, positive (or negative) synchronization errors cannot be corrected rapidly enough, which generates undesired transients. In addition, if the RU phase or the RD phase becomes shorter than twice the dead time TD , the compensation is altogether impossible as thresholds cannot invert their sign. Therefore, the algorithm can operate as described above only up to a maximum modulation index level, which is given by TD Tlat (14) Mmax = min 1 − 4 ∗ , 1 − 4 ∗ Ts Ts where Tlat is equal to 550 ns in our hardware, determining a 0.956 maximum modulation index. To prevent undesired oscillations of thresholds when the modulation index tends to become higher than (14), a saturation strategy needs to be implemented. In our case, any time the calculated threshold becomes lower than a predefined minimum, a fixed threshold regime is entered; specifically, the last nonsaturated threshold value is applied until the modulation index reduces and threshold calculation no longer results into too small values. Of course, frequency regulation is lost during saturation, but due to the unsymmetrical threshold positioning, average current control can be maintained. 4) Sampling Noise: The current controller operates comparing current samples to thresholds and measuring zerocrossing synchronization errors. Therefore, a good signal-tonoise ratio (SNR) in the current error sampling process is mandatory to achieve satisfactory performance levels. The circuit can be made somewhat tolerant to input injected noise by introducing hysteretic nonlinearities in the zero- and thresholdcrossing detection subcircuits and, sacrificing some bandwidth, by implementing an input digital denoising filter. Nevertheless, if the noise level is too high, the resulting jitter in the zeroand threshold crossing detections will rapidly deteriorate the performance. To estimate the controller robustness, simulations have been performed, injecting white noise of increasing power at the ADC input. Doing so, it was possible to verify that excellent frequency stabilization capabilities can be obtained as long as the ADC output SNR is above 60 dB or, in other words, the controller operates on at least 10 effective bits in the current error representation; in the simulation, an average error below 1% has been achieved, with an adequate value of N . To guarantee this SNR level, care must be taken in the acquisition board design and layout. Analog filters can be used as well, but their frequency response needs to be carefully shaped to avoid significant current error waveform distortion. III. S IMULATION R ESULTS The current control algorithm detailed above has been simulated considering its application to a single-phase dc–ac
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TABLE I C ONVERTER PARAMETERS
converter [see Fig. 1(b)] with the parameters listed in Table I. The simulation model includes all the systematic (i.e., switch dead times) and random error sources aforementioned and replicates the FPGA circuit operation with the maximum accuracy. Random noise is injected at the circuit input that corrupts the lowest 2 bits of the current error sampled value. Simulation results are shown in Fig. 4, which considers operation when a 20-A-peak 50-Hz-sinusoidal-current reference is applied. The three upper plots refer to a 0.96 maximum modulation index, which, according to (14), determines saturation in the vicinity of the current peaks. This condition is hardly encountered in practice, but it is considered in simulations to verify the capability of the controller to manage the saturation of thresholds. It is possible to see how, during saturation, frequency regulation is lost, with a decrease to about 15 kHz, but the current error average value is correctly kept to zero. The bottom plot instead shows the instantaneous frequency regulation error in a 100-ms interval, at 0.82 maximum modulation index, corresponding to the nominal inverter operating conditions in Table I. As shown, the peak frequency deviation has zero average and is almost everywhere smaller than 3%, with an RMS value equal to 3.2%. According to (12), this is consistent with the choice N = 100. Every 10 ms, the algorithm needs to correct severer threshold errors, occurring on the dead-time affected current peak because of the relatively high modulation index. This causes the instantaneous error bursts visible in the plot. When needed, better results can be obtained increasing the oversampling rate N . IV. D IGITAL C ONTROLLER E XPERIMENTAL T EST The previously described controller has been synthesized into an FPGA chip, namely, a Xilinx Spartan-6 LX45, available within the general-purpose inverter control board [25] currently used at our laboratory. The control board is coupled to a custom-designed acquisition daughterboard, featuring a 12-bit 65-MS/s-peak ADC (AD9226). In an attempt to maximize the SNR, the acquisition channel uses an ohmic sensor and a lownoise fully differential amplifier (AD8138). Acquired data are passed to the control board through high-speed magnetically isolated digital gates. To improve the SNR of the input signal, in addition to what has been presented in the previous sections, a four-sample moving average input filter is implemented in the FPGA circuit. Error sample processing is performed using multiple 16-bit fixed-point arithmetic units. The total chip occupation is nonetheless relatively low; less than 7% of available
Fig. 4. Simulated inverter current and internal variable evolution with 20-A-peak 50-Hz-current reference and 0.96 peak modulation index. (a) Inverter current. (b) Steady-state internal variable evolution with saturation. (c) Zoomed-in view at the beginning of the saturated regime (indicated by the box). (d) Instantaneous frequency regulation error at 0.82 peak modulation index (nominal conditions).
resources are used, namely, four DSP units, used in threshold update subcircuits to perform the divisions required by (11), and about 450 combinatorial and sequential logic blocks. The controller, therefore, is compatible with much smaller FPGA chips. The FPGA circuit and the control parameters are summarized in Table II, whereas a picture of the inverter and controller assembly is shown in Fig. 5. Both small- and largesignal response tests have been performed, whose results are described hereafter.
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TABLE II C ONTROLLER PARAMETERS
Fig. 5. Control boards, i.e., analog (in the white box) and digital [25], connected to the 3-kVA inverter used for the experimental tests.
Fig. 7. Controller’s response to current reference step variations. (a) DC current reference step variation from −7 to +7 A. (b) AC current peak reference step variation from 0 to 12 A.
performed on a numerical simulation model of the controller. As shown, in the considered frequency span, the amplitude response is practically flat, whereas just a small phase lag, about −3◦ , is measured at 3 kHz. This type of response is clearly much better than what any linear PWM-based current controller operating at the same modulation frequency (20 kHz) can get. In addition, it appears to be in good agreement with the result presented in [21], where a purely analog implementation of the hysteresis current controller, with 9.5 kHz switching frequency, is considered. B. Large-Signal Controller’s Performance Fig. 6. Controller’s small-signal response in magnitude and phase. (Solid) Experimental data are compared with (dashed trace) numerical simulation data.
A. Small-Signal Controller’s Performance In order to evaluate the controller small-signal performance, a constant reference current has been applied to which a ±5% sinusoidal perturbation has been summed. The perturbation frequency has been progressively increased from 10 Hz to 3.5 kHz. The resulting inverter current has been acquired and analyzed by discrete Fourier transform. The spectral component at the perturbation frequency has been extracted, thus determining the magnitude and phase response of the controller, as shown in Fig. 6. To validate the measurement, the same test has been
The controller’s response to current reference step variations is shown in Fig. 7, both for dc [see Fig. 7(a) and (b)] and ac current reference signals. As shown, in both cases, the transient response is close to ideal, as the inverter keeps powering up the inductor for the exact time needed to track the new reference current. Then, it immediately resumes modulation with the correct steady-state duty cycle. As a result, the average converter current settles onto the new reference in the minimum time compatible with the available converter hardware. In the case in Fig. 7(b), after the transient, the converter operates with a 50-Hz 230-V (RM S) sinusoidal load voltage, which determines a 0.82 maximum modulation index, reached at each peak of the sinusoidal current reference. The resulting steady-state current total harmonic distortion is 1.47%. To illustrate the quality of frequency regulation, Fig. 8(a) shows the statistical distribution
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frequency effect that typically characterizes hysteresis current controllers yet minimizing analog signal processing. This is limited to what is strictly required for the current error signal acquisition. Accordingly, no DACs or analog comparators are required. Its operation results into an almost constant switching frequency in the steady state and, at the same time, into the wide small-signal bandwidth and minimum large-signal response delay typical of nonlinear controllers. Its performance is demonstrated on a 3-kVA voltage source inverter switching at 20 kHz and using a 100 oversampling factor.
R EFERENCES
Fig. 8. Controller’s instantaneous frequency regulation in 2 · 103 control cycles during the ac transient experiment in Fig. 7(b). (a) Statistical distribution of the relative switching frequency regulation error. (b) Instantaneous relative frequency regulation error.
of 2000 instantaneous frequency error samples, recorded at each switching period during the ac transient experiment in Fig. 7(b). The samples are normalized to the target switching frequency value of Table II. As shown, despite the transient, close to 90% of the samples fall in a ±5% region around the target value. A different view of the same experiment is provided in Fig. 8(b), where the relative instantaneous switching frequency regulation error is shown against time. Because no commutations are performed during the transient, a large frequency regulation error is visible at t = 35 ms, which is rapidly recovered when the current reaches the steady state. It is possible to see how the frequency regulation error has maximum energy in the ±2% region, corresponding to the highest bars in Fig. 8(a). Finally, the increase in the inverter maximum modulation index, after the transient, determines the slightly higher density of regulation errors due to the severer threshold errors occurring at each current peak every 10 ms, with maxima around ±10%, pretty much like what Fig. 4(d) shows. V. C ONCLUSION A nonlinear wide-bandwidth digital current controller for dc–dc and dc–ac converters has been presented in this paper. The controller is designed to approximate the steady state and dynamic performance offered by an analog hysteresis current controller. It is implemented on an FPGA chip and exploits the oversampling of the current error signal allowed by a fast ADC. In addition, it effectively compensates the variable switching
[1] A. Borrell, M. Castilla, J. Miret, J. Matas, and L. G. de Vicuna, “Simple low-cost hysteretic controller for multiphase synchronous buck converters,” IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2355–2365, Jun. 2011. [2] S. C. Huerta et al., “Nonlinear control for DC–DC converters based on hysteresis of the COUT current with a frequency loop to operate at constant frequency,” IEEE Trans. Ind. Electron., vol. 58, no. 3, pp. 1036–1043, Mar. 2011. [3] F. Su, W. H. Ki, and C. Y. Tsui, “Ultra fast fixed-frequency hysteretic buck converter with maximum charging current control and adaptive delay compensation for DVS applications,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 815–822, Apr. 2008. [4] R. Ramos, D. Biel, E. Fossas, and F. Guinjoan, “A fixed-frequency quasisliding control algorithm: Application to power inverters design by means of FPGA implementation,” IEEE Trans. Power Electron., vol. 18, no. 1, pp. 344–355, Jan. 2003. [5] W. T. Yan, C. N. M. Ho, H. S. H. Chung, and K. T. K. Au, “Fixedfrequency boundary control of buck converter with second-order switching surface,” IEEE Trans. Power Electron., vol. 24, no. 9, pp. 2193–2201, Sep. 2009. [6] S. Maity and Y. Suraj, “Analysis and modeling of an FFHC-controlled DC–DC buck converter suitable for wide range of operating conditions,” IEEE Trans. Power Electron., vol. 27, no. 12, pp. 4914–4924, Dec. 2012. [7] F. Wu, F. Feng, L. Luo, J. Duan, and L. Sun, “Sampling period online adjusting-based hysteresis current control without band with constant switching frequency,” IEEE Trans. Ind. Electron., vol. 62, no. 1, pp. 270–277, Jan. 2015. [8] S. J. Cheng, Y. K. Lo, H. J. Chiu, and S. W. Kuo, “High-efficiency digital-controlled interleaved power converter for high-power PEM fuelcell applications,” IEEE Trans. Ind. Electron., vol. 60, no. 2, pp. 773–780, Feb. 2013. [9] D. G. Holmes, B. P. McGrath, and S. G. Parker, “Current regulation strategies for vector-controlled induction motor drives,” IEEE Trans. Ind. Electron., vol. 59, no. 10, pp. 3680–3689, Oct. 2012. [10] N. A. Azeez et al., “A medium-voltage inverter-fed IM drive using multilevel 12-sided polygonal vectors, with nearly constant switching frequency current hysteresis controller,” IEEE Trans. Ind. Electron., vol. 61, no. 4, pp. 1700–1709, Apr. 2014. [11] A. Dey, P. P. Rajeevan, R. Ramchand, K. Mathew, and K. Gopakumar, “A space-vector-based hysteresis current controller for a general n-level inverter-fed drive with nearly constant switching frequency control,” IEEE Trans. Ind. Electron., vol. 60, no. 5, pp. 1989–1998, May 2013. [12] Y. Ounejjar, K. Al-Haddad, and L. A. Dessaint, “A novel six-band hysteresis control for the packed U cells seven-level converter: Experimental validation,” IEEE Trans. Ind. Electron., vol. 59, no. 10, pp. 3808–3816, Oct. 2012. [13] T. Ghennam, E. M. Berkouk, and B. Francois, “A novel space-vector current control based on circular hysteresis areas of a three-phase neutralpoint-clamped inverter,” IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 2669–2678, Aug. 2010. [14] B. K. Bose, “An adaptive hysteresis-band current control technique of voltage-fed PWM inverter for machine drive system,” IEEE Trans. Ind. Electron., vol. 37, no. 5, pp. 423–430, Oct. 1990. [15] Q. Yao and D. G. Holmes, “A simple, novel method for variablehysteresis-band current control of a three phase inverter with constant switching frequency,” in Conf. Rec. IEEE IAS Annu. Meeting, 1993, pp. 1122–1129.
BUSO AND CALDOGNETTO: WIDE-BANDWIDTH DIGITAL CURRENT CONTROLLER FOR CONVERTERS
[16] K. M. Rahman, M. R. Khan, M. A. Choudhury, and M. A. Rahman, “Variable-band hysteresis current controllers for PWM voltage-source inverters,” IEEE Trans. Power Electron., vol. 12, no. 6, pp. 964–970, Nov. 1997. [17] S. Buso, S. Fasolo, L. Malesani, and P. Mattavelli, “A dead-beat adaptive hysteresis current control,” IEEE Trans. Ind. Appl., vol. 36, no. 4, pp. 1174–1180, Jul./Aug. 2000. [18] C. N. M. Ho, V. S. P. Cheung, and H. S. H. Chung, “Constant-frequency hysteresis current control of grid-connected VSI without bandwidth control,” IEEE Trans. Power Electron., vol. 24, no. 11, pp. 2484–2495, Nov. 2009. [19] J. C. Olivier, J. C. Le Claire, and L. Loron, “An efficient switching frequency limitation process applied to a high dynamic voltage supply,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 153–162, Jan. 2008. [20] D. G. Holmes, R. Davoodnezhad, and B. P. McGrath, “An improved threephase variable-band hysteresis current regulator,” IEEE Trans. Power Electron., vol. 28, no. 1, pp. 441–450, Jan. 2013. [21] J. C. Olivier, J. C. Le Claire, F. Auger, and L. Loron, “Improved linear model of self oscillating systems such as relay feedback current controllers,” Control Eng. Practice, vol. 18, no. 8, pp. 927–935, Aug. 2010. [22] L. Fangrui and A. I. Maswood, “A novel variable hysteresis band current control of three-phase three-level unity PF rectifier with constant switching frequency,” IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1727–1734, Nov. 2006. [23] D. Grant, “Frequency control of hysteretic power converter by adjusting hysteresis levels,” U.S. Patent 634 8780, Feb. 19, 2002. [24] A. Mihalka, “Fixed frequency hysteretic regulator,” U.S. Patent 6 885 175, Apr. 26, 2005. [25] National Instruments Single Board RIO—General Purpose Inverter Controller. [Online]. Available: http://www.ni.com/singleboard/gpic/
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Simone Buso (M’97) received the M.Sc. degree in electronic engineering and the Ph.D. degree in industrial electronics from the University of Padova, Padua, Italy, in 1992 and 1997, respectively. He is currently an Associate Professor of electronics with the Department of Information Engineering (DEI), University of Padova. His main research interests are in the industrial and power electronic fields and are specifically related to switching converter topologies, digital control of power converters, solid-state lighting, and renewable energy sources.
Tommaso Caldognetto (S’10) received the M.Sc. degree (with honors) in electronic engineering in 2012 from the University of Padova, Padua, Italy, where he is currently working toward the Ph.D. degree in the Department of Information Engineering (DEI), Graduate School of Information Engineering. In 2014, he was a Visiting Ph.D. Student at the Institute for Automation of Complex Power Systems, RWTH Aachen University, Aachen, Germany. His research interests include control of grid-tied converters, microgrid architectures, and real-time simulation for power electronics.
