a digital hysteresis loop to control the current which gives the disadvantage of carrierless switching frequency. A proper power converter design may be difficult.
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Improved Digital Current Control Methods in Switched Reluctance Motor Drives Frede Blaabjerg, Senior Member, IEEE, Philip C. Kjaer, Member, IEEE, Peter Omand Rasmussen, and Calum Cossar
Abstract— This paper proposes a method to avoid current feedback filters in fast digital-based current loops in switched reluctance drives. Symmetrical pulsewidth modulation (PWM) and synchronized sampling of the phase current allow a noisefree current sampling with no antialiasing filter. This paper also proposes more efficient methods to chop the two transistors in the asymmetric inverter used with switched reluctance drives. A fast field-programmable gate array (FPGA)-based test system is used for validation of the new methods. Test results show a significant improvement in dynamic and steady-state current loop control compared with traditional methods. The new chopping method is found to reduce the switching losses and increase the drive efficiency. Index Terms— Control, FPGA, noise-free sampling, switched reluctance drives.
I. INTRODUCTION
O
NE OF THE possible electrical machines in new modern variable-speed and servo drives is the switched reluctance motor (SRM). It is one of the first invented machines, but the applications have been limited due to the lack of control electronics and fast switching power devices. During the last 15 years, some industrial applications have appeared and many efforts have now been made to improve the total performance of switched reluctance drives. The major reasons for the use are the development of microcontrollers and power electronic devices. The main advantages of the switched reluctance drives are simple construction, low-inertia, high-speed performance, low costs, and fault tolerance. Some of the important disadvantages are that the drives emit acoustical noise, need a converter, are nonlinear, and information about the rotor position to make a proper control scheme is necessary. Control of the switched reluctance motor can be done in different ways. Basically, there exist three different modes of operation, namely, voltage control, current control, and single pulse control [1]. The current control method is normally used to control the torque efficiently, while single-pulse mode is entered for high-speed operation. Voltage control has no limitation of the current as the current sensor is avoided, which makes it applicable in low-cost systems. Due to the Manuscript received December 29, 1997; revised September 30, 1998. Recommended by Associate Editor, A. Trzynadlowski. F. Blaabjerg and P. O. Rasmussen are with Aalborg University, Institute of Energy Technology, DK-9220 Aalborg East, Denmark. P. C. Kjaer is with the Department of Power Engineering, ABB Corporate Research, V¨asteraas, Sweden. C. Cossar is with the SPEED Laboratory, Department of Electronics and Electrical Engineering, University of Glasgow, Glasgow, U.K. Publisher Item Identifier S 0885-8993(99)03760-6.
development of microcontrollers, the different control loops have changed from analog to digital implementation, which allows more advanced control features. However, problems still arise when designing high-performance current loops [2]–[4]. Design of digital current loops for switched reluctance motors can be done in different ways. One method is to use a digital hysteresis loop to control the current which gives the disadvantage of carrierless switching frequency. A proper power converter design may be difficult. If the hysteresis loop is done analog, it is very simple, but it is difficult to measure or to have knowledge of the impressed voltage or flux. The alternative solution is a fixed switching frequency operation with a classical controller for the current. One of the problems in this design is the need of a feedback filter due to the current ripple, and it limits the current loop bandwidth. This paper proposes a method to avoid current feedback filter in fixed switching frequency operation with digital current controllers, exemplified on a switched reluctance drive, but it may also be used in other applications. The paper also proposes an alternative way to control the transistor chopping in the asymmetrical SRM inverter. First, general control methods of the SRM and different ways to control the current in the SRM are described. Next, the new control methods will be explained. A test system is implemented, and experimental results verify the concept in detail. II. CONTROL
OF
SRM
Current control can be helpful in applications with or without a position sensor. The benefits are complete output protection of the inverter, easy implementation of advanced control methods like minimum torque ripple control, and fast dynamic performance, if that is necessary. A. Operation with Position Sensor A switched reluctance drive can be controlled in different ways, and Fig. 1 shows the block diagram representation of a three-phase SRM drive with a position sensor and an asymmetrical half-bridge inverter. The control unit consists of a commutation control [turn, turn-off angle , and pulsewidth modulation on angle (PWM) duty cycle ], a speed controller, and if the drive uses current control, a controller for the phase currents. Feedback and speed , and in current signals are the position control, the phase currents will also be measured. In many applications, the position signal is used to calculate the speed.
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Fig. 1. Control principle of a switched reluctance drive with sensor.
Fig. 2. Switched reluctance drive with position and speed observer.
B. Operation Without Position Sensor Different schemes without sensors are seen in the literature, and in [7] and [8] a number of possibilities are listed. One option is to use an observer to estimate the position on line. That solution takes advantage of fast modern signal processors where it is convenient to implement as much as possible in digital software. Fig. 2 shows such a scheme. In an observer-based scheme, the phase currents and the applied phase voltages are normally used to calculate the flux linkage and then the position and the speed. The dc link voltage and the duty cycle are used to calculate the output voltage from the converter to the SRM. In order to control the speed, the observer should fulfill both dynamic as well as steady-state requirements. In general, the inner loop of current control is important, and as illustrated in Fig. 2, accurate knowledge of the applied phase voltage is also important [8]. In the next paragraphs, only current control will be treated in order to fulfill the generated current reference from other controllers and observers. That means the torque ripple, acoustic noise, speed performance, and motor efficiency will be fractional affected by improving the current control. The main impact can be on the switching losses and capacitor losses in the inverter. III. CURRENT CONTROL
OF
SRM
Three typical current controllers will be discussed here. They are hysteresis control in analog implementation, delta modulation with fixed switching frequency in a digital implementation, and the classical linear control method with fixed switching frequency operation. The major difficulty when designing SRM current controllers is that the winding back electromotive force (emf) and electrical time constant vary significantly within one electrical cycle and with the
Fig. 3. Simple control model for current control of the SRM.
motor speed and phase current level. The voltage equation of the SRM is given as
(1) where applied phase voltage; phase winding resistance; phase current; phase flux linkage; phase back emf; phase inductance; angular speed; angle position of rotor. Equation (1) indicates a nonlinear model which is dependent on position, current, and speed. Fig. 3 shows the control model for the current controller in the SRM. The electrical time constant of a phase winding and the back emf vary strongly with current and rotor position and an analog hysteresis current loop is robust to use. The two
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(a)
Fig. 4. Current control in switched reluctance drive. (a) Analog hysteresis control. (b) Digital hysteresis control (delta modulator). (c) Digital linear control with fixed switching.
alternatives are digitally controlled, and all three possibilities are illustrated in Fig. 4. The analog hysteresis control is simple, but it has the disadvantage of variable switching frequency, which may cause a subsonic noise in the SRM. The design of the power converter becomes more difficult, and if information about the phase voltage is necessary for control (see Fig. 2), a direct voltage sensor is difficult to avoid. A digital solution (microcontroller or digital signal processor) for hysteresis control (delta modulation) presents the same disadvantages as analog hysteresis control except better information about the voltage may be obtained by the control signal (ON, OFF). between each sampling instant gives Integration of the flux linkage in the winding. However, fixed frequency delta modulation often results in higher current ripple than the digital linear controller with fixed sampling and switching frequency. This third solution gives a better basis for the converter design, acoustic noise prediction, and knowledge of the voltage. However, the dynamics of the current loop will be limited by the sampling time and a filter to smoothen out the current ripple caused by the switching frequency. It is an important limitation which may result in a limited bandwidth. Fig. 5 shows the effect of the sampled current with and without current filter in the feedback. The filter is normally designed as an antialiasing filter with a corner frequency at least two times lower than the sampling frequency. Fig. 4(c) shows the definitions of the signals. The signal indicates the sample time, is the sampled current, and is the switching period. The PWM signal is generated as singleended modulation. A proportional–integral (PI) controller or a proportional–integral–differential (PID) controller can be used in the design.
(b) Fig. 5. Current feedback signals from fixed switching frequency. (a) With current filter. (b) Without current filter.
Fig. 5 shows that the measured current is smoothened out very much by a filter, while if the current filter is avoided, aliasing appears on the ripple current and therefore it can be concluded the filter is difficult to avoid. If the filter is used, it will reduce the bandwidth of the controller significantly. IV. CURRENT CONTROL WITHOUT FILTER In traditional vector modulation for three-phase voltagesource-inverter drives, the solution to avoid filters in the feedback of the current loops is to sample during the zerovector states because no transistor switching noise is present. Even better is to sample in the center of a symmetrical modulation (also zero vector in three-phase inverter) because this gives an arithmetic correct average noise-free current sampling [5], [6]. The difference between single-ended modulation and double-sided modulation is illustrated in Fig. 6. Two singleended modulation strategies and one double-sided modulation strategy are shown. Typically, they are implemented in a timer which is running from a CLOW value to a CHIGH value. value, a change When the timer reaches a precalculated . In a double-sided strategy, on the output is performed the timer both counts up and down. It will then match two times and a symmetrical modulation is realized. The last modulation method can solve important problems in switched reluctance drives even though it is not a three-phase system. Fig. 7 shows the proposed principle and a possible realization. Practically, if the duty cycle is too small, some noise may appear in the current sampling. This can be avoided by
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(a)
(b)
(c)
Fig. 6. Different digital PWM techniques. (a) Single-ended modulation (leading edge). (b) Single-ended modulation (lagging edge). (c) Double-sided modulation (symmetrical).
(a)
(b) Fig. 7. Current sampling without current feedback filter. (a) Signals in the SRM system with symmetrical PWM. (b) Digital implementation of current loop.
operating with a minimum duty cycle and zero duty cycle. If the other phases are controlled at the same time, the PWM and the sampling time may be synchronized. Otherwise, there is a high risk of noise in the measurement. In practical implementations with digital electronics, it is possible to make this synchronization. V. SOFT
AND
current ripple and switching losses. However, it has been recommended that hard chopping is employed for braking operation to keep the current controllable. It was initially believed that efficient use of soft chopping was difficult with current-regulated PWM as the voltage demand for this linear controller was both positive and negative and changing very quickly. However, the zero-voltage loop can equally well be used for soft chopping between and and zero. This is shown schematically zero as between for a single phase of the converter in Fig. 8. When a positive is chopped and is constant on. The voltage is used, is then applied across the phase winding when voltage is on and the winding is short circuited by when is off. This is shown in Fig. 8(a). When a negative voltage has to be is off all the time and is chopping as shown in applied, across the phase winding. Fig. 8(b). The result is 0 V and The implementation of this in current-regulated PWM is not very demanding, as will be shown. A PI controller outputs a reference voltage between and . The modulator must translate this reference into a duty cycle. This duty cycle varies between 0 (corresponding ) and 1 (corresponding to ). The PWM signals to are generated by comparing the duty cycle to a triangular (or sawtooth) carrier wave running from zero to one. Hence, the duty cycle produced by the PI controller described is readily applicable to hard chopping. To illustrate the different modes in a converter, Fig. 9 shows the average voltage across the phase winding as a function of duty cycle. When hard chopping, the average phase voltage over one switching period is [see Fig. 9(a)]
HARD CHOPPING
Using the classic two-transistor–two-diodes per phase SRM converter, three voltage levels can be used. In hard chopping, and are used, giving the full voltage range. only and zero are used in soft chopping, which often Only suffices for motor operation as the required voltage is always positive between turn on and turn off of a phase. As is well known from standard hysteresis current regulation in SRM drives, using the zero-voltage loop can reduce the
(2)
where average output voltage; duty-cycle soft chopping; duty-cycle hard chopping.
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(b)
Fig. 8. Soft-chopping principle for SRM converter. (a) Positive voltage. (b) Negative voltage.
(a)
(b)
(c)
(d)
v
Fig. 10. Complementary PWM for control of SRM.
D
Fig. 9. Average phase voltage avg versus duty cycle in different modes. (a) Hard chopping. (b) Soft chopping with one transistor always on. (c) Soft chopping with one transistor always off. (d) Relation between soft chopping ( SC ) and hard chopping ( HC ).
D
D
In soft chopping, when one transistor is always on and the other is modulated [see Fig. 9(b)], the average voltage becomes (3) If one transistor is always off, the average voltage in soft chopping becomes [Fig. 9(c)] (4) , one If the reference voltage is between zero and transistor should always be on, and if the reference voltage is below zero, one transistor should always be off. This means that two soft-chopping technique can substitute the hard-chopping technique in all modes and linking those two techniques together it is possible to describe what the duty of the soft-chopping techniques should be at a cycles in the hard-chopping technique. It given duty cycle is illustrated in Fig. 9(d). The following relationship will be between the soft- and hard-chopping techniques: if if
(5)
In an implementation using an 8-b modulator, the seven least significant bits (LSB’s) of the duty cycle are simply shifted left
and the most significant bit (MSB) is used to detect whether one transistor should be on or off throughout the PWM period. An even better way to perform current-regulated PWM can be done. Two PWM signals are generated, with 180 phase and bottom displacement. Each signal drives the top transistors, respectively. The resultant phase voltage will be “soft chopped,” with a ripple frequency twice that of the previous schemes, but the power transistors experience the same switching frequency. Fig. 10 shows the principle with a complementary PWM. This scheme has two advantages compared to the previous schemes. 1) The current ripple amplitude is reduced to 50% because the ripple frequency is doubled. 2) The total inverter losses are unchanged, but both conduction and switching losses are evenly distributed between the top and bottom power transistors. This makes the design of the heatsink and the semiconductor device rating much easier. VI. IMPLEMENTATION As a part of a high-performance four-phase SR motor servo drive, a 32-b microcontroller (Motorola MC68332) is used for position, speed, and torque regulation. Apart from the motion control loops, the torque regulation consists of translating a torque reference into individual phase current references. Traditional commutation control [1] is also possible for less demanding applications. To reduce the computational overhead for the microcontroller, the actual phase current regulation is performed externally.
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Fig. 11.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 14, NO. 3, MAY 1999
Experimental setup for test of the current control principle.
(a)
(b) Fig. 12.
Step response on the current at zero speed. (a) Single-ended modulation. (b) Double-sided modulation and sampling.
The digital PI current controllers for all four phases are implemented in a field-programmable gate array (FPGA), connected to fast 12-b analog–digital (A/D) converters (Maxim MAX120) with up to 500-ksps throughput rates. This implementation avoids the drawbacks of conventional analog PI current controllers, and using the FPGA-wired logic has the advantage of very fast execution allowing sampling and control frequencies far greater than a digital signal processor (DSP) software implementation. The FPGA interfaces directly to the A/D converters and controls the timing of the current loops without any intervention from the microcontroller. Essentially, the FPGA uses a hard-wired one-clock-cycle execution of the PI-controller loop (see [9]) making the transistor switching frequency rather than the loop execution delay the limiting
factor for the obtainable bandwidth. The FPGA used for the reported investigation was a Xilinx XC3195A 84-pin device. Options for single-ended and double-sided modulation as well as for soft- and hard-chopping converter operation were implemented and tested on a 3-hp four-phase 8/6-pole SR motor operated from a classic asymmetrical half-bridge insulated gate bipolar transistor (IGBT) inverter topology. An 8-b resolution on the PWM generator was used. The SRM was loaded by a permanent-magnet dc commutator machine (DCM) coupled to a resistive load. A 100-V dc-bus voltage and a 19.3-kHz switching frequency were used. The update frequency from reference torque to reference phase currents was 4.1 kHz. A diagram of the experimental setup is shown in Fig. 11.
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(a)
(a)
(b)
(b)
Fig. 13. Measured phase current, sample time of phase current, and PWM signals using either (a) single-ended modulation or (b) double-sided modulation.
Fig. 15. Phase currents measured in SRM in flat-topped current control with a soft-chopped converter. (a) Single-ended modulation. (b) Double-sided modulation.
(a) (a)
(b) Fig. 14. Two phase currents measured in the SRM running with smooth 3:4 Nm. n = 490 rpm. torque control. Tref
=
(b) Fig. 16. Phase currents measured in SRM in flat-topped current control with a hard-chopped converter. (a) Single-ended modulation. (b) Double-sided modulation.
VII. TEST RESULTS The first test on the SR drive is made at zero speed and a step response on the current is performed from 10 to 15 A. The same PI controller for the current is used. The measurements
are shown in Fig. 12, which demonstrates that an improved response of the current is obtained when symmetrical modulation is used. The response is much more damped.
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(a)
(b) Fig. 17. Measured current waveforms at 714 rpm and 3.4-Nm reference torque at low-torque ripple. The upper and lower power transistor gate signals are also shown. (a) Hard chopping. (b) Soft chopping.
The next tests show the phase current, the sample time of the current (logically low), and the PWM signal. Fig. 13 shows the two cases. It is again at a standstill. Fig. 13 illustrates clearly the effect of sampling in the center of the PWM period with double-sided modulation. No switchings are present when the sampling is performed and a true average current is measured. Note the subharmonic “drift” in the single-ended modulation current waveform. In order to show the improved performance of the proposed control method for operation with multiple phases simultaneously excited, two phase currents are measured for operation with low-torque ripple current waveforms [9]. The reference current will vary, strongly dependent on the position, and a high-performance current loop is necessary. Fig. 14 shows it for the two cases at 490 rpm and a 3.4-Nm reference torque. The reference current update frequency of 4.1 kHz can be seen in the waveforms. Fig. 15 shows the double-sided modulation tracks the reference current better than the single-ended modulation and an improved control is obtained. The measured input power was fractionally higher with the single-ended modulation compared to the double-sided modulation. The phase currents are measured with flat-topped current control in both cases. The converter operates in soft-chopping V). Turn-on angle and turn-off mode (
angle . The SRM runs at 600 rpm, reference A, and the load torque is 3 Nm. The two current cases are shown in Fig. 15. Again, fewer current oscillations are seen in the doublesided modulation with symmetrical sampling. Test results are shown for the same operating point as . Fig. 15, but now the converter is hard chopped Fig. 16 shows the test results. In this case, the improvement with double-sided modulation is more clear than in the case of the soft-chopping mode. The oscillations are limited. The current ripple is also smaller in the soft-chopping mode comparing the measurements in Fig. 15 with Fig. 16. The soft-chopping technique was further tested. Fig. 17 shows experimental current waveforms (lower traces) for lowtorque ripple operation at 714 rpm with 3.4-Nm reference torque. The upper traces show the transistor gate signals. The soft-chopping operation is clear, and the current ripple significantly reduced. In theory, the ripple on the current waveform is expected to be halved, as the inductive voltage for soft chopping and for hard variation is chopping. This also has a positive effect on the audible noise emission as the flux-linkage gradients are “softer.” Ideally, the switching losses should also be halved with this scheme. Conduction losses are affected when changing from hard to soft chopping as the diode and transistor on times are modified.
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Both transistors receive PWM signals at different times, and in this way both the switching and conduction losses may be better distributed. An improvement of 10% in inverter efficiency was observed with the transition from hard to soft chopping. The complementary PWM scheme has not been implemented and tested. However, in summary, the tests conducted and the theory presented reveal that hard chopping, soft chopping, and complementary PWM have the following effects on the asymmetrical half-bridge inverter losses. • The losses of each transistor in hard chopping are equal. The current ripple in hard chopping is the higher than both other schemes. • The chopping transistor experiences higher switching losses than the commutating one in soft-chopping PWM, but fewer conduction losses. • The losses of each transistor in complementary PWM are equal. • The conduction losses are equal for soft-chopping and complementary PWM, but higher than hard chopping. • For the same switching frequency, complementary PWM causes twice the total switching losses of soft chopping, but also half the current ripple amplitude. • For the same current ripple amplitude, complementary PWM can use half the switching frequency of soft chopping, resulting in equal total transistor losses. Both transistors in complementary PWM experience equal losses, and the loss per transistor is smaller than that of the chopping transistor in soft chopping.
VIII. CONCLUSION This paper presented a new method to avoid antialiasing filters in the current feedback sensors in digital current-controlled SRM. By the use of symmetrical sampling and symmetrical modulation in the current control loop, a true average current may be sampled. At the same time, no switching noise will be present at the time of sampling and no filters are necessary. A soft-chopping method is also proposed for the asymmetrical half-bridge inverter which reduces noise and losses in the inverter. An FPGA implementation of the method is made and tested on an SRM servo drive. It is compared with traditional methods and the new current regulator shows significantly improved results. The new chopping mode reduces also the power losses in the inverter by 10%. It can be concluded that the method is applicable to new digitally current-controlled SRM’s. REFERENCES [1] T. J. E. Miller, Switched Reluctance Motors and Their Control. Oxford, U.K.: Clarendon, 1993. [2] C. R. Elliott, J. M. Stephenson, and M. J. Turner, “High performance control of phase current in switched reluctance motor,” in Proc. EPE’95, vol. 3, pp. 223–228. [3] C. Rochford, R. C. Kawanagh, M. G. Egan, and J. M. D. Murphy, “Development of smooth torque in switched reluctance motors using self-learning techniques,” in Proc. EPE’93, vol. 6, pp. 14–19. [4] P. C. Kjaer, J. J. Gribble, and T. J. E. Miller, “High grade control of switched reluctance machines,” in Proc. IAS’96, pp. 92–100.
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[5] W. Leonhard, “30 years space vectors, 20 years field orientation, 10 years digital signal processing with controlled ac-drives, a review (part 2),” EPE J., vol. 1, no. 2, pp. 89–102, Oct. 1991. , Control of Electrical Drives, 2nd ed. New York: Springer[6] Verlag, 1996. [7] F. Blaabjerg, L. Christensen, S. Hansen, J. R. Kristoffersen, and P. O. Rasmussen, “Sensorless control of switched reluctance motor with variable-structure observer,” Electromotion, vol. 3, no. 3, pp. 141–152, 1996. [8] W. F. Ray and I. H. Al-Bahadly, “Sensorless methods for determining the rotor position of switched reluctance motors,” in Proc. EPE’93, vol. 6, pp. 7–13. [9] P. C. Kjaer, C. Cossar, and T. J. E. Miller, “Very high bandwidth digital current controller for high performance motor drives,” in Proc. 6th Int. Conf. Power Electronics and Variable Speed Drives (PEVD’96), pp. 185–190.
Frede Blaabjerg (S’86–M’88–SM’97) was born in Erslev, Denmark, on May 6, 1963. He received the M.Sc.E.E. degree from Aalborg University, Aalborg, Denmark, in 1987 and the Ph.D. degree from the Institute of Energy Technology, Aalborg University, in 1995. He was with ABB-Scandia, Randers, Denmark, from 1987 to 1988. During 1988–1992, he was a Ph.D. student at Aalborg University. He became an Assistant Professor in 1992 at Aalborg University and in 1996 an Associate Professor. In 1998, he became a Full Professor in Power Electronics and Drives at Aalborg University. His research areas are in power electronics, static power converters, ac drives, switched reluctance drives, modeling, characterization of power semiconductor devices, and simulation. He is involved in more than ten research projects with the industry. Dr. Blaabjerg is a member of the European Power Electronics and Drives Association and the IEEE Industry Applications Society Industrial Drives Committee. He is also a member of the Industry Power Converter Committee in the IEEE Industry Application Society. He is an Associate Editor of the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS in the Industry Power Converter Committee. He serves as a Member of the Board of the Danish Technical Research Council in Denmark. He received the 1995 Angelos Award for his contribution in modulation technique and control of electric drives and an Annual Teacher Prize at Aalborg University, also in 1995. In 1998, he received the Outstanding Young Power Electronics Engineer Award from the IEEE Power Electronics Society and an IEEE TRANSACTIONS ON POWER ELECTRONICS Prize Paper Award for a paper published in 1997. He also received two prize paper awards at the IEEE Industry Application Annual Meeting in 1998.
Philip C. Kjaer (S’92–M’93) was born in Montreal, P.Q., Canada, in 1969. He received the M.Sc.E.E. degree in electrical engineering from Aalborg University, Aalborg, Denmark, in 1993 and the Ph.D. degree from the University of Glasgow, Glasgow, U.K., in 1997. His studies included one year at the Universit´e Catholique de Louvain-la-Neuve, Belgium. From 1993 to 1998, he was a Research Assistant in the Department of Electronics and Electrical Engineering, University of Glasgow, working with advanced control of switched reluctance machines and drives. He is currently a Development Engineer in the Department of Power Engineering, ABB Corporate Research, V¨asteraas, Sweden. His research covers control and application of electrical machines and power electronic converters.
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Peter Omand Rasmussen was born in Aarhus, Denmark, in 1971. He received the M.Sc.E.E. degree from Aalborg University, Aalborg, Denmark, in 1995. He is currently working towards the Ph.D. degree at Aalborg University. His research areas in the Ph.D. project are modeling, design, and control of different types of switched reluctance motors operating at both low and high speeds. The main aspects in the Ph.D. project are to develop flexible programs for both design and control of switched reluctance motors where special attention to the acoustic noise aspects is taken.
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Calum Cossar was born in Hamilton, U.K., on January 22, 1962. He received the B.Sc. (Hons.) degree in electrical and electronic engineering from the University of Glasgow, Glasgow, U.K., in 1983. He spent five years as a Design Engineer with Ferranti Defence Systems Ltd. and was involved in high-speed DSP in radar. For the last ten years, he has been a Research Technologist in the SPEED Laboratory, University of Glasgow. His field of interest is digital techniques in motor control.
