A Novel Flash Fast-Locking Digital PLL: Verilog-AMS Modeling and ...

2013 10th International Conference on Information Technology: New Generations

A Novel Flash Fast-Locking Digital PLL: Verilog-AMS Modeling and Simulations By

Dr. Mahmoud Fawzy Wagdy Professor of Electrical Engineering, California State University, Long Beach (CSULB), 1250 Bellflower Blvd., Long Beach, CA 90840, USA &

Sandesh Maraliga Jayaram, MSEE, CSULB, Electrical Engineer, Qualcomm Technologies Inc., 10426, Caminito Alvarez, San Diego, CA 92126, USA

frequency matches that of the input frequency; the time taken for such iterative process is called the lock time. Lock time is a significant attribute of the PLLs because it can determine the difference of the data that may be lost. Fast-locking DPLLs [4-9] constitute a hot field of research during the last decade. The major goal of this paper is to design, via Verilog-AMS, a fast-locking FLASH DPLL that will lessen the loss of data during Frequency changeovers. The FLASH DPLL efficiently reduces the lock-time compared to that of a Conventional DPLL.

ABSTRACT - A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled using Verilog-AMS. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm leading to a thermometer code as done in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage includes an array of frequency comparators, a priority encoder, a digital-to-analog converter (DAC), and control logic including a monostable multivibrator. Verilog-AMS (Smash) is used to design and simulate both the fast-locking DPLL and its classical counterpart. Simulations revealed a lock time improvement (reduction) by a factor of 1.50-3.00 depending on the size of the input frequency hop in favor of the fast-locking DPLL.

II. THEORY OF OPERATION The Novel FLASH DPLL using DAC was conceptualized and created by Wagdy [10]. Fig.1 shows a the block diagram of the Novel FLASH DPLL [11]. The operation of the DPLL includes two stages, namely Coarse tuning and Fine tuning. It is made up of a phase/frequency detector (PFD), charge pump (CP), lowpass filter (LPF), voltage-controlled oscillator (VCO), frequency comparator (FC), encoder, D/A converter (DAC), and control logic (CL). The operation is based on rapid and parallel comparison of the incoming frequency with many equal-spaced fixed frequencies in the DPLL operating range. The DPLL constantly monitors the input frequency (Fin) in time slots of 20ns with the reference frequencies of Frequency Comparator Array. The FC array has 7 comparators which are equi-spaced in range of 250MHz to 1.75GHz. This results in a thermometer code at the output of the FC Array based on the Highs ‘1’, the Lows ‘0’, and the Timeouts ‘1’ of each comparator [10, 11]. This thermometer code is applied to the encoder which then outputs a 3-bit binary code varying from ‘000’ to ‘111’. The DAC converts the 3-bit code to an

Key Words: PLL, DPLL, frequency hop, fastlocking, coarse tuning, frequency tracking, flash algorithm, thermometer code, fine tuning, phase tracking, lock time, behavioral modeling, VerilogAMS.

I. INTRODUCTION The digital phase-locked loop (DPLL) recovers clock from digital data signals and the carrier from satellite transmission signals. It performs frequency and phase modulation and demodulation, synthesize exact frequencies for receiver tuning, and distribute clock-timing pulses in electronic applications. DPLLs can be found in computers, radios, cell phones, etc. A DPLL [1-3] works by responding to both the frequency and phase of an input signal with input frequency (Fin) by increasing or decreasing the frequency of a voltage-controlled oscillator (VCO) until the output 978-0-7695-4967-5/13 $26.00 © 2013 IEEE DOI 10.1109/ITNG.2013.36

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Fig. 1. Block Diagram of the Novel Flash Fast-Locking DPLL [11]

Signals of analog and digital types can be declared in the same module. Initial, always, and analog procedural blocks can also appear in the same module. Both analog and digital signal values can be accessed from any context (analog or digital) in the same module. Digital signal values can be set (write operations) from any context outside of an analog procedural block, and analog potentials and flows can only receive contributions (write operations) from inside an analog procedural block. The semantics of the initial and always blocks remain the same as in IEEE 1364-1995 Verilog HDL. The discipline declaration is extended to digital signals and a new construct and connect statement is added to facilitate auto-insertion of user-defined connection modules between the analog and digital domains. When hierarchical connections are of mixed type, i.e., analog signal connected to digital port or digital signal connected to analog port, user-defined connection modules are automatically inserted to perform signal value conversion. SMASH [13] is powerful modeling and simulation software that provides an environment to create digital, analog and mixed signal systems. SMASH is produced by DOLPHIN Company. VERILOG- AMS and SMASH are used to design the Conventional DPLL and the FLASH DPLL. Behavioral modeling is performed for each of the individual blocks, and does not take account the parasitic effect on the simulations.

appropriate analog voltage value which closely matches F in to act as input to the LPF, which in turn controls the VCO output, thus ending the coarse-tuning stage. This stage is subsequently followed by a fine-tuning stage, where the LPF input does not come from the DAC but rather comes from the charge pump (CP). During the fine-tuning stage, the DPLL works in a much narrower frequency range, so that the transient response is minimal. Accordingly, the step performance provided by the coarse-tuning stage reduces the lock time.

III. VERILOG-AMS Verilog-AMS [12] benefits users by allowing them to describe and simulate analog and mixed signal designs using a top-level design methodology as well as the traditional bottom-Up approach. Verilog-AMS supports analog and mixed signal designs at three levels: transistor/ gate, transistor/gate-rtl/behavioral, and mixed transistor/gate-rtl/behavioral circuit levels. The solutions of analog behaviors that obey laws of conservation fall within the generalized form of Kirchhoff’s laws. Verilog-AMS HDL can be used to describe discrete (digital) systems (per IEEE 1364-1995 Verilog HDL) and mixed-signal systems using both discrete and continuous descriptions as defined in the LRM. 218

innto the LPF duuring the UP ppulse to increaase the ouutput frequenccy and sinks cuurrent during thhe DN puulse to decreasse the output frrequency. The LPF iis shown in F Fig. 2. Generallly the vaalue of C2 iss much smalller than that of C1 (aabout 1/6 too 1/10). The Verilogg-AMS deescription is giiven below.

IV. FL LASH DPLL L DESIGN USING VERIL LOG-AMS gn of some exaample blocks Modeling and desig are given below. F Deetector (PFD) A. Phase Frequency Thee PFD block diiagram is given in [1]. The inputss for the PFD D are the in nput clock (signal) and a the VCO output. The outtput UP/DN signals deepend on th he lead/lag relationship r between th he two inpu ut signals. When the DPLL is locked both the t UP and DN D signals w. The State Flow implementation of remain low PFD is given g in [11, Fig. 9]. Veerilog-AMS description n is given below w: // pfd.vamss // Phase Frrequency detector Behaviorall `include "cconstants.vamss" `include "d disciplines.vam ms" module pffd (UP, DOWN N, clkref, clkvcco, reset); output UP, U DOWN; // outputs from the t PFD kref, clkvco; input clk /// the Ref and Fin inputs wire reset; reg UP, DOWN; a declared ass reg // up and down are integer sttate; /// the state variaable initial begin up = 0; down = 0; end // phase deetector is repressented as a statte machine. // “up” and d “down” are reeg type that tak ke values 1 // or 0 baseed on whether the t reference leeads or // lags the output o of the divider. d always @(posedge clkref c or poseedge reset) begin if (reeset) UP