A Scalable Large-Signal Multiharmonic Model of AlGaN ... - IEEE Xplore

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 65, NO. 8, AUGUST 2017

A Scalable Large-Signal Multiharmonic Model of AlGaN/GaN HEMTs and Its Application in C-Band High Power Amplifier MMIC Yuehang Xu, Senior Member, IEEE, Changsi Wang, Huan Sun, Zhang Wen, Yunqiu Wu, Ruimin Xu, Member, IEEE, Xuming Yu, Chunjiang Ren, Zhensheng Wang, Bin Zhang, Tangsheng Chen, and Tao Gao

Abstract— A scalable electrothermal large-signal AlGaN/GaN HEMTs model for both fundamental and multiharmonics is presented based on the modified Angelov model. To obtain accurate scalability of the electrothermal model, a simple empirical expression is proposed for the geometric and power-dissipationdependent nonlinear thermal resistance Rth . Only one additional parameter with linear scaling rule is needed in the drain–source current (Ids ) model for a scalable large-signal multiharmonic model. The proposed model has been validated by different AlGaN/GaN HEMTs characterized by on-wafer measurements. It shows that the presented scalable model can well predict the dc I–V , pulsed I–V , scattering (S) parameters, and large-signal performance up to third harmonic. Furthermore, to further validation, a C-band power amplifier is designed. The amplifier is realized using the second-harmonic tuned approach to enhance the efficiency. Measurement results show that the GaN high power amplifier (HPA) microwave monolithic integrated circuit (MMIC) exhibits more than 40% power-added efficiency and 60-W output power ( Pout ) with associated gain of 25 dB in 5–6 GHz measured at 28-V drain voltage and pulse signal with 100-µs pulsewidth and 10% duty cycle. The area of the chip is 3.2 mm × 5.3 mm (16.96 mm2 ). These results show that the proposed model will be useful for high-efficiency HPA MMIC design. Index Terms— AlGaN/GaN HEMT, harmonic tuned amplifier, microwave monolithic integrated circuit (MMIC), multiharmonics, scalable large-signal model (LSM).

I. I NTRODUCTION UE to the merit of high power densities at high frequency, GaN HEMTs have shown great potential in micorwave solid-state amplifiers for various wireless systems [1]–[3]. Accurate large-signal models (LSMs) can largely improve designer efficiency to develop highperformance GaN circuits. So the LSM of GaN HEMTs has

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Manuscript received April 16, 2016; revised August 14, 2016, December 25, 2016, and February 7, 2017; accepted February 9, 2017. Date of publication March 10, 2017; date of current version August 4, 2017. This work was supported in part by the National Natural Science Foundation of China under Grant 61474042 and in part by the China Post-Doctoral Science Foundation under Grant 2015T80969 and Grant 2016T90844. (Corresponding author: Yuehang Xu.) Y. Xu, C. Wang, H. Sun, Z. Wen, Y. Wu, and R. Xu are with the School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu 611731, China (e-mail: [email protected]). X. Yu, C. Ren, Z. Wang, B. Zhang, T. Chen, and T. Gao are with the Nanjing Electronic Devices Institute, Nanjing 210016, China. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TMTT.2017.2669984

Fig. 1.

Topology of the electrothermal LSM.

been widely studied in recent years, including physical-based models, electrothermal models, trapping effects, and kink effects [4]–[10]. Though good results have been demonstrated when applied to high-power or high-efficiency amplifier, most are only validated by discrete transistors with constant gate periphery, which means they are typically not scalable. However, the gate geometric (finger number N f and unit width W f ) of GaN HEMTs must be optimized for best performance in designing microwave monolithic integrated circuits (MMICs) [11]. As a result, an accurate, scalable LSM of GaN HEMTs is essential for high-performance GaN MMICs design. Compared with compact physical-based modeling methods [12]–[14], empirical models are still most frequently used due to their good accuracy and convergence. These modeling methods are easy to implement in commercial microwave simulation software as well. Due to the importance of MMICs for radar and wireless communications, scalable empirical LSMs for FETs have been widely investigated in the past. The equivalent circuit model of FETs is usually classified by intrinsic and extrinsic as shown in Fig. 1. Typically, linear scalable rules can have good accuracy for scalable intrinsic GaAs FET models up to very high frequencies. As a result, most recent works only focus on the improvement of scalable extrinsic equivalent networks for higher operation frequency GaN HEMTs [15]–[18]. Nevertheless, the conventional linear scalable model is inappropriate for the intrinsic model of GaN HEMTs, especially for the electrothermal model.

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XU et al.: SCALABLE LARGE-SIGNAL MULTIHARMONIC MODEL OF AlGaN/GaN HEMTs AND ITS APPLICATION

Different from GaAs HEMTs, the self-heating effect of AlGaN/GaN HEMTs is much more significant and complicated at high output power densities [19].The linear scalable rules for device thermal resistances are not suitable for the electrothermal model [20], [21]. In 2001, Lee et al. [22] proposed a scalable LSM with a separated electrothermal model for GaN HEMTs by directly connecting the elementary cells in series. This method basically uses a linear scaling rule based on a reference device and thus requires more fitting procedures when scaling to large size devices. An improved scalable LSM was validated in a hybrid power amplifier with linear scalable thermal resistance in the electrothermal model in 2014 [23]. This paper shows that the scalable LSM needs four empirical parameters to fit the different size devices. However, the results are still not sufficient for both fundamental and harmonics prediction; they are also not sufficient for high power amplifier (HPA) MMIC design even when using an accurate LSM with harmonic properties and linear-scaled electrothermal model [10], [24]. At the meantime, high-efficiency design methods (i.e., harmonic tuned approaches, class E, and class F) are highly attractive for microwave HPA application [25], [26]. These methods require manipulation of highorder harmonics to enhance the fundamental output power efficiency. So a LSM is required to accurately predict highorder harmonics while maintaining good accuracy of the fundamental properties [27]. As only need to control the second harmonic while switch-mode methods need to consider multiple harmonics [28], harmonic tuned methods are extremely competitive in MMIC technology due to high frequency and small area. GaN HPA MMIC by using the harmonic tuned approach has been reported in S-band [29]. Nevertheless, higher frequency like C-band GaN HPA MMICs based on harmonic tuned method is still to be explored [24], [30]. To further improvement HPA MMICs efficiency, it is necessary to have a scalable multiharmonic LSM to realize “first pass” design. In this paper, an improved scalable electrothermal LSM for AlGaN/GaN HEMTs, which is also capable of predicting multiharmonics, is presented. The available models are too complicated to be applied to a nonlinear scalable model [10], so a single-stage nonlinear electrothermal model is adopted to simplify the scalable model. Both thermal resistance (Rth ) and thermal capacitance (Cth ) in the nonlinear electrothermal model are modeled related to the gate geometrical parameters. The model is validated by on-wafer measurement results of dc I –V , pulsed I –V , scattering (S) parameters up to 40 GHz, and large-signal performance up to the third harmonics for different size GaN HEMTs. And a C-band three stages GaN HPA MMIC by using second-harmonic tuned method is designed. This paper is organized as follows. In Section II, the scalable LSM is detailed, and the parameters’ extraction procedure of electrothermal and dispersive models is explained and validated by measurement results. In Section III, the LSM is verified by dc and pulsed I –V , S-parameters, fundamental and harmonics output power (Pout ), and power-added efficiency (PAE). In Section IV, design procedure and results of a C-band HPA MMIC are presented. Section IV is the summarization of the work.

Fig. 2.

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Parameters extraction flow of the scalable LSM.

II. L ARGE -S IGNAL M ODEL D ESCRIPTION The topology of the LSM is shown in Fig. 1. The T-type inductance–capacitance (LC) networks access to both of the gate and drain terminals is used to accurately model the parasitic effects. The element Rpdg is capable of improving the S-parameters in the low-frequency band, especially for S12 [10]. The intrinsic elements include the bias-dependent Cgs and Cgd , the drain–source current Ids , and gate diodes Dgs and Dgd . The Cds is provided as a bias-independent element to simplify modeling, which has good accuracy for microwave GaN HEMTs. A nonlinear Rth –Cth subcircuit is used to characterize the thermal effects. The parameters extraction flow for the proposed scalable model is demonstrated in Fig. 2. First, a LSM is established for the reference AlGaN/GaN HEMT, which is a 4 × 100 μm device in this paper [31], [32]. The established reference device model is validated by measurement results. Then, the power dissipation (Pdiss ), Rth (Pdiss, W f , N f ), and Cth (Pdiss, W f , N f ) models are constructed using finite element method (FEM) simulation. Finally, the scaling rules for the parameters are added in the scalable LSM with the scalable parameters. A. Drain–Source Current Ids Model The Angelov Ids model (Keysight Advanced Design System, ADS v.2013) for AlGaN/GaN HEMTs is used for scalable modeling, which is given by [10], [32] Ids = Ipkth × (1 + Mipkth × tanh(ψ)) × tanh(αVds ) (1a)    Ipkth = Ipk0 × 1 + kipk0 × Tch (1b) Mipkth = (1 + Mipkl × (1 + tanh(q × (Vgseff − Vgsm ))))    × 1 + k M × Tch (1c) ψ = Pk1th × (Vgseff − Vpk1 ) + Pk2th × (Vgseff − Vpk2 )2 + Pk3th × (Vgseff − Vpk3 )3

(1d)

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TABLE I E XTRACTED Ids MODEL PARAMETERS OF 4 × 100 μm AlGaN/GaN HEMT

Fig. 3. Compassion of measured and modeled Ipk0_sc for different unit gate widths.

Vgseff = Vgs + ksurf (Vgsq − Vgspinchoff)(Vgs − Vgspinchoff) Pknth  Tch

+ ksubs(Vdsq + Vdssub0 )(Vds − Vdsq ) = (kn0 + (kn0 + kn1 × Vds ) × tanh(αn × Vds ))    × 1 + kpn × Tch n = 1, 2, and 3 = Pdiss × (Rth × (1 − exp(−t/τ th))

Cth = τ th/R

(1e) (1f) (1g) (1h)

where α denotes the saturation voltage parameter. Ipk0 represents the drain current where the maximum trans-conductance gm occurs, and Mipkth is the hyperbolic tangent multiplier as a function of Vgs . Pknth (n = 1, 2, and 3) is the fitting parameters of the ψ polynomial. Vpk1 , Vpk2 , and Vpk3 allow the asymmetric gm bell-shape characteristic. kn0 , kn1 , and αn  is the describe the drain voltage relationships for Pknth . Tch channel temperature variation, which is dependent on Pdiss . τth is the thermal time constant, respectively. Cth is obtained by calculating the ratio of time constants to the calculated thermal resistances. The trap-induced dispersive effect is characterized by the modification of gate bias Vgs . The ksurf and Vgspinchoff are related to the surface trapping effect, and ksubs and Vdssub0 are used to describe the substrate trapping. These parameters are extracted by pulsed I –V measurement as described in [4]. As for the scalable capability of the Ids model, the parameter Ipk0 is modeled by the following linear scale rule: Ipk0_sc = Ipk0 × sfw × sfn sfw = W f /W f _rf sfn = N f /N f _rf

(2a) (2b) (2c)

where W f _rf and N f _rf are the unit gate width and number of fingers of the reference device, respectively. sfw and sfn represent the scaling factors. Fig. 3 shows the Ipk0_sc variation versus gate width for different devices. The nearly linear property of the Ipk0 with the increasing gate width can be observed. Equation (2) can be used to model the current characteristic of the devices with different gate widths. Table I lists the main extracted parameters of Ids model, and the other parameters can be found in [10]. B. Electrothermal Subcircuit Model Compared with the experimental methods [33], [34], the FEM simulation is extensively used for conveniently

Fig. 4. Simulated results of Rth for different AlGaN/GaN HEMTs. (a) Rth versus the N f at W f = 100 μm. (b) Rth versus W f at N f = 4. (c) Rth at different power dissipations for 4 × 100 μm device. (d) Rth versus sfw at the same power density (5 W/mm) for different size devices, where sfw is the normalized unit gate width with respect to the reference device.

identifying Rth and Cth . In addition, the simulations are accurate and efficient for different size devices to determine their thermal parameters. The ANSYS (v.14.0) software is used for the electrothermal simulations in this paper. The channel temperature variations can be easily captured, and then the thermal resistances can be derived accurately by including the thermal boundary resistance of the nucleation layer [35], [36]. To obtain the scalability of Rth with device periphery, different N f and W f values have been investigated as shown in Fig. 4. Fig. 4(a) and (b) shows Rth versus N f for W f = 100 μm and Rth versus W f at N f = 4, respectively. It can be seen that Rth decreases with the increase of W f and N f , which is consistent with the heat transfer mechanism [33]. Fig. 4(c) shows Rth at different power dissipations for 4 × 100 μm AlGaN/GaN HEMTs. The Rth increases with the power dissipation Pdiss, which is due to the nonlinear thermal conductivities with respect to temperature [37]. Fig. 4(d) shows the simulated Rth versus sfw at different values of N f by using the same power density (5 W/mm) for different size devices, which also clearly shows that Rth is nonlinearly dependent on device geometry. Then, the scalable Rth_sc is

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Fig. 5. Measured (symbol) and simulated (line) pulsed Ids with 5-ms width and 1% duty cycle for Vgsq /Vdsq = −4/0 V to Vgs /Vds = −1/28 V. Inset is zoomed-in view.

Fig. 7. Measured (symbol) and simulated (line) dc I –V for the different size AlGaN/GaN HEMTs at Vgs = −4 to 0 V with 0.5-V steps from bottom to top, and Vds = 0 to 40 V with 1-V step. (a) 2 × 50 μm. (b) 4 × 50 μm. (c) 4 × 100 μm. (d) 6 × 100 μm.

Fig. 6. Measured (symbol) and simulated (lines). (a) gm for different AlGaN/GaN HEMTs. (b) gm2 and gm3 for 4 × 100 μm device. Vgs = −4 to 0 V, with 0.2 V steps from bottom to top, Vds = 28 V.

modeled by Rth_rf (Pdiss ) × f (sfw) sfn Rth_rf (Pdiss ) = Rth0 × (1 + k R1 × exp(k R2 × Pdiss )) f (sfw) = Rw0 × (1 − kw0 × exp(kw1 × sfw)) Rth_sc =

(3a) (3b) (3c)

where Rth_rf denotes the thermal resistance of reference devices. Rth is modeled as a function of Pdiss with fitting parameters Rth0 , k R1 , and k R2 , and Rw0 , kw0 , and kw1 . The thermal time constant τth is derived from the thermal transient simulations, and it is equal to the product of Rth and thermal capacitance Cth . Cth can be considered constant with Pdiss . The scalable Cth_sc is modeled with a linear scaling factor related to reference device Cth_rf as Cth_sc = Cth_rf × sfw × sfn.

(4)

The results of the nonlinear thermal subcircuit accounting for the self-heating effect are illustrated in the pulsed I –V , gm , and dc I –V plots shown in Figs. 5–7, respectively. The measured and simulated pulsed I –V characteristic pulsing from Vgsq /Vdsq = −4/0 V to Vgs /Vds = −1/28 V with longduration width (5 ms) and 500-ms period is shown in Fig. 5. This comparison of Ids between measurements and simulations reveals that the dynamic Ids characteristics have accurately captured. The accuracy of gm and relevant high-order derivations (gm2 and gm3 ) are significant for the large-signal behavior, especially the high-order harmonics. Fig. 6 shows the gm , gm2 ,

and gm3 versus Vgs for AlGaN/GaN HEMTs. The reduction of gm due to the self-heating effect has been accurately predicted. Moreover, the scalability of gm has also been validated for devices with different geometries. Fig. 7(a) shows the comparison of measured and simulated dc I –V of the 4 × 100 μm reference device at Vgs from −4 to 0 V and Vds from 0 to 40 V. The simulated I –V results using the proposed scalable model and the measured results for different size devices are shown in Fig. 7(b)–(d). It shows that the scaled model can give a good prediction of Ids for different size devices. To show the improvement of the proposed nonlinear Rth model, represented by Case A, the results are compared with two other cases by following steps. 1) Extract all the parameters of Ids for the 4 × 100 μm reference device, including the Rth_rf . 2) Calculate the other size devices with constant Rth , where Rth = Rth_rf . This condition is represented by Case B. 3) Calculate the other size devices with linear Rth with geometry, represented by Case C, where Rth = Rth_rf × [400/(N f × W f )]. The comparison of drain current at Vgs = 0 V is presented in Fig. 8. In Case B, the results show that the drain current is underestimated due to the overestimated Rth for larger size devices and overestimated due to the underestimated Rth for smaller size devices. It also shows that the accuracy of Case A is higher than Case C, especially at high drain bias with larger power dissipation. C. Extrinsic and Intrinsic Parasitic Parameter Extraction Multibias small-signal S-parameters in the range of 0.1–40 GHz are conducted the equivalent circuit parameters extraction. The extrinsic capacitances and inductances are extracted from the “cold FET” and the “hot FET” S-parameters

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Fig. 8. Comparison of predicted drain currents at Vgs = 0 V at Case A: Nonlinear Rth , Case B: Constant Rth , and Case C: Linear Rth .

Fig. 11. Measured (symbol) and simulated (lines) S-parameters of the AlGaN/GaN HEMTs for Vgs = −2.5 V and Vds = 28 V. (a) 2 × 50 μm. (b) 4 × 50 μm. (c) 4 × 100 μm. (d) 6 × 100 μm. Fig. 9.

Photograph of on-wafer load–pull system setup.

Fig. 10. Photographs of the different AlGaN/GaN HEMTs used to establish the scalable LSM. (a) 2×50 μm (b) 4×50 μm. (c) 4×100 μm. (d) 6×100 μm.

with the consideration of the bias-dependent parasitic resistances Rs and Rd [38], [39]. The extracted Rs and Rd are 0.1 and 1.3  for 2 × 50 μm device at Vgs = −4 V and Vds = 0 V, respectively. Due to relatively small thermal effects of Rs and Rd , the temperature-dependent access resistances are not included to simplify the model. Moreover, considering that the class AB GaN amplifier is usually biased at low drain current to get high efficiency, the bias dependence of the access resistances is negligible and is thus not considered to further simplify the model [40]. The intrinsic gate capacitances Cgs , Cgd , and Cds are extracted using “hot FET” S-parameter measurements and the bias-dependent equations are employed to model the capacitance behavior as shown in [10]. The measured forward bias I –V is used to extract the gate diodes Dgs and Dgd . The extrinsic and other intrinsic elements are modeled by linear scaling rules as described in [15] and [16].

III. VALIDATION OF THE S CALABLE M ODEL The developed LSM is embedded using symbolically defined devices in the commercial software ADS v.2013. The devices are measured using the on-wafer load–pull system on cascade deck (Summit 12 000), as shown in Fig. 9, for validation purposes. The input signal generator is Agilent E8257D, and the output power is detected by power meter Agilent N1912A and Vector Network Analyzer. The proposed scalable model is validated by 0.25-μm AlGaN/GaN HEMT with different geometries. The breakdown voltage of double field-plated AlGaN/GaN HEMT is ∼80 V [41]. The f T and power density are 28 GHz and 5 W/mm under 28 V drain voltage, respectively. The GaN HEMT is fabricated on SiC substrate. From bottom to top, the epitaxial layers are constituted by Fe-doped (4 × 1018 cm−3 ) GaN buffer (2 μm), AlN nucleation layer (20 nm), AlN spacer layer (1 nm), AlGaN barrier layer (20 nm), and GaN cap layer (2 nm). The Al-mole of AlGaN is 0.25. The sheet density of 2-DEG is 1.0 × 1013 cm−2 . Hall measurement exhibits a mobility of 1900 cm2 /V · s. The gate–drain spacing (L gd ) and gate– source spacing (L gs ) are 2 and 1 μm, respectively. The 4 × 100 μm GaN HEMT is used as the reference device. The other three devices with the sizes of 2 × 50 μm, 4 × 50 μm, and 6 × 100 μm are considered for the scaling model. The 6 × 100 μm device has already shows quite large self-heating effects, which are good enough to establish scalable modeling. Fig. 10 shows the device photographs with different gate widths, which are used to verify the scalable model. A. Small-Signal Characterization All four devices are used for the verification of the smallsignal S-parameters using the scalable LSM. Fig. 11 shows the

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Fig. 13. Waveforms of Vds and Ids when tuning the load impedances for 4 × 100 μm AlGaN/GaN HEMT at 8 GHz. TABLE II L OAD –P ULL R ESULTS OF GaN HEMTs AT f 0 = 8 GHz. I MPEDANCE U NIT: 

Fig. 12. Maximum PAE load–pull simulation results for 4 × 100 μm AlGaN/GaN HEMTs at 8 GHz. Impedances unit: . (a) Fundamental. (b) Second harmonic. (c) Third harmonic.

simulated and measured S-parameters in the frequency range of 0.1–40 GHz for Vgs = −2.5 V and Vds = 28 V. The good agreement between simulations and measurements demonstrates that the scalable model with the nonlinear thermal subcircuit and appropriate scaling rules can accurately predict the S-parameter for different device geometries. The deviation between measured and simulated results at higher frequencies can be improved by using a distributed parasitic network [15], [18]. B. Large-Signal Performance Verification To validate the proposed model, the large-signal load–pull simulation at maximum PAE for 4 × 100 μm GaN HEMTs at 8 GHz is performed as shown in Fig. 12. The devices’ bias is chosen at Vgs = −2.8 V and Vds = 28 V, which is near or at the pinch-off state of transistors with large nonlinear effects. All of the input powers (Pin ) are set at 3 dB of output power compression. The harmonics impedances are set at 0  when performing the fundamental load–pull simulation. The third harmonic is set at 0  when performing the secondharmonic load–pull simulation. The mark pointed contours are the maximum Pout or PAE, and the values decrease along the outer circles or opposite direction. Z mEn and Z mPn , where n = 1, 2, 3, are mark impedances for maximum PAE or Pout , respectively. PAE can be well improved by tuning the harmonic loads with a maximum of ∼7% with constant source impedance. The PAE improvement can be attributed

to the increase in fundamental output power and decrease in power dissipation [26]. Fig. 13 shows the waveforms of Ids and Vds when tuning the load impedance for the 4 × 100 μm device. The intersection of the output current and voltage can be decreased when tuning harmonics loads. The analysis method will be useful to determine the optimal gate geometries for best performance. Then, the load–pull measurement is performed for different devices. However, limited to the load–pull measurement system, the maximum reflection (||) can only reach up to 0.8 at f 0 = 8 GHz for our measurement system. This prevents us to do the load–pull measurements at maximum PAE in the entire Smith chart for these devices as simulated in Fig. 11, especially for small size device (i.e., 2 × 50 μm) or large seize device (i.e., 6 × 100 μm). For example, the imaginary part of the optimal fundamental impedance for 2 × 50 μm is more than 228.8 , and the real part of the optimal source impedance for 6 × 100 μm is less than 5 , results that are all larger than the maximum || that can be measured. As a result, we verified the model by comparing with the measured results at the same conditions listed in Table II, which are the best results that can be achieved by our system. The devices are biased at Vgs = −2.8 V and Vds = 28 V. From Table II, very good accuracy can be achieved even for 2 × 50 μm and 6 × 100 μm with high VSWR [42]. Finally, to verify the capability of the model predicting harmonics, a comparison between load–pull measurements and

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TABLE III L OAD R EFLECTION C OEFFICIENTS OF THE AlGaN/GaN HEMTs

the simulations under different harmonic impedances has been performed at maximum fundamental Pout. The various reflection coefficients of the load impedances (fundamental, secondharmonic, and third-harmonic impedances) for 4×100 μm and 4 × 50 μm are listed in Table III. Three cases are performed for each device. Case A uses the optimum fundamental load matched, Case B is for the optimum condition with fundamental load and the second harmonic, and Case C is the optimal load matched with fundamental, second harmonic, and third harmonic. The same source impedances,  S = 0.749 < 147.5 in polar for 4 × 100 μm and  S = 0.701 < 122.5 in polar for 4 × 50 μm, are used for the Cases, and the load impedance conditions are set the same as the former case for comparison purposes. Each load–pull measurement is confined to only the capability of our measurement system. As a result, these results are not maximum output power of these transistors but are only used for easy comparison and verification. The comparison of simulated and measured results at different load impedances is presented in Fig. 14. The model can well predict the second- and third-harmonic powers over an available Pin range from 0 to 25 dBm under different load impedances for these two devices. These results are attributed to the accurate modeling of gm and higher order derivative of gm with the proposed model as shown in Fig. 6. The comparison between measured and simulated results of the fundamental Pout, Gain, and PAE at Case C for maximum output power is shown in Fig. 15. The devices with 4×100 μm and 4 × 50 μm gate width are measured and simulated at 8 GHz as shown in Fig. 14(a) and (b), respectively. It shows that very good agreement has been achieved. Fig.14(c)–(d) is the measured fundamental PAE and fundamental Pout of these three Cases. Case C can improve 0.2-dB Pout with a corresponding improved PAE of 3%. More improvement can be obtained by tuning optimally each of the impedances of the source and load for the fundamental and high-order harmonics. IV. C-BAND A MPLIFIER MMIC D ESIGN A C-band GaN HPA MMIC with second-harmonic tuned matching is designed using the proposed model. In order to have higher PAE and maintain the same area of the MMIC chip, only the output and input of the final stage are considered. A. Topology of the GaN HPA MMIC The same schematic of the GaN HPA MMIC in [24] is used. For the first stage, two 4 × 100 μm HEMTs are chosen.

Fig. 14. Measured (symbols) and simulated (lines) harmonics of Pout at with maximum fundamental Pout at f 0 = 8 GHz, for Vgs = −2.8 V, Vds = 28 V. (a) 4 × 100 μm at Case A. (b) 4 × 100 μm at Case B. (c) 4 × 100 μm at Case C. (d) 4 × 50 μm at Case A. (e) 4 × 50 μm at Case B. (f) 4 × 50 μm at Case C.

Fig. 15. Measured and simulated fundamental Pout and PAE for different cases for Vgs = −2.8 V and Vds = 28 V. (a) and (c) 4 × 100 μm device. (b) and (d) 4 × 50 μm device.

The second stage is made up of four 2 × 4 × 110 μm HEMTs, whereas the third stage uses eight 3 × 4 × 210 μm HEMTs. Different from [24], the scalable model is used instead of the linear scalable model of small gate-width transistors. First, the load–pull simulation of the 3 × 4 × 210 μm HEMT at 6 GHz at optimal source impedance is fulfilled as shown in Fig. 16. And the second-harmonic impedances are 50  for both source and load. The simulated maximum

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Fig. 16. Fundamental frequency load–pull simulation results at 6 GHz of the 3 × 4 × 210 μm HEMT by setting the second and harmonic loads with 50  at quiescent bias Vgs = −2.5 V and Vds = 28 V. (a) Simulated Pout. (b) Simulated PAE.

Fig. 18. Simulated output matching results of signal way GaN HEMT with gate width of 3 × 4 × 210 μm. (a) Layout of matching network. (b) Simulated S21 and S22 parameters.

Fig. 17. (a) Second-harmonic load–pull and (b) source–pull simulation results at 6 GHz of the 3 × 4 × 210 μm HEMT with quiescent bias Vgs = −2.5 V and Vds = 28 V.

Pout and PAE are 42.6 dBm and 62% at Z s = 2 + j 3  and Z L = 11 + j 12 , respectively. Then, the secondharmonic (2 × 6 GHz) load–pull simulation is used to obtain the optimal second-harmonic impedance with the best efficiency as shown in Fig. 17(a). Finally, the source–pull impedance at the second harmonic (2 × 6 GHz) is simulated to further improve the efficiency as shown in Fig. 17(b). The results show that larger than 5% PAE can be obtained using the second-harmonic tuned match by these three steps.

Fig. 19. Simulated results of intermatching networks between the second stage and third stage for a single way. (a) Layout of matching network. (b) Simulated S21 parameter. (c) Simulated S11 and S21 in Smith chart.

B. Design of the GaN HPA MMIC Using the load–pull simulation of the 4 × 100 μm, 2 × 4 × 110 μm, and 3 × 4 × 210 μm devices with the proposed model, all of the optimal input–output impedances are obtained for each stage. To optimize the Rth of large periphery GaN HEMTs, a large via hole (shown in Fig. 20) between each unit element is used to reduce the thermal coupling. Considering the use of the AB class bias with small static current (i.e., Vds = 28 V, Ids = 10 mA for 3 × 4 × 210 μm), these thermal couplings are not considered in the proposed HPA design. The same scalable model and modeling method can also be used for bias with high dc power or devices without a special design for reducing thermal coupling. The only difference is the value of the coefficients in the scalable electrothermal model.

The layout of the output matching networks is presented in Fig. 18(a). The dc bias node VD3 feed symmetry for each transistor uses an air bridge to isolate the coupling from the signal line. The resistances are used to avoid the odd-mode oscillator. The simulated single way (HEMTs cell with gate width of 3 × 4 × 210 μm) results are shown in Fig. 18(b). The drain of stage 3 transistors represents port 1 and the output port represents port 2 in the S-parameter simulation. The “m3” and “m4” mark points in S22 are the second-harmonic impedance with PAE = 66% by second-harmonic load–pull simulation as shown in Fig. 17(a). The interstage matching network between the second stage and the third stage is designed with the layout shown in Fig. 19. The input second-harmonic tuned circuits for the

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Fig. 21. Comparison between simulated (lines) and measured (symbols) results at 25 °C with 100-μs pulsewidth and 10% duty circle. (a) Input power sweep results at 6 GHz. (b) Frequency sweep results at Pin = 23 dBm.

Fig. 22. Comparison between simulated (lines) and measured (symbols) results at Pin = 23 dBm with 100-μs pulsewidth and 10% duty circle at different ambient temperatures in the range of −55 °C ∼ +85 °C.

Fig. 20. Measurement setup for the GaN HPA MMIC. (a) Measurement setup for large-signal measurement. (b) Photograph of large-signal measurement setup at room temperature.

third stage are realized using stubs loaded with capacitance. To isolate the gate bias of the third stage and drain bias of the second stage, two capacitances are introduced in the matching network. These two small metal–insulator–metal capacitances are connected using bottom layer metal transmission line. The simulated results of single way (single transistor with gate width of 2 ×4 ×110 μm) are shown in Fig. 19(b) and (c). The drain of stage 2 represents port 1, and the source of stage 3 transistors represents port 2 in the S-parameter simulation. Comparing with Fig. 17(b), we can see that S22 matches at a very high-efficiency impedance point with 67% PAE. C. GaN HPA MMIC Results The total dimensions are 3.2 mm × 5.3 mm (16.96 mm2 ). The chip is loaded into a jig for measurement. The schematic of the measurement setup for large-signal measurements is shown in Fig. 20(a). Fig. 20(b) is the photograph of largesignal measurement setup at room temperature. The highand low-temperature measurements are fulfilled by putting the jig into the high- and low-temperature chambers. The commercial amplifier and signal analyzer in Fig. 20(a) are used to assistant the measurement. Fig. 21 shows the measured results of PAE, Pout, and the associated power gain. The results are measured with pulsewidth 100 μs and duty circle 10% at 25 °C. Fig. 21(b) shows that the PAE was above 40%, the output power was above 60 W, and the associated power gain was above 25 dB between 5 and 6 GHz with input power Pin = 23 dBm at 25 °C. Fig. 22 shows the simulated and

measured results at Pin = 23 dBm with pulsewidth 100 μs and duty circle 10% at different ambient temperatures in the range of −55 °C ∼ +85 °C. Very good agreement has been achieved, which further validates the proposed model. Compared with the published data [24] for HPA MMICs at the C-band, the designed HPA MMIC provides good performance with more than 40% PAE and 60 W Pout with 25-dB associate Gain, which is competitive for radar applications. V. C ONCLUSION A scalable multiharmonic LSM for AlGaN/GaN HEMT is presented. A scalable nonlinear electrothermal model is proposed, and electrothermal FEM simulations are used to extract parameters. On-wafer measurement of I –V , smallsignal, and large-signal behaviors with different AlGaN/GaN HEMTs are used to verify the proposed model. The results show that accurate predictions for fundamental, second harmonics, and third harmonics have been achieved. Furthermore, the proposed scalable model is used to design a C-band GaN power amplifier MMIC. The second harmonic of the last stage is optimized to improve the PAE of the amplifier. The measurement results show that more than 40% PAE, 60-W output power, and 25-dB associated gain are achieved over 5–6 GHz at room temperature. Excellent agreement has been shown between the simulated and measured results in the ambient temperatures range of −55 °C ∼ +85 °C. The proposed model can be applied to design high-performance GaN MMICs with full use of harmonics and to design amplifiers based on “waveform engineering.” R EFERENCES [1] U. K. Mishra, L. Shen, T. E. Kazior, and Y. F. Wu, “GaN-based RF power devices and amplifiers,” Proc. IEEE, vol. 96, no. 2, pp. 287–305, Jan. 2008.

XU et al.: SCALABLE LARGE-SIGNAL MULTIHARMONIC MODEL OF AlGaN/GaN HEMTs AND ITS APPLICATION

[2] R. S. Pengelly, S. M. Wood, J. W. Milligan, S. T. Sheppard, and W. L. Pribble, “A review of GaN on SiC high electron-mobility power transistors and MMICs,” IEEE Trans. Microw. Theory Techn., vol. 60, no. 6, pp. 1764–1783, Jun. 2012. [3] J. J. Komiak, “GaN HEMT: Dominant force high-frequency solid-state power amplifiers,” IEEE Microw. Mag., vol. 16, no. 3, pp. 97–105, Mar. 2015. [4] K. S. Yuk, G. R. Branner, and D. J. McQuate, “A wideband multiharmonic empirical large-signal model for high-power GaN HEMTs with self-heating and charge-trapping effects,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 12, pp. 3322–3332, Dec. 2009. [5] S. Vitanov et al., “Physics-based modeling of GaN HEMTs,” IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 685–693, Feb. 2012. [6] J. B. King and T. J. Brazil, “Nonlinear electrothermal GaN HEMT model applied to high-efficiency power amplifier design,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 1, pp. 444–454, Jan. 2013. [7] D. Hou, G. L. Bilbro, and R. J. Trew, “A compact physical AlGaN/GaN HFET model,” IEEE Trans. Electron Devices, vol. 60, no. 2, pp. 639–645, Feb. 2013. [8] G. Crupi et al., “An extensive experimental analysis of the kink effects in S22 and h 21 for a GaN HEMT,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 3, pp. 513–520, Mar. 2014. [9] A. Raffo, G. Bosi, V. Vadalá, and G. Vannini, “Behavioral modeling of GaN FETs: A load-line approach,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 1, pp. 73–82, Jan. 2014. [10] C. Wang et al., “An electrothermal model for empirical large- signal modeling of AlGaN/GaN HEMTs including self-heating and ambient temperature effects,” IEEE Trans. Microw. Theory Techn., vol. 62, no. 12, pp. 2878–2887, Dec. 2014. [11] S. Marsh, Practical MMIC Design. Norwood, MA, USA: Artech House, 2006. [12] S. Khandelwal, S. Ghosh, Y. S. Chauhan, B. Iniguez, and T. A. Fjeldly, “Surface-potential-based RF large signal model for gallium nitride HEMTs,” in Proc. IEEE Compound Semiconductor Integr. Circuit Symp. (CSICS), Oct. 2015, pp. 1–4. [13] P. Martin, R. Hah, and L. Lucci, “A surface-potential-based compact modelof AlGaN/GaN HEMTs power transistors,” in Proc. NSTI Nanotech Conf., May 2013, pp. 544–547. [14] U. Radhakrishna, T. Imada, T. Palacios, and D. Antoniadis, “MIT virtual source GaNFET-high voltage (MVSG-HV) model: A physics based compact model for HV-GaN HEMTs,” Phys. Status Solidi C, vol. 11, nos. 3–4, pp. 848–852, Mar. 2014. [15] A. Jarndal and G. Kompa, “An accurate small-Signal model for AlGaNGaNHEMT suitable for scalable large-signalmodel construction,” IEEE Microw. Wireless Compon. Lett., vol. 16, no. 6, pp. 333–335, Jun. 2006. [16] D. Resca et al., “Scalable nonlinear FET model based on a distributed parasitic network description,” IEEE Trans. Microw. Theory Techn., vol. 56, no. 4, pp. 755–766, Apr. 2008. [17] D. Resca, A. Raffo, A. Santarelli, G. Vannini, and F. Filicori, “Scalable equivalent circuit FET model for MMIC design identified through FWEM analyses,” IEEE Trans. Microw. Theory Techn., vol. 57, no. 2, pp. 245–253, Feb. 2009. [18] D. Schwantuschke et al., “A fully scalable compact small-signal modeling approach for 100 nm AlGaN/GaN HEMTs,” in Proc. 8th Eur. Microw. Integr. Circuits Conf., Oct. 2013, pp. 6–8. [19] J. Khurgin, Y. Ding, and D. Jena, “Hot phonon effect on electron velocity saturation in GaN: A second look,” Appl. Phys. Lett., vol. 91, no. 25, p. 252104, 2007. [20] A. M. Darwish, A. J. Bayba, and H. A. Hung, “Thermal resistance calculation of AlGaN-GaN devices,” IEEE Trans. Microw. Theory Techn., vol. 52, no. 11, pp. 2611–2620, Nov. 2004. [21] A. Darwish, A. J. Bayba, and H. A. Hung, “Channel temperature analysis of GaN HEMTs with nonlinear thermal conductivity,” IEEE Trans. Electron Devices, vol. 62, no. 3, pp. 840–846, Mar. 2015. [22] J. W. Lee, S. Lee, and K. J. Webb, “Scalable large-signal device model for high power-density AlGaN/GaN HEMTs on SiC,” in IEEE MTT-S Int Microw. Symp. Dig., May 2001, pp. 679–682. [23] Y. Xu et al., “A scalable GaN HEMT large-signal model for highefficiency RF power amplifier design,” J. Electromagn. Waves Appl., vol. 28, no. 15, pp. 1888–1895, 2014. [24] X. Yu, H. Sun, Y. Xu, and W. Hong, “A C-band 60W GaN power amplifier MMIC designed with harmonic tuned approach,” Electron. Lett., vol. 52, no. 3, pp. 172–173, Feb. 2016. [25] P. Colantonio, F. Giannini, and E. Limiti, High Efficiency RF and Microwave Solid State Power Amplifiers. Hoboken, NJ, USA: Wiley, 2009.

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[26] M. Thian, A. Barakat, and V. Fusco, “High-efficiency harmonicpeaking class-EF power amplifiers with enhanced maximum operating frequency,” IEEE Trans. Microw. Theory Techn., vol. 63, no. 2, pp. 659–671, Feb. 2015. [27] V. Vadala, A. Raffo, S. D. Falco, G. Bosi, A. Nalli, and G. Vannini, “A load–pull characterization technique accounting for harmonic tuning,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 7, pp. 2695–2704, May 2013. [28] Y. Sun and X. Zhu, “Broadband continuous class F−1 amplifier with modified harmonic-controlled network for advanced long term evolution application,” IEEE Microw. Wireless Compon. Lett., vol. 25, no. 4, pp. 250–252, Mar. 2015. [29] A. Alexander and J. Leckey, “A 120 Watt GaN power amplifier MMIC utilizing harmonic tuning circuits for S-band applications,” in Proc. IEEE Int. Microw. Symp. (IMS), Phoenix, AZ, USA, May 2015, pp. 1–3. [30] K. Mimis and G. T. Watkins, “Design method for harmonically-tuned, dynamicload-modulated power amplifier,” in Proc. German Microw. Conf., Nürburg, Germany, pp. 16–18, Mar. 2015. [31] Z. Wen, Y. Xu, C. Wang, X. Zhao, and R. Xu, “An efficient parameter extraction method for GaN HEMT small-signal equivalent circuit model,” Int. J. Numer. Model. Electron. Netw. Devices Fields, vol. 30, no. 1, p. e2127, Jan./Feb. 2017. [32] Z. Wen, Y. Xu, C. Wang, X. Zhao, and R. Xu, “A parameter extraction method for GaN HEMT empirical largesignal model including selfheating and trapping effects,” Int. J. Numer. Model. Electron. Netw. Devices Fields, vol. 30, no. 1, p. e2137, Jan./Feb. 2017. [33] G. Sozzi and R. Menozzi, “A review of the use of electro-thermal simulations for the analysis of heterostructure FETs,” Microelectron. Rel., vol. 47, no. 1, pp. 65–73, Jan. 2007. [34] C. P. Baylis, L. P. Dunleavy, and J. E. Daniel, “Direct measurement of thermal circuit parameters using pulsed IV and the normalized difference unit,” in IEEE MTT-S Int Microw. Symp. Dig., Jun. 2004, pp. 1233–1236. [35] G. J. Riedel et al., “Reducing thermal resistance of AlGaN/GaN electronic devices using novel nucleation layers,” IEEE Electron Device Lett., vol. 30, no. 2, pp. 103–106, Feb. 2009. [36] A. Manoi, J. W. Pomeroy, N. Killat, and M. Kuball, “Benchmarking of thermal boundary resistance in AlGaN/GaN HEMTs on SiC substrates: Implications on the nucleation layer microstructure,” IEEE Electron Devices Lett., vol. 31, no. 12, pp. 1395–1397, Dec. 2010. [37] H. Hjelmgren, M. Thorsell, K. Andersson, and N. Rorsman, “Extraction of an electrothermal mobility model forAlGaN/GaNheterostructures,” IEEE Trans. Microw. Theory Techn., vol. 59, no. 12, pp. 3344–3349, Nov. 2012. [38] D. W. Disanto and C. R. Bolognesi, “At-bias extraction of access parasitic resistances in AlGaN/GaN HEMTs: Impact on device linearity andchannel electron velocity,” IEEE Trans. Electron Devices, vol. 53, no. 12, pp. 2914–2919, Dec. 2006. [39] M. Thorsell, K. Andersson, H. Hjelmgren, and N. Rorsman, “Electrothermal access resistance model for GaN-based HEMTs,” IEEE Trans. Electron Devices, vol. 58, no. 2, pp. 466–472, Feb. 2011. [40] J. M. Tirado et al., “Origin of the increasing access resistance in AlGaN/GaN HEMTs,” in Proc. 66th Device Res. Conf., Santa Barbara, CA, USA, Jun. 2008, pp. 203–204. [41] Y. F. Wu, M. Moore, A. Saxler, T. Wisleder, and P. Parikh, “40-W/mm double field-plated GaN HEMTs,” in Proc. 64th Device Res. Conf., State College, PA, USA, Jun. 2006, pp. 151–152. [42] O. Jardel et al., “An electrothermal model for AlGaN/GaN power HEMTs including trapping effects to improve large-signal simulation results on high VSWR,” IEEE Trans. Microw. Theory Techn., vol. 55, no. 12, pp. 2660–2669, Dec. 2007. Yuehang Xu (M’11–SM’16) received the B.S. and M.S. degrees in electromagnetic field and microwave techniques from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2004 and 2007, respectively, and the Ph.D. degree from UESTC joint with Columbia University, New York, NY, USA, in 2010. In 2010, he joined the Department of Electronic Engineering, UESTC, and became an Associate Professor in 2012. He was a Visiting Associate Professor with Case Western Reserve University, Cleveland, OH, USA, in 2016. He has authored or co-authored more than 30 scientific papers in international journals and conference proceedings. His current research interests include modeling and characterization of radio frequency micro and nanoscale electronic devices and microwave monolithic integrated circuit design.

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Changsi Wang was born in Sichuan, China. He received the B.S. degree from the Institute of Xi’an Communication, Xi’an, China, in 2006. He is currently pursuing the Ph.D. degree in electromagnetic field and microwave techniques at the University of Electronic Science and Technology of China, Chengdu, China. From 2006 to 2008, he was a Mobile Communication Engineer with Xi’an Hui Long Network Technology Company, Ltd., Xi’an. His current research interests include HEMT devices modeling for microwave and millimeter-wave large-signal operation and microwave monolithic integrated circuit design.

Huan Sun was born in Sichuan, China, in 1989. He received the B.S. degree in electromagnetic field and microwave techniques from the University of Electronic Science and Technology of China, Chengdu, China, in 2012, where he is currently pursuing the M.S. degree in electromagnetic field and microwave techniques. From 2012 to 2013, he was a Mobile Communication Engineer with the China Electronic Technology Group Corporation, Chengdu. His current research interests include high-efficiency power amplifier and microwave monolithic integrated circuit design.

Zhang Wen was born in Hubei, China, in 1990. He received the B.S. degree in mathematics and applied mathematics from the University of Electronic Science and Technology of China, Chengdu, China, in 2012, where he is currently pursuing the Ph.D. degree in electromagnetic field and microwave techniques. His current research interests include characterization and modeling of GaN HEMT devices.

Yunqiu Wu received the B.S. and Ph.D. degrees from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 2004 and 2009, respectively. From 2009 to 2012, she was a Lecturer with UESTC, where she was involved with the research on microwave parameter measurement of thin-film materials. From 2012 to 2013, she was a PostDoctoral Researcher with the Technique University of Denmark, Copenhagen, Denmark, where she was involved in the design and parameter extraction of left-hand materials. She is currently an Associate Professor with UESTC. Her current research interests include microwave measurement and IC design.

Ruimin Xu (M’07) was born in Sichuan, China, in 1958. He received the B.S. and Ph.D. degrees in electromagnetic field and microwave techniques from the University of Electronic Science and Technology of China (UESTC), Chengdu, China, in 1982 and 2007, respectively. He is currently a Full Professor with UESTC. His current research interests include microwave and millimeter-wave technologies and applications and radar systems.

Xuming Yu was born in Zhejiang, China, in 1982. He received the M.S. degree in electromagnetic field and microwave techniques from the Nanjing University of Science and Technology, Nanjing, China, in 2006, and the Ph.D. degree in electromagnetic field and microwave techniques from Southeast University, Nanjing, in 2016. In 2006, he joined the Nanjing Electron Devices Institute, Nanjing. His current research interests include GaN HEMT devices modeling and power amplifier microwave monolithic integrated circuit design.

Chunjiang Ren was born in Zhejiang, China, in 1979. He received the B.S. degree in microelectronics and solid-state electronics from Zhejiang University, Hangzhou, China, in 2002, and the M.S. degree from the Nanjing Electron Devices Institute (NEDI) Nanjing, China, in 2005. He is currently a high-frequency electronic device developing Engineer with NEDI. His current research interests include the design, fabrication, characterization, and development of GaN-based high-frequency high-power electronic devices.

Zhensheng Wang was born in Jiangshu, China, in 1979. She received the B.S. degree in the microelectronic field from Southeast University, Nanjing, China, in 2000, and the M.S. degree in the microwave solid electronics field from the Nanjing Electronic Device Institute, Nanjing, in 2006. She was involved in power model and microwave monolithic integrated circuit design work. Since 2006, she has been an Engineer with the Nanjing Electronic Device Institute. She is currently involved with load–pull measurement systems.

Bin Zhang was born in Jiangsu, China, in 1960. He received the B.S. and M.S. degrees in electronic devices and physics from Southeast University, Nanjing, China, in 1982 and 1985, respectively. In 1985, he joined the Nanjing Electron Devices Institute, Nanjing. His current research interests include the design of microwave and millimeterwave power amplifier microwave monolithic integrated circuits.

Tangsheng Chen was born in Hubei, China, in 1964. He received the B.S. and M.S. degrees in semiconductor physics and devices from Xi’an Jiaotong University, Xi’an, China, in 1986 and 1989, respectively. In 1989, he joined the Nanjing Electron Devices Institute, Nanjing, China. His current research interests include the fabrication, characterization, and development of compound semiconductor highfrequency high-power electronic devices.

Tao Gao, photograph and biography not available at the time of publication.