Oct 17, 2017 - ... I. Yatsenko, M.Sc (speaker). Industrial Electronics Department,. Chernihiv National University of. Technology (ChNTU),. Chernihiv, Ukraine ...
A Scalable VHDL-Implementation Technique of the Binary Encoder Structure into FPGA
Roman D. Yershov, PhD St., Denys S. Yakosenko, M.Sc., Serhii I. Yatsenko, M.Sc (speaker) Industrial Electronics Department, Chernihiv National University of Technology (ChNTU), Chernihiv, Ukraine
RESEARCH STRUCTURE • Introduction to a novel technique. • Generic logic element design flow from mathematical description to algorithm of generation sequence. • A scalable binary encoder design flow from mathematical description to algorithm of generation sequence. • The logic structure of interconnections in scalable binary encoder. • Synthesis and analysis testing results at different FPGA’s platforms. • Conclusions and future research.
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TARGET OF RESEARCH • A scalable VHDL-description of the Generic Logic Element (GLE) based on Basic Logic Element (BLE). • An algorithm and relationships which allow to generate platform-independent GLE with optimal timing and performance characteristics. • A scalable VHDL-implementation of the Binary Encoder structure which consist of generic logic elements. • A technique of interconnections generation between the components inside scalable Binary Encoder. 3
RELATED PROBLEMS • Non-optimal using of FPGA resources by the typical behavior descriptions. • Choosing the basic logical function for generating scalable logic element. • Instantiation order based of generic logic elements into encoder circuit. • Comparison of FPGA resource utilization by our technique and the typical approaches. 4
INEFFECTIVE IMPLEMENTATION “CONCURRENT WHEN..ELSE”
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SYNTHESIZED “CONCURRENT WHEN..ELSE” RTL-REPRESENTATION
This circuit occupies 29 cells (8 inputs and error detection). 6
DISADVANTAGES OF THE IMPLEMENTATION “WHEN..ELSE” • Non-scalable description; • Circuit depth proportional to input count; • Fictive synthesized latches at every output; • Redundant comparators for each valid combination. 7
INEFFECTIVE IMPLEMENTATION “SEQUENTIAL CASE“
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SYNTHESIZED “SEQUENTIAL CASE” RTL-REPRESENTATION Mux0
din[7..0]
000000000000000000000000000000100000000000000010000000100010000 --
SEL[7..0] OUT DATA[255..0]
MUX
Mux1
SEL[7..0]
000000000000000000000000000000100000000000000010000000000000110 --
OUT DATA[255..0]
dout[2..0]
MUX
Mux2
Disadvantages: • Non-scalable description; • Excessive and redundant MUX data width for direct table truthfunctions storage.
SEL[7..0]
000000000000000000000000000000100000000000000000000000100000104 --
OUT DATA[255..0]
MUX
Mux3
SEL[7..0]
FFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFEFFFFFFFEFFFEFEE9 --
OUT DATA[255..0]
error
MUX
This circuit occupies 13 cells (8 inputs and error detection). 9
PYRAMIDAL CASCADING BACKGROUND Equation below describes dependence between connections of basic logic element - BLE inside tree of the generic logic element - GLE.
𝐹 𝐹 𝑥1 , … , 𝑥𝑝 , 𝐹 𝑦1 , … , 𝑦𝑝 , 𝐹 𝑧1 , … , 𝑧𝑝 = 𝐹(𝑥1 , … , 𝑥𝑝 , 𝑦1 , … , 𝑦𝑝 , 𝑧1 , … , 𝑧𝑝 )
= 10
Equation below describes the number of the pyramid levels inside GLE. L – number of Pyramid levels; M – needed number of used inputs only; P – number of BLE’s inputs (small and fixed value).
L= log 𝑝 𝑀 11
REGULAR PYRAMID INPUTS COUNT
Equation below describes the number of all inputs (B) in GLE. M – used inputs; P – number of BLE inputs; L – number of pyramid levels.
𝐵 = 𝑃 ∙ 𝑃𝐿−1 = 𝑃 ∙ 𝑃 log𝑝 𝑀 −1 = 𝑃 log𝑝 𝑀
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STUBBING OF UNUSED INPUTS
M – number of used inputs only (M=6). Neutral stable value: ‘1’ for AND; ‘0’ for OR and XOR.
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RELATIONSHIPS BETWEEN INDECES OF THE BLEs I/O INSIDE GLE (TREE PARADIGM)
Fundamental dependence between indexes of parent nodes and its sons in the tree when we passing through the tree in horizontal way. Relationships between indexes of parent node (local element output) and his sons nodes (local element input) on the level: Parent: ( i; j ) -> Sons: First( i + 1; 2 * j + 0 ), Second( i + 1; 2 * j + 1 )
𝑮𝒆𝒏𝒆𝒓𝒂𝒍𝒍𝒚:
𝑆𝑜𝑛𝐼𝑛𝑑𝑖+1 ℎ = 𝑃𝑎𝑟𝐼𝑛𝑑𝑖 ∙ 𝑝 + ℎ; where h − son index; p - sons amount.
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ALGORITHM OF GLE GENERATION SEQUENCE IN VHDL Next VHDL-code implements according to fundamental dependence an algorithm of connections between BLEs inputs and outputs inside tree of the GLE.
BLEs are mounted in the signal grid inside the nested ‘for’ loop.
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CONNECT THE GLE-PYRAMID TO I/O PORTS OF ENTITY
It VHDL-code implements connection the BLE`s based pyramid to entity of the GLE I/O-ports. 16
SCALABLE BINARY ENCODER GENERATION TECHNIQUE
𝐾 = log 2 𝑁 ,
Where K – the number of encoder output lines; N – the number of encoder input lines; ∗ – ceiling operator. 17
The next system of equations shows the relationships between the indices of inputs and outputs in the binary encoder.
Q0 0 I1 2 I 3 4 I 5 6 I 7 , 8 … 0=1 – one through one input is skipped ! 2 Q1 I 2 I 3 I 6 I 7 , 45 89 … 1 01 2 =2 – two through two inputs are skipped ! ; Q2 0 1I243 I 5 I 6 8I97 10 11 … 22=4
– four through four inputs are skipped !
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LOGIC STRUCTURE OF SCALABLE BINARY ENCODER
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INTERCONNECT VOCABULARY STRUCTURE We need to realize interconnect matrix called “Interconnect vocabulary” which represents a sequence of connections between the outputs of Single Request Detector (SRD) and inputs of Disjunction Inputs Matrix (DIM).
1 K
2 4
3 3 5
N/2+1
1
5 6
Q0
2
6
‘OR’ gate
K
N-1
3
Q1
N
‘OR’ gate
N/2+2
nil N/2+3
N-1
5 6 Qk-1 N-1
Interconnection Vocabulary Non-synthesed Part
Input Bus
‘OR’ gate Disjunctions Input Matrix Binary Encoder
OFLEs array
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ALGORITHM OF SCALABLE BINARY ENCODER GENERATION SEQUENCE IN VHDL Next VHDL-implementation realized connections between OFLEs inputs (DIM) and SRD outputs inside Interconnect vocabulary.
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STUBBING OF UNUSED INPUTS IN CASE OF INCOMPLETE ENCODER Next VHDL-code realizes stubbing of unused inputs of OFLEs:
vac_reg is used to indicate the actual used number of each OFLE’s inputs in case of incomplete encoder. 22
SYNTHESIZED STRUCTURE AT THE REGISTER TRANSFER LEVEL REPRESENTATION
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COMPARATIVE ANALYSIS OF FPGA RESOURCES UTILIZATION Resources utilization by Xilinx ICs 300
250
FPGA family:
Macrocells
200
CoolRunner-II 150
Spartan-3 Spartan-6
100
50
0 0
50
100
Number of encoder inputs
150
Spartan-6 macrocells are twice as large as those of other families
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Resources utilization by Intel Altera ICs 450 400
Macrocells
350
FPGA family:
300
MAX-3000A
250
Cyclones-III
200
MAX-II
150 100 50 0 0
50
100
Number of encoder inputs
150
MAX-3000A macrocells are twice as large as those of other families 25
СONCLUSIONS • Proposed architecture is pure scalable and allows keeping the algorithm flexibility by taking the advantages of ‘generic’ and ‘generate’ VHDL statements. • Compared to the typical behavior-style implementation, the synthesized circuit is pure combinational and has minimal logical chain depth. • All synthesized structures was implemented into FPGA and tested under timing simulation. • Description is platform-independent and can be used to synthesize any macro functions for different FPGAs families.
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FUTURE RESEARCH • To develop a scalable implementation of the highest-priority request selection circuit (daisychain), as a result to realize the structure of scalable highest-priority binary encoder. • Approbation of the proposed novel technique as a part of ASIC design flow.
• Comparative analysis of timing characteristics and power consumption. 27
THANK YOU FOR YOUR ATTENTION! HAVE A GOOD DAY!
If you used our article please add the following reference: R.D. Yershov, D.S. Yakosenko, and S.I. Yatsenko, “A Scalable VHDL-Implementation Technique of the Binary Encoder Structure into FPGA,” in III IEEE International Young Scientists Forum (YSF) on Applied Physics and Engineering, October 17-20, 2017, Lviv, Ukraine.
