2017 IEEE International Young Scientists Forum on Applied Physics and Engineering YSF-2017
A Scalable VHDL-Implementation Technique of the Binary Encoder Structure into FPGA Roman D. Yershov, PhD St., Denys S. Yakosenko, M.Sc., Serhii I. Yatsenko, M.Sc., Industrial Electronics Department, Chernihiv National University of Technology (CNUT), Chernihiv, Ukraine e-mail:
[email protected];
[email protected];
[email protected]
Abstract— The problem of scalable and optimal behaviorstyle description of the binary encoder implementation into FPGA was examined. The structural synthesis technique of the binary encoder with input requests filtration and error detection circuits, which allow improving FPGA resource utilization in comparison with typical description, was proposed. The results of research and development, which have presented by relationship equations for encoder and its structure generation algorithm, were confirmed by correct register-transfer level representation and during timing simulation. The numeric comparative assessments of FPGA recourses utilizing depending both the encoder inputs number and FPGA ICs family from different vendor was implemented. Keywords— binary encoder; VHDL; synthesis; regular structure; scalable design
I.
FPGA;
structural
INTRODUCTION
In the classical exposition of digital circuitry, combinational devices are divided according to the modification of data flows by them: devices that switch a single from a number of input signals to the output, according to a certain rule (encoder, multiplexer); and devices that switch a single input to one of many output by a certain rule (demultiplexer, decoder). By criterion of code conversion during signal passing through the scheme are divide into: devices that convert “1 from N” code to binary code or vice versa (decoder, encoder), and devices that convert some binary codes into switching of another signals (multiplexer, demultiplexer). However, during the synthesis it turns out that the decoder is the base circuit for other devices, the multiplexer and demultiplexer are being built on it. The encoder is differs from others by the logic structure and operating features. At the same time encoder implementation in most sources of educational and even specialized literature is given without taking them into account. That is why most engineers often replace the hardware encoder implementation by softwarebased. A similar situation has developed with FPGA vendors, which usually do not include the binary encoder into the standard macrofunctions library. The most general overview of novel FPGA design methodologies is given in [1]. The most useful and relevant paradigm of portable HDL-implementation, different timing
simulation techniques, in-system debugging design tools, was presented in terms of industrial control system. The design flow for reconfigurable computing in [2] helps to understand interaction between mixed descriptions using pure sequential and parallel languages together. A very important paradigm of mapping DSP algorithms into FPGA, where computational elements (which are nodes of data flow graph) are installed between nodes of signal network represented by two-dimensional array is described in [3]. Also an important auxiliary data structures and limitation rules applied during mapping process is showed. The powerful theoretical background of highest-priority encoder operation is given [4]. The different rules for priorities request filtration and selection, developed basic priority management cell and rule for its sequential cascading in VSLI basis is described. Also the lookahead scheme for reduction a propagation delay was proposed. A several practical methodologies of implementation a scalable priority encoder are presented in [5]. The key relationships in binary encoders allow its scaling also described. All results were approved with simulation for 180nm CMOS ICs. The patented encoder devices by famous IC vendors (TI, IBM, Xilinx, Toshiba) [6][10] gives us deeply understanding of the structure and operating features of the most complexity type of encoders, which realized and their operation is approved. The considered above examples lead to the idea that the task of creating a scalable encoder is divided into two: firstly, creating a logical element with a tunable input dimension and performed logic function, and, secondly, creating an expandable algorithm for placing these elements according to the interconnection network of the binary encoder circuitry. The aim of research covered in this paper is to develop by using the hardware description language (VHDL), a complete binary encoder IP-core that would meet the following requirements: scalability of the inputs number, the choice of the active request level, cross-platform implementation (source code independence from the type of FPGA and its manufacturer), optimality using resources of the crystal, and at the same time, the proximity of the synthesis results to the discrete manual circuit implementation.
October 17-20, 2017 | Lviv, Ukraine
2017 IEEE International Young Scientists Forum on Applied Physics and Engineering YSF-2017 II.
GENERIC LOGIC ELEMENT IMPLEMENTATION
A. Theoretical background and relationships Supposing that we have some Basic Logic Element (BLE) with small and fixed count of inputs denoted as P. Obviously that we can build a certain Generic Logic Element (GLE) with the larger necessary count of inputs M, which would implemented the same logic function as single BLE, by cascading BLEs into pyramid topology and using only a finite number of them. It should be noted, that cascading possibility has a number of limitations imposed on realized truth function: it must be commutative, idempotence and has non-inverting output. Functions, those meet these requirements, are – ‘OR’, ‘AND’, and ’XOR’. Analytically cascading is described by:
F ( F ( x1 , , xP ) , F ( y1 , , yP ) , F ( z1 , , z P ) ) = = F ( x1 , , xP , y1 , , yP , z1 , , z P )
.
(1)
Let's establish the patterns between parameters of BLE and GLE which consists of pyramidally cascaded BLEs. The level count of pyramid L will be equal to
L = log P M ,
(2)
where brackets around of logarithm suggest of rounding up (integer ceiling). The integer iterative calculation procedure of (2) will describe below. The amount I of BLEs with P-bit input, which are placed at an arbitrary pyramid level with number i, i ∈ [ 0; L − 1] can be calculated as:
I = Pi .
(3)
The total number of input lines B, located at the bottom level of the pyramid, will be calculated according to the (4), actually B is ceiling of M to the nearest power of P:
B = P ⋅ P L −1 = P ⋅ P
log P M −1
= P
log P M
.
(4)
Equations (2)-(4) already allow us to determine border conditions for structural generation loop ‘for...generate’, but it remains unclear how to store and get access to the I/O ports of already placed BLEs, to connect them among themselves, and moreover, in strictly established order. Upon closer examination of our BLE pyramid (see Fig.1), we can see that its structure corresponds to the tree data structure. As we know, a tree is a recursive, and therefore a homogeneous structure that is well suited for scaling. Really, (2)-(4) will be valid only for the case when the topology of mutual placement of BLEs in the pyramid will correspond to the concept of a full perfect tree: all nodes that are not at the bottom level have no unconnected inputs; all the nodes with unconnected inputs (leaves) are located only on separated level (lowest).
Fig. 1. GLE structure by cascading BLEs into pyramid.
There are existing relationship between indexes of nodes between the local parent node and immediately connected node (sons) in perfect full tree. Lets some tree node placed at level i in pyramid (tree) get the index of ParInd during horizontal traversal. Its son nodes will be placed at level i+1 and has tightly bound indexes SonInd(h):
SonInd i +1 ( h ) = ParInd i ⋅ P + h ,
(5)
where h ∈ [ 0; P − 1] − the son index value relation to parent node. This relation allow to describe the mutual placement of all nodes in tree and well suitable for tree nodes representation as two-dimensional array (matrix). The advantage of limitation (5) is the convenience of generating the required number of elements, using nesting loops (external through the levels from 0 to L-1, the internal through the elements of selected level). But there is also a significant disadvantage: we can generate a GLE with no number of inputs M, but only ceiling to B. B. Algoritm of Generation Sequence Accordance to the theoretical background described above and the goal set earlier, the next GLE generation sequence was developed as architecture of the VHDL-entity: 1) specifying the GLE tunable parameters in the ‘generic’ declaration section of the entity: the actual number of inputs (parameter ‘GLE_BOTTOM_WIDTH’) and the implemented logic function e.g. AND, OR, XOR (parameter ‘LOGIC_OPERATOR’); 2) the number of inputs of the basic logic element (BLE) (constant ‘BLE_MOD’) also takes into account, In our case we take it equal to 2, but it can be modified to became equal to the count of LUT inputs in specified FPGA;
October 17-20, 2017 | Lviv, Ukraine
2017 IEEE International Young Scientists Forum on Applied Physics and Engineering YSF-2017 3) calculating pyramid dimension constants at compilation stage: the number of levels in the pyramid which collected from BLEs (constant ‘NUM_LEVELS’, see Fig. 4); the number of inputs at the bottom (lowest level) of the pyramid (constant ‘PYRAMID_BOTTOM_SIZE’) to agree with the perfect full tree topology. Note, that all computational functions are not synthesized, and do not affect the resources of the FPGA; 4) creating the matrix of pyramid interconnection network (‘pyr_grid’ signal). The number of its columns is one more than the number of levels of the tree (since the nodes are installed between the signals from adjacent columns), and the number of rows is ‘PYRAMID_BOTTOM_SIZE’. One element of the matrix has type of 'std_logic’ (see Fig. 1); 5) servicing the border exception situation, when the input port capacity is equal to one, resulting to the generation of the pyramid has discarded, the GLE degenerates to the repeater (or inverter) between the input and output ports; 6) installation of the BLEs in the nodes of the interconnection signal network in accordance with the above described (2)-(5). In this case, the initial elements of each level are superposed with the top row of the interconnection matrix, through the horizontal traversal of the tree, and the elements are set from the root to the leaves (see Fig.2). 7) connecting the GLE’s output port to the top of the pyramid (i.e. to the root of the BLEs tree); 8) connecting the signals of the input port to the bottom level ( i.e. leaves of the BLEs tree) and stubing those inputs, which left unconnected, with a ‘NEUTRAL_VALUE’ constant, which does not affect the output (selected respectively to the truth functions) (see Fig.3). if GLE_BOTTOM_WIDTH > 1 generate for level_iter in 0 to NUM_LEVELS-1 generate for elem_iter in 0 to BLE_MODUS**level_iter-1 generate pyr_grid (level_iter)(elem_iter)
