A Single FPGA Embedded Framework for Secondary User in Cognitive Network* Xin Lu, Xin Su Member IEEE, Jie Zeng, HaiJun Wang Tsinghua National Laboratory for Information Science and Technology Tsinghua University,Beijing, China 100084 lu-x08,
[email protected],
[email protected],
[email protected]
Ahstract- The cognitive radio technology is very helpful
to handle the heavy computational missions, while support
in improving the use of spectrum resources and reacting its
ing partial reconfiguration at run-time, and secondary user
operating environment. This paper presents a novel embedded
must contain a hybrid of programmable and reconfigurable
framework for secondary user based a single FPGA in cognitive
components designed to provide performance and flexibility.
network. By analyzing the processing ability of FPGA and
Meantime secondary user needs a processor as a decision
evaluating the existed architecture, this framework based FPGA supplying more logic resources and stronger embedded CPU
center to handle control, intelligence and higher application.
can support spectrum sensing and the transmission of complex
Our proposed framework is designed for these requirements.
communication protocols. In a single FPGA, we refer that the
[1] [2].
hardware and software mapped framework can realize the function of cognition easily. Meantime the pre-exist library
II. EX ISTING FRAMEWORKS
and design tools can improve the efficiency of cognitive radio design. At last, we introduce the mechanism of this single
The existing platform related to secondary user can mainly
FPGA embedded framework and demonstrate this framework
be classified into these classes: pure software framework,
by a practical application. Results of the application show that this framework can flexibly switch between sensory mode and
hardware framework, and hybrid software and hardware
transmission mode, which can meet the demands of secondary
framework. GNU radio [3] and OSSIE [4] are software
user in the cognitive network.
frameworks. These pure software frameworks writing in C++ are simple to use, simulate, and evaluate the development of
Index Terms-Cognitive Network. FPGA. Embedded frame
communication protocol. However, processing performance
work.
of speed and large form factor limit application the areas of this framework. WARP [5] is a hardware platform. This
I. INTRODUCTION
platform consists of some real hardware components and
As more and more wireless services emerge in the com
also has enough resources to satisfy the demand of intensive
munication market, the already heavily crowded radio spec
processing demand. But it is not suit for cognitive radio
trum becomes much scarcer. At the same time, the use of
because of being void of an adaptive run-time reconfiguration
radio spectrum resource is insufficiency. Cognitive radio is
system for cognition.
a promising technology to alleviate the increasing stress on
designed for flexible processing at both radio physical and
KUAR [6] and WINC2R
[7] are
the fixed and limited radio spectrum. In the cognitive radio
MAC/network layer. These platforms consist of software and
networks, the secondary (unlicensed) users can periodically
hardware architecture aiming at providing adequate flexibility
search and identify available channels in the spectrum. Based
and adaptability to the environment and traffic changes as
on the searched results, the secondary users dynamically
desired in cognitive radio scenarios. But the mechanism of
tune its transceivers to the identified available channel to
run-time system, high-level design tool, and the library of
communicate among themselves without disturbing the com
radio component are still in the research prior period.
munications of the primary (licensed) users. So a cognitive
According to the shortage of the existing platforms ,
node should complete these functions: Multi-band operation,
such as processing performance, the mechanism run-time
fast spectrum scanning, frequency agility, the library of
system, power consumption, high-level design tool, and the
spectrum policy processing, and different MAC algorithms
library of component, we refer that a combination of software
switching.
frameworks with the performance and hardware frameworks
Our single FPGA embedded framework for secondary user
with simple design-flow is effective for secondary user in
meets these requirements above in cognitive network. A cog
cognitive network. By analyzing the processing ability of a
nitive node must provide sufficient computational resources
single FPGA and the requirements of secondary user ,Our proposed framework can base on a single FPGA.
-This paper is supported by Important National Science and Technology Specific Projects-No.2009ZX03005-004
978-1-4244-6871-3/10/$26.00 ©2010 IEEE
881
III. THE FPGA-BASED E MBE DDE D SOFTWARE AND
in the FPGA fabric and managed through a Linux device.
HARDWARE FRAME WORK
As shown in Fig.2. the software framework consists of regular modular, configuration modular, library modular,
In order to meet the requirement of the secondary user,
middleware, control and management modular at run-time,
the framework should have the ability to combine the advan
network and application modular. The software framework
tage of hardware's high processing speed, low time delay
can map to hardware framework suitably. Every software
and software's flexible control, easy-to-adequate new pro
modular can be supported by a hardware subsystem.
tocol.Meantime this framework must support partial recon figuration dynamically. Considering the portable, powerful, and flexible requirement in the development framework for secondary user, we propose a reality embedded framework
DODD
DODD
based on a single FPGA. The key feature of this frame
Regular
Configuration
work is that software and hardware have the relationship
modular(IP)
modular
of mapped to each other. This framework makes full use
DODD
of the advantage of the software and hardware. Considering the rapid development of FPGA, more logic resources can
I
soft-core microprocessor chip such as NiosII can support
I
8-8-88
cognitive requirement. The design tools supplied by the FPGA manufacture company can improve the efficiency of designers. The system designers will pay more attention to the communication system design without knowing low
library
J
Middleware
(
support complex digital signal processing, stronger embedded
Memory
00 )
( r:�:��ol ) I
I
I
(ApplicatiO�
level technology details of hardware. The virtual hardware architecture is shown in Fig.I.
Fig. 2.
The single FPGA embedded framework of software.
The hardware architecture based on a single FPGA mainly consists of the regular processing subsystem, reconfiguration processing subsystem, memory subsystem, and embedded processing subsystem. The regular processing subsystem is used for intensive computation in PRY, such as FFT, viterbi decoding. Considering these computations frequently used
Hardware
and highly performance, the design of hardware IP core
component
is a helpful way to handle stringent time constraints. The
Secondary Platform
reconfiguration processing subsystem is responsible for re
Software
component Cognitive resource
configured computation at run-time. This is a special part in our propose framework for the demand of CR in order to change the system flexible. This subsystem is implemented
Fig. 3.
Regular
Reconfiguration
On-chip
processing(IP)
processing
memory
The structure of the pre-exist library in our framework.
In order to improve the efficiency of system design and shorten the time of development, it is important for the pre existed library and high-level tools of system component under our proposed framework. By using the library and
(
(( Fig. 1.
On-chip
Nios
)
BUS
Interface
Extras
design tools, system designer has not had to worrying about
)
)
low-level software and hardware details and pays more
J
attention to improving the performance of the cognitive node while taking advantage of computational power of the FPGA and dynamic reconfiguration for real-time system. Fig.3. shows the structure of pre-exist library. Software and hardware components, configuration and chain component,
The single FPGA embedded framework of hardware.
and cognitive resources etc. are built up this library. To adapt
882
specific spectrum environments, the cognitive users need to make adj ustments on component and chain parameters. This pre-exist library can be saved on on-chip memory based on
1 1 1 1 1 1 1 1 1 1 1-
a single FPGA. Besides software description language C++ and hardware description language, we can use high-level design tool such as DSPBuilder, EDS and est. to complete the development of components and high level of signal processing chains.
Radio
Frontend
________
1
Set frequency
� Hardware component � Software component Fig. 5.
library
The practical application of framework based on single FPGA.
The sense modular consists of estimator component and detection component. These aim at detecting the center frequency of any transmissions by receiving and analyzing the radio front-end.The advice engine is responsible for the management of the pre-exist library. Due to the library of cognitive radio including many components, it is efficient for the advice engine using the sensing signal to help the decision
Processing chain
engine control and excuse the radio processing chain. The decision engine is the core part in this mechanism. It aims
Fig. 4.
at intelligent processing in cognitive radio. The decision
The realizing mechanism of the secondary user in this framework.
engine is used for controlling and excusing the cognitive and processing chains while not considering implementation details of the components. Meantime this part controls the
IV. T HE MECHANISM AND APPLICATION OF T HIS
reconfigured components partly for the run-time system.
FRAME WORK
The co-design engine is responsible for hardware and software co-design. By the co-design engine, hardware and
In this section, we will introduce the mechanism and application of this framework for secondary user in cognitive
software components can be combined in a singer chain.
network. A transmitter, implemented with the tradition design
To improve the flexible of design, interface design is key
at the licensed frequency. The secondary user enters sensing
part in this engine. The hardware and software components
mode using energy detection based spectrum to find the va
should be wrapped for the decision engine disposing into a
cancy frequency to set up a connection. Once the connection
custom interface. All the hardware interfaces based on a FIFO
sets up, the secondary user reconfigures into the reception
which has already been designed can connect consecutive
mode and begins to demodulate the signal. If this mission
components to chains. Especially, to satisfy the requirement
fails, the secondary user changes back into sensing mode,
of decision engine, some hardware components should be wrapped in software components with identical interfaces.
and searches for the connection built up.
The chain module connects all the components which are
Under this background of communication, the data and control flows of this application are shown in FigA. The
selected from the pre-exist library and excuses reconfigured
sensory modular with environment interaction sends out the
components at real-time for cognitive demands.
trigger. The trigger transfers to the advice engine. After
We realize this mechanism by a practical application
searching the pre-exist library, the advice engine will give the
simply. Considering LTE femtocells might be deployed in
signal to decision engine. The decision engine controls the
GSM spectrum in order to increase frequency utilization,
whole processing chain and realizes the run-time system. The
an LTE femtocell need to detect the signal activity if this
co-design plane is used for hardware and software component
frequency is already occupied. Spectrum sensing can be
wrapper and interface of the chain. After wrapper of co
used to solve this problem. Our framework is based on this
design plane, the chain modular builds up the processing
practical background. So a real platform using this framework
chain and excuses partly reconfiguration function. The mech
supports switching between sensing and transmission mode.
anism of this framework consists of the cognitive chains in
It is effective to use the same hardware resources for those
the bottom and the processing chains in the below.
operations without wasting hardware resources and power,
883
thus using a single FPGA.
signal. Once it has found the space channel, it switches into transmission node and start transmitting the streaming video. The receiver tries to receive the transmission, once a
Primary user
transmission has been found, the receiver will demodulate
---l:I I J
.. \ ......
· , , · ·
- --�
Secondary user
the signal. Fig.5. show this application. On our platform
:\
-' -- -� . -=- --....---'
.
,it is used a Altera EP2C70 to complete mainly processing
.
. . .
component and chain.Nios processor only uses about
.....
1810
LEs and IDE can be used for design. A 2-1-7 viterbi decoder uses about
1425 LEs. A 256-point FFT IPcore uses about
3658 LEs.A time-averaged power spectral density is used for Secondary user
.................!r.�!'���..........................
. ... .t
signal detection. The basic outline of detector contains two
f
units: the FFT and an averaging memory. The realization of the switch between sensory and transmission mode illustrates in Fig.7. V. CONCLUSION AND FUTURE WORK
"
�........... Reception .... . . . ..... .. .... .
. . . . . . ...
. " .................. .
f
In this paper, we introduce embedded framework for secondary user in cognitive network based on single FPGA
Fig. 6.
from three aspects: the mapped architecture of hardware and
The demonstration of this practical application.
software, the pre-exist library and tools, and the mechanism of framework. We realize this mechanism by a practical demonstration . With the improvement of processing abil ity, this proposed framework can meet the requirement of
Switch Between Sensory And Transmission Mode
intelligent wireless communication. Our future works aim at speeding up the development of this framework based already existed work. This includes that improving the ability of decision engine and advice engine, developing components of new communication protocol and function, and the high level of design tool for hardware reconfiguration. REFERENCES [I] Mitola J III, Cognitive radio: an intergrated agent architecture for software radio. PhD thesis, Royal Insititute of Technology [2] M. J. Marcus, "Unlicensed Cognitive Sharing of TV Spectrum: The controversy at the Federal Communications Commission," IEEE Com
Transmission Mode
munications Magazine, vol. 43,pp.24-25, May 2005 Fig. 7.
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The switch between sensory and transmission mode.
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Signals, Systems, and Computers,
[4] GNU
Radio,
"Thd
in Proc. Asilomar Con!
Nov.7-1O, 2004, vol. 1, pp.772-776.
GNU
Software
Radio
Project."
http://www.gnu.org!software!gunuradio! [5] M. Robert, S. Sayed , C. Aguayo, et al. "OSSIE: Open source SCA for
The demonstration as shown in Fig.6 consists of three radio
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nodes; the primary node, the secondary transmission and
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of a femtocell. The transmitter node begins in sensory mode to find the space channel without interfere with LTE-like
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