Simple Tuned Fuzzy Controller Embedded into an FPGA - IEEE Xplore

Simple Tuned Fuzzy Controller Embedded into an FPGA ∗ Centro

Oscar Montiel∗ , Yazmin Maldonado† , Roberto Sep´ulveda‡ , and Oscar Castillo

de Investigaci´on y Desarrollo de Tecnolog´ıa Digital del Instituto Polit´ecnico Nacional (CITEDI-IPN) Av. del Parque No. 1310, Tijuana, B.C., M´exico, Email: [email protected] † MS. student of CITEDI -IPN, Email: [email protected] ‡ CITEDI-IPN, Email: [email protected] § Tijuana Institute of Technology, Dept. of Computer Science Calzada Tecnol´ogico S/N, Tijuana, B.C., M´exico, Email: [email protected]

Abstract—It is presented a flexible architecture that allows to implement an embedded nonlinear fuzzy controller into an FPGA which can be easily tuned through the use of the Simple Tuning Algorithm (STA) without a controller reference model. The model was developed using VHDL programming, and it was tested in soft real time using Xilinx System Generator and Simulink before the final implementation into the FPGA. Experimental results show how the fuzzy controller works for different tuning values.

I. I NTRODUCTION At present time, there are several digital techniques to implement a digital controller. Conventional PID controllers still being a key component in industrial control because they are simple and provide useful solutions to many important industrial processes [1]. Although the extensive use of conventional PID controllers and the implementation of new techniques to improve them, they have significant limitations, because they work basically for linear processes. Some of the limitations are: •

•

•

They do not work effectively controlling complex processes that are nonlinear, time-variant, with major disturbances, uncertainties, and large time delays. They need to be tuned properly when the plant dynamics change. This is a frustrating and time-consuming experience if the nonlinearities of the plant becomes more accentuated. There are several algorithms to tune or autotune PID controllers, but in some situations, when the system becomes too complex, where the conventional PID controller will not work, no matter how it is tuned. A conventional PID cannot be used as the core of an smart control system.

Nowadays, the traditional structure of a PID controller has evolved, and the Fuzzy implementation of a PID structure (FPID) has demonstrated to be a successful idea for several reasons, some of them are: •

•

§

FPID uses every day words to establish the Fuzzy Inference System (FIS). The linguistic variables error, change of error, and integral of error can be used to handle the same signals than the conventional PID controller uses. They can work as a linear or a non linear PID controller.

978-1-4244-2352-1/08/$25.00 ©2008 IEEE

They can be smart, working in combination with other soft computing techniques. • The FPID has more parameters to adjust than conventional PID, but there are several effective methods to tune them. Fuzzy controllers are intrinsically nonlinear since they have three sources of nonlinearity; they are: The rule base, the inference engine and the defuzzification stage. Nevertheless it is possible to construct linear input-output mapping by choosing the appropriated fuzzy connectives, number of rules, etc., [2]. Thus, it is not easy to select the suitable setting for a system and then tune it. In literature, there are several ideas to tune a fuzzy controller [3] [4]; some of them are hand-tuning based on some heuristics [5], others techniques use a tuned PID controller [2], and there are methods to automatically tune the FIS [6]. The Simple Tuning Algorithm (STA) is a very simple manual method that uses only one parameter to adjust the FIS performance [7] [8]. Digital controllers can be implemented in different hardware platforms, including personal/industrial computers, industrial boards based on discrete digital logic, Digital Signal Processor (DSP) or microcontroller systems, using dedicated hardware for specific applications like Application-Specific Integrated Circuit (ASIC) or in an FPGA. In this work, we are interested in an FPID controller embedded into a Field Programmable Gate Arrays (FPGA), that can be easily tuned using the STA. Other works related are [9] [10] [11]. The organization of this paper is as follows: Section II describes the system structure, emphasizing on the fuzzy controller and the FIS structure for a latter FPGA implementation using any Hardware Description Language (HDL) as is the VHDL. Section III explains the STA tuning method and gives and overview about how to implement it using VHDL. In Section IV the software requirements to repeat the experiments showed in this paper are given; moreover, two models to achieve the experiments are explained, one is focused to obtain the control surface for different tuning values, the other one is to show how to test the fuzzy controller on-line, using soft real time in the sense of fast computing. Finally, in Section V the conclusions are given. •

II. S YSTEM DESCRIPTION To implement the Simple Tuned Fuzzy Controller (STFC), several VHDL modules were developed. Fig. 1 shows the main blocks of the system where it can be distinguish two kind of components. They are the hardware components (HWC) identified by numbers 1 to 3, and the software components (SWC) labeled with letters a to i. The Fuzzy Inference System (FIS) is identified as SWCa. The block SWCb, SWCc, and SWCd are gains for the inputs error, change of error and the fuzzy output cu, respectively. SWCe is a positive feedback loop to perform the integral action, so the controller is called Fuzzy Incremental (FInc) [2]. SWCf represents the STA method that allows to tune the FInc by modifying the input membership functions using only one variable, in this paper it is named k. The FInc output U (n) is sent to the SWCg that

of the linear PID controller given by (1).   n  e(n) − e(n − 1)  1 e(j)Ts + Td u(n) = Kp e(n) + Ti j=1 Ts (1) Index n is the time instant, Kp is the proportional gain, Ti is the integral time, Td is derivative time, and Ts is the sampling time. The output u(n) of an incremental controller is given by (2), (2) u(n) = u(n − 1) + ∆u(n)Ts where an incremental change (3) is added to the current control sequence.   e(n) − e(n − 1) 1 + e(n) (3) ∆u(n) = Kp Ts Ti The FInc output [2], is given by (5), U (n) =

m 

(cu(j) ∗ GCU ∗ Ts )

(4)

j=1

U (n) =

m 

(f (GE ∗ e(j), GCE ∗

j=1

∆e(j) ) ∗ GCU ∗ Ts ) (5) ∆t

A. VHDL FIS description The general structure of the improved FIS architecture for an FPGA implementation is shown in Fig. 2. The two main

Fig. 1. Main HW and SW components involved in the speed motor control application using a FInc controller embedded into an FPGA.

using a conversion factor gives an estimate of the duty cycle to generate the appropriated Pulse Width Modulation (PWM) signal using the SWCh block which is sent to an H-bridge (pin 5), based on the power handling integrated circuit LMD 18200 from National Semiconductor (HWC1) [12], which outputs (pins 2 and 10) are conected to the DC Servo Gearedmotor GM9236S025 with 500 pulse per revolution (ppr) optical encoder with quadrature output [13]. The function of the block SWCi is to count pulses from the optical encoder and convert these counts to speed values. The control strategy of a digital FPID controller is formulated using fuzzy rules instead of a conventional digital PID controller given by (1). Both controllers use the same set of input signals based on the error signal obtained by e = ref −y, where e is the error, ref is the control target, and y is the feedback signal. FInc (linear and nonlinear) is based on a digital emulation

Fig. 2.

Fuzzification and inference engine stages.

methods to design the Fuzzification stage are: Storage memory, and Arithmetic calculation. The first one basically consists in storing into a memory the linguistic variable names (tags), and their corresponding degree of membership. The arithmetic method performs progressive calculation of the degree of membership of the antecedents, and it uses two memory locations to save the straight lines slopes and interception points. Our proposal to improve this stage is based on the arithmetic calculation method with significant differences to those we found reported using a similar idea. Fig. 3 shows the arithmetic calculation method, it consists in performing a progressive calculation of the degree of membership of the antecedents, and it is restricted to use only normalized triangular membership functions (MFs). The method uses two memory locations for each straight line, where their slopes

Fig. 3.

Fuzzification using the arithmetic calculation method.

values and interception points are saved. An arithmetic circuit for the input of Fig. 3(a) solves the corresponding straightline equation as it can be seen in Fig. 3(b). Fig. 4 shows the proposed algorithm to implement the fuzzification stage that can be divided in the next three steps: 1) Calculate the value of the slope. 2) Calculate the degree of membership. 3) Assign the degree of membership to the outputs as well as the respective tag of the linguistic variable.

Fig. 5. Fuzzy inputs and outputs. Each fuzzy input has five MFs named Negative Big (NB), Negative (N), Zero (Z), Positive (P), Positive Big (PB). The output has five singletons called Big Decrease (BD), Decrease (D), Hold (H), Increase (I), Big Increase (BI).

each input produces two fuzzified values; i.e., in input 1 (in1 ) the dashed line indicates a crisp value that is being fuzzified, so it will produce the labels e1 and e2 with their corresponding degree of membership ge1 and ge2 . The label value for e1 is “000”, and “001” for e2 . Input in2 works in a similar way. The values e1 , e2 , ge1 , and ge2 from the fuzzification stage are the inputs of the inference engine. They are connected to the MUX block which function is to address each combination of ei and dei to join the label values in order to select a rule to determine which fuzzy output set is involved. For example, if the counter value pq in Fig. 2 is “00”, and considering the dashed line of in1 in Fig. 5, we will have the rule combination “000000”, for pq=“01” the rule combination is “000001”, for pq=“10” the combination is “001000”, and for pq=“11” is “001001”. A rule that uses this codification is written as follows: If e1 is “000” and de1 is “000” then BI

Fig. 4.

Flow diagram to implement the fuzzification stage using VHDL.

This realization has two main advantages that help to reduce the hardware cost by mean of reducing its complexity. Hence, the system considers processing only the active rules, and limiting to two the degree of overlapping between (MFs). To illustrate this development the speed control of a DC motor was chosen. Fig. 5 shows the linguistic variables for the inputs and for the output, they are: error, change of error, and output. Each input has five MFs, Negative Big (NB), Negative (N), Zero (Z), Positive (P), and Positive Big (PB); and each label has associated a binary value, for example NB is associated with the value “000”, etc. The output has five singletons values called Big Decrease (BD), Decrease (D), Hold (H), Increase (I), and Big Increase (BI); hence, BD is associated with the binary value “000”, etc. Fig. 5 shows that

(6)

In Fig. 6 is illustrated a piece of code that handles the fuzzy rules. Considering the above rule, the antecedent (ante) is form by the concatenation of the values e1 and de1 , so we have the “ante” value of “000000”. For this rule, we also calculate the “min” of both fuzzified values since we are using the “max-min” method. The label and the firing strength are saved into a memory position, tagged as “00” in Fig. 2. The whole process is repeated for all the active rules; the maximal is four since the method that we are using. Once the rules have been evaluated and saved their results in memory, the next step is to calculate the “max” value of all memory positions tagged with the same label. Finally, at the outputs we can have the four possible consequent tags, o1 − o4 , and their firing strength, as can be seen in Fig. 2. For example, the output o1 can be given by the content of C1 and the resulting firing strength after applying the “max” operation to the corresponding set of rules. The Height method was used to achieve the VHDL implementation of the defuzzification stage. A fuzzified output with this method is calculated using (7); here, the inputs Cm and om are the peak value and height value respectively, for

Fig. 6.

VHDL Rule base codification.

the linguistic value LUm . The result of that division is f (y). n C ·o n m m f (y) = m=1 (7) m=1 om III. VHDL IMPLEMENTATION OF THE STA A. The Simple Tuning Algorithm (STA) The STA is a method to tune fuzzy controllers; it is based on the properties of the control surface, allowing the modification of the controller’s behavior by means of manipulating the ranges of the MFs of the input variables, remaining without any modification the output MFs [8] [9]. The STA uses a single variable, k, to make the modification. Fig. 7 shows the recommended rule base table for this application. The method basically consists of four steps: 1) Tuning Factor Selection. A number k ∈ [0, 1] is used to define the tuning adjustment level. k = 0 is the biggest settling time and k = 1 the smallest. 2) Normalization of the ranges of the Fuzzy Controller’s variables. The range of each input fuzzy variable is modified in order to have the lower and upper limits equal to -1 and +1, respectively. 3) Tuning Factor Processing. Once the range is normalized, the new vector of operation points will be given by: (8) V opf inal = (V opinitial )r(k) Where V opinitial is a vector with normalized values of the membership in the x-axis and r(k)is the polynomial: 30k 3 + 37k 2 + 52k + 1 (9) 40 4) Renormalization of the ranges of the fuzzy variables. Convert the normalized range to the previous range of the system. This can be computed multiplying the vector by a constant factor. r(k) =

Fig. 7.

Rule Base Table.

B. Hardware description of the STA The easier way to implement the STA method is evaluating for different k values with the aim of generating a look-up table for each MF. The original values (the unmodified values) correspond to k=0.5, hence expansion or compression of the MFs is possible. The universe of discourse of this application is the real number domain, because this implementation works with positive integer numbers, it was necessary to adapt the original scale [-40,40] to a positive scale [0,80]. Finally, for eight bit representation we used the scale [0,255]. Fig. 8 shows the ranges of the input error, when k=0.5. Note that the support of NB is [-40,-15], NEG is in [-30,0], Z is in [-15,15], etc. For the same inputs, changing scales, NB is in [0,80], NEG in [32,128], Z in [80,176], etc. Fig. 9 shows a piece Membership Functions NB

N

Z

P

PB

1

Degree of membership

function regla base(a : std logic vector) return std logic vector is variable cn: std logic vector(m downto 1); variable conse: std logic vector(m*2 downto 1); begin conse:=a; case conse is when “001001” =>cn := BI; when “001010” =>cn := BI; when “001011” =>cn := BI; when “001100” =>cn := BI; when “001101” =>cn := BI; when “010001” =>cn := BI; when “010010” =>cn := I; when “010011” =>cn := I; when “010100” =>cn := H; when “010101” =>cn := I; when “011001” =>cn := I; when “011010” =>cn := H; when “011011” =>cn := H; when “011100” =>cn := H; when “011101” =>cn := D; when “100001” =>cn := D; when “100010” =>cn := H; when “100011” =>cn := D; when “100100” =>cn := D; when “100101” =>cn := BD; when “101001” =>cn := BD; when “101010” =>cn := BD; when “101011” =>cn := BD; when “101100” =>cn := BD; when “101101” =>cn := BD; when others =>cn := “000”; end case; return cn; end function regla base;

0.5

0 −0.1 −40

−30

−20

−10

0

10

20

30

40

error

Fig. 8.

MFs of the input error for k=0.5.

of code in VHDL that defines the original values (k=0.5), and Fig. 10 shows how to redefine the original values using VHDL codification. A typical use of this function is as follows: nb:=STA nb(ka), where in ka is given the k value of the STA.

variable variable variable variable variable

nb:trapezoidal:=(“00000000”,“00000000”,“00100000”,“01010000”); – (0,0, 32, 80); neg: triangular :=(“00100000”,“01010000”,“10000000”); – (32,80, 128); z: triangular :=(“01010000”,“10000000”,“10110000”); – (80,128, 176); p: triangular :=(“10000000”,“10110000”,“11100000”); – (128, 176, 224); pb:trapezoidal:= (“10110000”,“11100000”,“11111111”,“11111111”); –(176, 224, 255,255);

Fig. 9. Original MFs definition. They correspond to the STA value of k=0.5.

IV. E XPERIMENTAL SET UP AND RESULTS In this development we used three software tools. They are:

k=0.5 0.6 –(0, –(0, –(0, –(0, –(0, –(0, –(0, –(0, –(0, –(0, –(0,

0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,

1,3); 6,19); 12,35); 18,51); 25,66); 32,80); 40,92); 48,102); 57,111); 66,117); 74,121);

0.4

Duty Cycle

function STA nb(a: std logic vector) return trapezoidal is variable newp: trapezoidal; variable new MF: std logic vector (4 downto1):=(others=>’0’); begin new MF:=a; case new MF is when “0000”=>newp :=(“00000000”,“00000000”,“00000001”,“00000011”); when “0001”=>newp :=(“00000000”,“00000000”,“00000110”,“00010011”); when “0010”=>newp :=(“00000000”,“00000000”,“00001100”,“00100011”); when “0011”=>newp :=(“00000000”,“00000000”,“00010010”,“00110011”); when “0100”=>newp :=(“00000000”,“00000000”,“00011001”,“01000010”); when “0101”=>newp :=(“00000000”,“00000000”,“00100000”,“01010000”); when “0110”=>newp :=(“00000000”,“00000000”,“00101000”,“01011100”); when “0111”=>newp :=(“00000000”,“00000000”,“00110000”,“01100110”); when “1000”=>newp :=(“00000000”,“00000000”,“00111001”,“01101111”); when “1001”=>newp :=(“00000000”,“00000000”,“01000010”,“01110101”); when “1010”=>newp :=(“00000000”,“00000000”,“01001010”,“01111001”); when others = >newp :=(“——–”,“——–”,“——–”,“——–”); end case; return newp; end function STA nb;

0.2 0 −0.2 −0.4 −0.6 −10

Fig. 10. Code to redefine the MF Negative Big (NB) of the error input. Each case statement option corresponds to a predetermined STA k value in the range of [0,1] with an increment of 0.1; hence, for convenience, the 6th option is the same as the original option; i.e. k=0.5.

−5 0 5 10

40

20

Fig. 11. This Simulink model was used to plot the control surface, the VHDL code of the FInc is in the STA subsytem block.

Fig. 12.

−20

−40

error

change of error

Control surface using the original MFs; i.e., for k=0.5.

k=0.7 0.6

0.4

0.2

Duty Cycle

1) Simulink from Mathwork that allows to test and correct designs at a high level. 2) Xilinx Integrated Software Environment (Xilinx ISE) is a Hardware Description Language (HDL) design software suite, that allows taking designs through several steps in the ISE design flow, finishing with final verified modules that can be implemented in a hardware target, such a Field Programmable Gate Array (FPGA). 3) Xilinx System Generator (XSG) is a DSP design tool that enables the use of the Simulink for FPGA design through a “Black-box” to import VHDL code for simulation. It is very important to have the adequate versions of each software tool. We used the next setting: 1) Matlab/Simulink version 7.1 (R14). 2) Xilinx ISE Project Navigator: Release version 8.2.03i, application version 1.34. 3) Xilinx System Generator version 8.2. Two experimental Simulink models to test the FInc and the STA working together in the speed motor control application were created. The first model is shown in Fig. 11, its purpose is to provide a method to analyze the FInc control surface for different k values. The main block has three inputs, k, error, and change of error. At the input the selected k values, as well as the test vectors for the inputs error and change of error, are given with the idea to obtain the Duty Cycle output vector, and then plotting the control surface using Matlab instructions. Fig. 12 shows the control surface using the original MFs (k=0.5), Fig. 13 shows how the surface change with k equals to 0.7, and Fig. 14 shows the surface for k=0.9. The second model

0

0

−0.2

−0.4

−0.6 −10 −5 0 5 10

change of error

Fig. 13.

40

20

0

−20

−40

error

Control surface for k=0.7.

shown in Fig. 15 was developed to test the FInc in a soft real time application. The whole controller model is in the “Blackbox” (from XSG) labeled as STA entity. This second model is using the same FInc of the first model shown in Fig. 11. The second model was adapted to collect information from the DC motor for several k values in soft real time. In essence the Hardware/Software configuration of Fig. 1 was achieved. The blocks SWCa to SWCg are in the computer as Simulink blocks, the HWC1 to HWC3 are external components. Fig. 16 shows the system response for several k values; in this figure, the faster response without overshoot is obtained using a k value of 0.9. Now, the code is ready to make the final implementation into an FPGA and carry out the functionality tests. We choose the Spartan 3 as the target FPGA, and we had to make only minor modifications to obtain results like the ones obtained with the Simulink models.

V. C ONCLUSIONS k=0.9

0.6

0.4

Duty Cycle

0.2

0

−0.2

−0.4

−0.6 −10 −5

−40 −20

0 0

5

20 10

40

error

Change of error

Fig. 14.

Control surface for k=0.9.

A practical VHDL FIS model that allows to implement a flexible nonlinear FInc controller embedded into an FPGA was obtained. The STA method to tune the fuzzy controller can be implemented in a very easy way, this method allows to tune a nonlinear fuzzy controller without the necessity of employing other reference model, for example a classical digital PID. Results obtained with the experimental set up shown in Fig. 15, were very similar to those obtained with a digital oscilloscope with memory capabilities, so we conclude that although the Simulink model is a soft real time model, it worked fine in order to achieve the test. It is worthwhile to mention that owing to latency times of the operating system (Windows XP) and the Simulink by itself, we had to repeat the experiment to obtain the results that corresponds to those obtained with the memory oscilloscope. A hard real time application was not possible since the Simulink imports throught the Xilinx System Generator the VHDL modules like m-functions instead of the s-functions, as it is required. R EFERENCES

Fig. 15. Simulink model used to achieve the soft real time application of controlling the speed of the DC motor.

System response for different k values 40

35

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rpm

25 k=1 k=0.9 k=0.8 k=0.7 k=0.6 k=0.5 k=0.4 k=0.3 k=0.2 k=0.1

20

15

10

5

0

0

1000

2000

3000

4000

5000

ms

Fig. 16.

System response for several k values.

6000

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