A Spread Spectrum Clock Generator Using a ... - IEEE Xplore

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 57, NO. 6, DECEMBER 2015

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A Spread Spectrum Clock Generator Using a Programmable Linear Frequency Modulator for Multipurpose Electronic Devices Hyuk Ryu, Student Member, IEEE, Sangyong Park, Student Member, IEEE, Eun-Taek Sung, Student Member, IEEE, Seung-Gi Lee, and Donghyun Baek, Senior Member, IEEE

Abstract—This paper presents a fractional-N phase-locked loop based spread spectrum clock generator (SSCG) using a programmable linear frequency modulator. The SSCG provides a programmable frequency deviation and modulation frequency regardless of its operating frequency. The ranges of frequency-deviation ratio and modulation frequency are 0–80% and 0–100 kHz with 610 Hz step resolution. The proposed SSCG successfully support five serial-link standards by using a single SSCG, and can be applied to various switching circuits such as class-D power amplifiers or switching power converters. The EMI reduction was measured to be 10.24–13.94 dB under 100-kHz resolution bandwidth. The proposed SSCG was fabricated using a 0.13-μm CMOS process with an active area of 0.11 mm2 , while consuming an overall power of 6.28 mW at 1 GHz. Index Terms—EMI reduction, frequency modulation, phase locked loop (PLL), spread spectrum clock generator (SSCG).

Fig. 1.

PSD of (a) conventional clock generator and (b) SSCG.

I. INTRODUCTION LECTROMAGNETIC interference (EMI) is becoming a critical issue in consumer electronic devices that use seriallink communications, class-D switching power amplifiers, or switching power converters. In electronic devices, EMI comes from their high peak spectral power that is concentrated on a narrow frequency bandwidth at fundamental and harmonic frequencies. To reduce EMI level, a spread spectrum clock (SSC) generation method has been considered as an efficient solution [1]. Therefore, the SSC is essential in high speed data-link applications, such as DisplayPort, PCI Express, and Serial ATA [2]–[4]. In addition, class-D power amplifiers and switching power converters adopt the SSCs to reduce EMI radiation or radio disturbance according to the guidelines by the Federal Communications Commission or International Special Committee on Radio Interference (CISPR) [5]–[6]. In high speed data-link applications, the SSCs are used for their main clock generator. Fig. 1 shows the power spectral

E

Manuscript received September 4, 2014; revised March 3, 2015; accepted June 4, 2015. Date of publication July 17, 2015; date of current version December 11, 2015. This work was supported by the Basic Science Research Program through the National Research Foundation of Korea funded by the Ministry of Education (2013R1A1A2060885), the MSIP, Korea, under the ITRC support program NIPA-2013-(H0301-13-1013), and the Chung-Ang University Excellent Student Scholarship in 2015. The authors are with the School of Electrical Engineering, ChungAng University, Seoul 156-756, South Korea (e-mail: ryuhyuk@naver. com; [email protected]; [email protected]; [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TEMC.2015.2442618

Fig. 2. Main specifications of SSCGs: a modulation frequency (fM O D ), frequency deviation (fD E V ), and EMI reduction.

densities (PSD) of conventional clock generator and spread spectrum clock generator (SSCG). The SSCG spreads the spectral power, which would otherwise be concentrated at a single frequency, to reduce the peak radiated energy in compliance with electromagnetic compatibility (EMC) regulations. The main features of the SSCG are defined by modulation frequency (fM OD ), frequency deviation (fDEV ), and EMI reduction (EMIR), as illustrated in Fig. 2. The modulation frequency is the speed of frequency modulation; the frequency deviation is the difference in frequency between the maximal modulated SSC (fm ) and non-SSC (f0 ); the EMI reduction is the difference in power between the peak SSC and non-SSC. The main specifications for various high-speed serial-link standards are summarized in Table I. As the specifications have been updated steadily, a programmable SSCG can reduce the redesign effort to satisfy the various updated requirements for the multipurpose SSCs. The SSCGs have been realized by a phase-locked loop (PLL), in which various modulation techniques are employed to

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TABLE I SSCG SPECIFICATIONS OF HIGH SPEED SERIAL-LINK STANDARDS Specification

Unit

PCI Express b [2]

Serial ATA c [3]

DisplayPort d [4]

Operating frequency a Modulation frequency Frequency deviation EMI reduction

GHz kHz MHz dB

1.25 30–33 –6.25 N/A

0.75 / 1.5 30–33 –3.75 / –7.5 >7

0.81 / 1.35 30–33 –4.05 / –6.75 N/A

a

Operating frequency is calculated by assuming that the transferred data is coded using non-return to zero (NRZ) format. b PCI Express has a data-rate of 2.5 Gb/s. c Serial ATA standard has multiple data rates of 1.5 and 3.0 Gb/s. d DisplayPort low-rate and high-rate have data rates of 1.62 and 2.7 Gb/s, respectively.

generate a spread spectrum [7]–[17]. Among them, an open-loop control technique is the simplest way to implement. This technique directly controls the voltage-controlled oscillator (VCO) with a triangular signal. This signal is generated by an analog-todigital converter or a programmable charge pump (CP) [7]–[11]. By changing the magnitude and period of the triangular signal, the programmable SSC can be achieved [7], [8]. However, the nonlinear varactor characteristic of an LC-VCO or a nonlinear current mirroring factor of a ring-based oscillator causes nonlinear relation between the frequency and control signal, resulting in an irregular frequency modulation. Therefore, an additional compensation circuit is required to enhance the modulation linearity [15]. A closed-loop control technique adjusts the frequency-division ratio (FDR) of a PLL periodically with a delta-sigma modulator (DSM) to generate the SSC [13]–[17]. This technique is more robust to the nonlinear VCO gain than the open-loop control technique because a modulated frequency is determined by the closed-loop phase feedback of the PLL. Until now, the SSCGs using this technique have been designed to support a single dedicated standard with fixed modulation parameters. A few SSCGs employing the programmable modulation have been reported, which used a dual-DSM, a look-up table, or a static random access memory (SRAM) [18]–[21]. However, they are aimed to generate a complex nonlinear profile for achieving large EMI reduction in a single dedicated application rather than multipurpose applications. This paper proposes a close-loop control based SSCG using a simple linear frequency modulator (LFM). The SSCG supports various programmable modulation profiles with fine frequency resolution in a wide operating frequency range for various SSCG applications. The proto-type SSCG can support the five high speed serial link standards given in Table I, as well as class-D power amplifiers or switching power converters. This paper is organized as follows. The design challenges of SSCGs are described in Section II. The overall SSCG architecture using the proposed programmable LFM is explained in Section III. The experimental results are shown in Section IV, followed by the conclusion in Section V. II. DESIGN CHALLENGES OF SSCGS A. Sensitivities of the Modulation Characteristic Most of the VCOs have an intrinsically nonlinear gain (KVCO ) due to the nonlinear varactor characteristics of an

Fig. 3. Modulation profiles with (a) nonlinear gain, (b) gain offset and (c) gain transition of the VCO.

Fig. 4.

Expected SSC (a) with nonlinearity of the VCO and (b) PVT variations.

LC-VCO or the nonlinear current mirroring factor of a ringVCO. Process, voltage, or temperature (PVT) variation also influences the VCO gain. Fig. 3 depicts the expected problems of a conventional SSCG that uses open-loop control technique. The nonlinear VCO gain, shown in Fig. 3(a), produces a nonlinear modulation profile. This nonlinear profile causes an irregular EMI (eEM I ) PSD, as shown in Fig. 4(a). The unintended peaks in the PSD lowers the EMI reduction [13]. The PVT variation also causes the VCO frequency offset and gain variation, as shown in Fig. 3(b) and (c), respectively. If an SSCG has no controllable options, these profiles produce a frequency deviation error (eDEV ), as shown in Fig. 4(b). In order to prevent these unexpected errors, an additional compensation circuit is needed [11].

RYU et al.: SPREAD SPECTRUM CLOCK GENERATOR USING A PROGRAMMABLE LINEAR FREQUENCY MODULATOR

Fig. 5.

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Required PSD of various standards.

Fig. 7.

Fig. 6. Programmable characteristics of the proposed LFM: (a) programmable frequency deviation (fD E V ) and (b) modulation frequency (fM O D ) control.

In this study, a closed-loop control based SSCG is used to avoid these problems. The proposed LFM applied SSCG makes linear modulation properties by changing the FDR of the PLL, although the implemented VCO has nonlinear gain. B. Multipurpose Operation In high speed serial-link applications, the frequency deviation ratio is defined as a fraction of their operating frequency, such as –5000 ppm or –0.5%. The modulation frequency is designated as an absolute quantity from 30 to 33 kHz. These specifications are almost identical in high speed serial-link applications except the operating frequency. Fig. 5 shows the required PSD of the five SSCG standards. To support these multistandards with a single SSCG, the frequency modulation properties such as frequency deviation and modulation frequency should be adjustable regardless of the operating frequency. In switching power converters or class-D power amplifiers, SSCGs have been also employed to reduce the radiated power. The frequency deviation and modulation frequency are determined by the allowed radiated power or radio disturbance [5], [6]. For example, the SSCGs used in the switching power converter [22], [23] and class-D power amplifier [24, [25] have the frequency deviation ratio of 4–30% and modulation frequency of 1–60 kHz. Therefore, the proposed SSCG with programmable modulation capability as well as a fine frequency resolution can also be applied to these applications. Fig. 6(a) shows the PSD of the down spread SSC with variable frequency deviations. Fig. 6(b) illustrates the SSC output frequency when the modulation frequency changes. The proposed LFM was designed to meet the following properties. First, the frequency deviation and modulation frequency are adjustable, as shown in Fig. 6. Second, the frequency resolution is programmable for various applications. Finally, additional costs for realizing the programmable operation should be minimized.

Overall architecture of the proposed SSCG.

III. DESIGN OF THE PROGRAMMABLE SSCG The overall architecture of the proposed SSCG is shown in Fig. 7. The SSCG consists of two parts: a fractional-N PLL and a programmable LFM. The DSM-based fractional-N PLL consists of a phase frequency detector (PFD), a CP, a loop filter (LF), a ring-type VCO, a multimodulus frequency divider (MMFD), and a DSM. The LFM controls the FDR of the frequency divider in order to modulate the output frequency. The FDR-sweep modulates the control voltage of the VCO (VCTRL ) through the PFD and CP. Consequently, the frequency deviation and modulation frequency can be controlled. The LFM generates the programmable modulated FDR, Δ(N.F), according to the mode inputs, where N is the integer division ratio and F is the fraction division ratio. The mode inputs of the LFM are composed of 32-bit data, which are converted into the frequency deviation and modulation frequency. The output control bits of the LFM are combinations of fractional and integer control parts. Once the SSCG operates, the fractional part controls the fractional ratio of the DSM, while the integer part maintains the initial input value. When the frequency modulation scale exceeds 1-division ratio of the MMFD, the LFM starts the integer part control by adding 1-division ratio and resets the integrated fractional part information. The DSM generates a delta-sigma modulated FDR to provide a fractional division function using the initial value, (N.F)INIT . The final modulated FDR (N.F)M OD can be obtained by summing Δ(N.F) and the output of the DSM. A. Programmable LFM The overall structure of the LFM is depicted in Fig. 8(a). The LFM is composed of a timing generator, a modulation profile generator, and an input multiplexer. The LFM has two 32-bit data inputs, which include information for LFM operation. The two modes are executed alternately by the mode shift signal. Fig. 8(b) shows the 32-bit modulation control data format, which allocates two bits for the mode definition (MDEF ), 16 bits for the modulation period (NM OD ), eight bits for the unit modulation

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Fig. 8.

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 57, NO. 6, DECEMBER 2015

Proposed programmable LFM: (a) overall structure, (b) programmable data input, and (c) timing diagram.

scale (ΔF), and six bits for the unit time period (NSTEP ) from the most significant bit in descending order. The two-bit MDEF defines four modes: hold (00), up (01), down (10), and reset (11). To generate the triangular modulation profile, the LFM uses the up and down mode. The mode is shifted when one mode finishes its operation and transits to another mode. The triangular modulation profile can be obtained by repeating these two modes. The mode definition has two extra modes, such as hold and reset. The hold mode maintains the present frequency and the reset mode returns the frequency to the initial frequency. The step counters generates a timing clock TSTEP for the mode counter and the first order integrator, which is determined by the reference period TREF and NSTEP as TSTEP = TREF · NSTEP . The mode counters create a timing clock TM OD for the mode shift, which is generated by TSTEP and NM OD as TM OD = TSTEP NM OD . The mode controller in the modulation profile generator selects a modulation step frequency among +ΔF and –ΔF according to the mode definition (MDEF ). This step frequency is integrated and is supplied to the frequency divider of the PLL. The timing diagram for the LFM is shown in Fig. 8(c). The step counter adjusts TSTEP according to the NSTEP value, and the mode counter counts TSTEP in NM OD times. The modulation period TM OD is set by the counting of the mode counter. The period of the mode shift is TM OD . The mode shift signal resets all of the digital counters and selects another input data in the multiplexer. Then, the new input data are read, all the components are reset to the initial values, and the LFM starts the next mode operation. Fig. 9 shows a flowchart of the proposed frequency modulation algorithm. Once the frequency modulator begins modulation process, the data output, Δ(N.F), is initially set to zero and the mode is set to the first mode. As the input data is read, if the mode is the up mode (MDEF = 0), ΔF is added to Δ(N.F), or if the mode is the down mode (MDEF = 1), ΔF is subtracted from Δ(N.F). At the same moment, NM OD is decreased by one at each calculation. These calculating processes are performed in a cycle, which lasts as long as the given NSTEP value. The

Fig. 9.

Flowchart of the frequency modulation algorithm.

adding or subtracting cycle is repeated until NM OD falls to zero. The mode shift occurs when the NM OD value is equal to zero. Then, MDEF is changed to indicate the next mode. According to these repeated processes, Δ(N.F) is modulated continuously. The frequency deviation and modulation frequency is determined by ΔF, NSTEP , NM OD , and TREF . The frequency deviation is calculated as fDEV = ΔF · NM OD ·

215

1 · TREF

(1)

RYU et al.: SPREAD SPECTRUM CLOCK GENERATOR USING A PROGRAMMABLE LINEAR FREQUENCY MODULATOR

Fig. 10.

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Schematic of the PLL circuits (open-loop path).

where the factor of 1/215 comes from the 15-bit DSM. And the modulation frequency is derived as fM OD =

1 2TM OD

=

1 2TREF · NSTEP · NM OD

.

(2)

Since TM OD corresponds to half of a modulation period, the fM OD is two times slower than (1/TM OD ). A proto-type SSCG was designed to verify these programmable LFM characteristics. The frequency range VCO is from 0.4 to 2 GHz. The reference clock of 20 MHz is employed. The SSCG has a frequency deviation from 610 Hz to 1.6 GHz (0–80%) and modulation frequency range from 2.38 Hz to 100 kHz. The minimum frequency resolution is 610 Hz (fREF /215 ). Most of the SSCG standards for high speed seriallink demand a modulation frequency range from 30 to 33 kHz and a frequency deviation of –0.5%. The frequency deviation of –0.5% corresponds to a few megahertz, as shown in Table I. The proposed SSCG can cover the required multistandard specifications by using the control options without any additional circuitry. The proposed LFM only uses the reference clock (TREF ) and digital codes provided from the external source to modulate the frequency, whereas previous SSCGs use the intrinsic PLL properties, such as the VCO gain and CP current. Therefore, the proposed modulation scheme does not suffer from a nonlinear VCO gain and variations of the internal PLL parameters due to the PVT variations. Furthermore, since the LFM is designed using serial toggle flip-flop chains, and the other blocks are realized with standard digital cells, the proposed SSCG achieves a small chip area with very low power consumption. B. PLL Fig. 10 shows the circuit schematic of the PLL, which consists of a CP, an LF, and a VCO. The frequency dividers and LFM are not shown in Fig. 10. The VCO is designed with a voltage to current (V–I) converter and a current-controlled oscillator (CCO). The CP is designed in differential mode with an operational amplifier (OPA) feedback. The unit-gain OPA continuously matches the voltages between each differential node,

Fig. 11.

Implemented pseudodifferential CCO with output buffers.

which prevents static up-down current mismatch [26]. The LF is designed with a third-order low-pass filter to reduce the outband noise from the DSM. The LF voltage VCTRL is converted to the current (IX = VCTRL /RX ) in the V–I converter, which consists of an OPA and reference resistor RX . This current is applied to the CCO with the multiplication factor α and is also fed back to the CP with the multiplication factor β. Fig. 11 shows a detailed schematic diagram of the CCO. The CCO consists of four stages of pseudodifferential inverters, which have a high power-supply rejection ratio, low-power operation, and linear gain over a wide operating frequency range [27]–[29]. An output buffer is added to the output of ring stages to attain the differential rail-to-rail outputs. The CP and VCO use a self-feedback current biasing scheme [27], [30]. Since the current of the V–I converter (IX ) is mirrored to that of the CP (ICP ) with multiplication factor β and to the CCO (ICCO ) with multiplication factor α, the PLL can be modeled as shown in Fig. 12. This biasing configuration can maintain an optimal PLL

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Fig. 12.

IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, VOL. 57, NO. 6, DECEMBER 2015

Phase-domain model of the self-current feedback biasing scheme.

Fig. 14.

Fig. 13.

Measured and simulated CCO output frequencies.

Die micrograph.

bandwidth over a wide output frequency range [27]. The loop bandwidth can be derived using an equivalent phase domain model as f3dB = η ·

ICP R1 · · fREF IX RX

(3)

where η (0.76 in this study) is the correlation factor of the CCO, which depends on the linearity of the KCCO and the oscillation frequency. (3) indicates that the loop bandwidth only tracks the reference frequency, while the other design values are constant. Therefore, the implemented PLL has a loop bandwidth that is independent of the feedback dividing ratio (N.F), as well as of the PVT variations. IV. EXPERIMENTAL RESULTS

Fig. 15. Measured frequency modulation profiles at f0 = 800 MHz (a) with fD E V = 4, 8, and 16 MHz and (b) with fM O D = 2.5, 5, and 10 kHz.

The proposed programmable SSCG was fabricated using 1P6M 0.13-μm CMOS technology. The die micrograph is illustrated in Fig. 13. The SSCG occupies 0.11 mm2 . The overall current consumption is 6.28 mA from a 1.2-V supply including the output buffer at 1-GHz operating frequency. The proposed SSCG has a smaller chip area and lower power consumption than that of previous works [7]–[17], owing to the simple circuitry of the proposed LFM. Fig. 14 shows the measured CCO output frequency with the simulation result. The CCO output frequency range was 0.4–2 GHz according to the CCO current (ICCO ) range of

0.24–1.5 mA. The implemented CCO provides a full frequency coverage for five high-speed serial-link standards. The modulation profiles were tested by adjusting the mode input parameters (ΔF, NSTEP , and NM OD ). Fig. 15(a) shows the three modulation profiles at f0 = 800 MHz and fREF = 20 MHz with fDEV = 4, 8, and 16 MHz. When ΔF = 53, NSTEP = 8, and NM OD = 125, the frequency deviation is 4 MHz according to (1). In this way, the 8 and 16-MHz frequency deviations are also determined. Fig. 15(b) shows the example with

RYU et al.: SPREAD SPECTRUM CLOCK GENERATOR USING A PROGRAMMABLE LINEAR FREQUENCY MODULATOR

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Fig. 16. Measured output spectrums and modulation profiles of the proposed SSCG: (a) DisplayPort low-rate, (b) DisplayPort high-rate, (c) PCI Express 2.5 Gb/s, (d) Serial ATA 1.5 Gb/s, (e) Serial ATA 3.0 Gb/s, and (f) up spread example.

modulation frequency variations. The input combination of ΔF = 53, NSTEP = 8, and NM OD = 125 yields a 10-kHz modulation frequency, as well as 4-MHz frequency deviation. In the same way, the 5- and 2.5-kHz modulation frequencies are also obtained. To demonstrate the multistandard operation, the output spectrums and frequency modulation profiles having various

operating frequencies and frequency deviations were tested. Fig. 16(a) and (b) shows the low-rate and high-rate DisplayPort. The operating frequencies f0 are 810 MHz and 1.35 GHz with fDEV = −4.05 and –6.75 MHz, respectively. Fig. 16(c) shows 2.5-Gb/s PCI Express with f0 = 1.25 GHz and fDEV = −6.25 MHz. Fig. 16(d) and (e) shows the 1.5- and 3.0-Gb/s Serial ATA, which have f0 = 750 MHz and 1.5 GHz with

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TABLE II MEASUREMENT SUMMARY AND COMPARISON WITH PREVIOUS WORKS Specifications

Unit

This study

JSSC 2010 [20]

JSSC 2012 [21]

TEMC 2009 [17]

TCAS-I 2010 [16]

TCAS-I 2013 [10]

Modulation method

–

Delta-sigma

Delta-sigma

VCO directly

– GHz

Ring 0.4–2

Ring 3.5

Delta-sigma + VCO directly Ring 1.5

Delta-sigma

Oscillator type Operating Frequency (f 0 ) Modulation Frequency (f M O D ) Frequency Deviation (f D E V ) Programmable Resolutiona

Digital delay-line Ring 0.18–1.27

Ring 3

LC 6

kHz

0–100

19–4961

31–95

31.25

33

31.5

MHz /%

0–1600 / 0–80

0–635 / 0–50

7.6 / 0.507

15 / 0.5

30 / 0.5

–

Δ fM O D = Δ fD E V = 610 Hz

No

No

No

dB

10.24–13.94e

Δ fM O D = 19.4 kHz Δ fD E V = 2.48 MHz 10.6–20.5g

17.5–122.5 / 0.5–3.5 Δ fM O D = 30 kHz Δ fD E V = 17.5 MHz 19.14–24.8j

10.14

14.5

12.5

dB

10.24–16.91

12.73–13.48

12.7–15.47

10.08

11.51

6.5

2.44 0.85 130 23.72 0.076

5.49 0.82 180 27 0.211

5.4 1.62 130 14.7 0.211

2.06 1.24 90 14.4 0.533

EMI reduction (EMIR)b Normalized EMI reduction (EMIR(n) )c RMS Jitterd RMS Jitter × f0 CMOS technology Power consumption Chip area

ps % nm mW mm2

f

16.7 1.34 130 6.28 0.11

h

12.8 1.6 65 44i 0.044

a

Calculated under worst case condition. b Measured with 100 kHz RBW. c EMIR(n) = EMIR – 10log[(f D E V + 2f M O D ) / 7.56 MHz]. d Measured under SSC-off condition. e Measured under f 0 = 0.75–1.5 GHz, f D E V = f 0 / 200 (5%), and f M O D = 30–33 kHz condition. f Measured at f 0 = 800 MHz. g Measured under f 0 = 750 MHz, f D E V = 3.75–45 MHz, and f M O D = 100 kHz condition. h Measured at f 0 = 1.25 GHz. i SRAM consumes much power (65% of total power consumption). j Measured under f D E V = 17.5–122.5 MHz and f M O D = 31 kHz condition.

fDEV = −3.75 and –7.5 MHz, respectively. To show the upspread modulation, an example was tested at f0 = 800 MHz with fDEV = +4 MHz, as shown in Fig. 16(f). The EMIR was measured to be approximately 10.24 to 13.94 dB with 100-kHz resolution bandwidth (RBW), according to the EMI measurement guidelines of the IEEE standard ANSI C63.2-2009 [31]. EMIR depends on the modulation parameters. According to Carson’s rule [32], the PSD in a continuously modulated spectrum is inversely proportional to the Carson’s bandwidth, CBW = 2 (Δf + fM OD ), where Δf is a peak frequency deviation under center spreading condition. In our case, Δf = fDEV /2 and CBW = fDEV + 2fM OD . For a fair comparison with other SSCGs, a normalized EMI reduction EMIR(n ) is introduced as   C BW EMIR(n ) = EMIR − 10 log (n ) CBW   fDEV + 2fM OD = EMIR − 10 log (4) (n ) CBW where CBW (n ) is a normalization factor. In this study, CBW (n ) is set to 7.56 MHz according to Serial ATA 3.0 Gb/s standard (fDEV = 7.5 MHz, fM OD = 30 kHz). The calculated EMIR(n ) range using the measured EMIR in Fig. 16 is from 10.24 to 16.91 dB. Fig. 17 shows the measured phase noise at f0 = 800 MHz. The phase noise and the corresponding integrated root-meansquare (RMS) jitter are –92.44 dBc/Hz at 1-MHz offset frequency and 16.7 ps, respectively. Since the RMS jitter is a frequency- dependent parameter [33], a frequency-normalized

Fig. 17.

Measured phase noise and integrated rms jitter at f0 = 800 MHz.

jitter (RMS Jitter × f0 ) including both the measured jitter and operating frequency is more appropriate for comparison. The normalized jitter of the proposed SSCG is 1.34%, which value is sufficient to satisfy the required jitter specifications of 1.8–1.875% given by [4], [5]. The output spectrums, modulation profiles and phase noise were measured by an Agilent E4440A PSA Spectrum Analyzer and E5052B Signal Source Analyzer. Table II presents the measurement summary and comparison with previous SSCGs. The proposed SSCG has a wider frequency range, variable frequency deviation and modulation frequency, and finer frequency resolution. The other common

RYU et al.: SPREAD SPECTRUM CLOCK GENERATOR USING A PROGRAMMABLE LINEAR FREQUENCY MODULATOR

electrical parameters, such as EMI reduction, jitter, power consumption, and chip area, are comparable with previous works. The proposed SSCG successfully demonstrates simple, precise, and versatile modulation properties for satisfying the various EMI/EMC regulations of multistandard electronic devices, while the additional costs and design efforts are minimized in comparison with the other SSCGs.

[18] [19]

[20]

V. CONCLUSION This paper proposes a versatile SSCG based on a programmable LFM, which can be applied to be used multipurpose applications using a single SSCG. The proposed SSCG has a wide modulation range and a fine modulation step, due to the programmable options of the internal LFM. The SSCG is realized in a small chip with low power consumption. The experimental results demonstrate that the proposed SSCG can support five standards of SSCG applications: PCI Express, Serial ATA 1.5 and 3 Gb/s, DisplayPort low and high rate. The proposed SSCG will be able to satisfy future requirements due to its programmable characteristics.

[21]

[22]

[23]

[24] [25]

REFERENCES [1] K. B. Hardin, J. T. Fessler, and D. R. Bush, “Spread-spectrum clock generation for the reduction of radiated emissions,” in Proc. IEEE Int. Symp. Electromagn. Compat., 1994, pp. 227–231. [2] Radio Frequency Devices, FCC 47 CFR Part 15, 2008. [3] Information Technology Equipment—Radio Disturbance Characteristics —Limits and Methods of Measurement, CISPR Publication 22 Edition 6.0, 2008. [4] PCI Express Base Specification Revision 3.1, PCI-SIG, 2014. [5] Serial ATA Revision 3.2, Serial ATA International Organization, 2013. [6] Display Port Standard Version 1, Revision 2, Video Electronics Standard Association, 2010. [7] H.-H. Chang, I.-H. Hua, and S.-I. Liu, “A spread-spectrum clock generator with triangular modulation,” IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 673–676, Apr. 2003. [8] Y.-B. Heish and Y.-H. Kao, “A fully integrated spread-spectrum clock generator by using direct VCO modulation,” IEEE Trans. Circuits Syst. I, vol. 55, no. 7, pp. 1845–1853, Aug. 2008. [9] V. C. D. LeBlanc, B. T. Voegeli, and T. Xia, “Dual-loop direct VCO modulation for spread spectrum clock generation,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2009, pp. 479–482. [10] C.-H. Wong and T.-C. Lee, “A 6-GHz self-oscillating spread-spectrum clock generator,” IEEE Trans. Circuits Syst. I, vol. 60, no. 5, pp. 1264– 1273, May 2013. [11] W.-Y. Lee and L.-S. Kim, “A spread spectrum clock generator for display port main kink,” IEEE Trans. Circuits Syst. II, vol. 58, no. 6, pp. 361–365, Jun. 2011. [12] D.-S. Shen and S.-I. Liu, “A low-jitter spread spectrum clock generator using FDMP,” IEEE Trans. Circuits Syst. II, vol. 54, no. 11, pp. 979–983, Nov. 2007. [13] J.-W. Lee, H.-J. Kim, and C. Yoo, “Spread spectrum clock generation for reduced electro-magnetic interference in consumer electronics devices,” IEEE Trans. Consumer Electron., vol. 56, no. 2, pp. 844–847, May 2010. [14] S.-Y. Lin and S.-I. Liu, “A 1.5 GHz all-digital spread-spectrum clock generator,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3111–3119, Nov. 2009. [15] T. Ebuchi, Y. Komatsu, T. Okamoto, Y. Arima, Y. Yamada, K. Sogawa, K. Okamoto, T. Morie, T. Hirata, S. Dosho, and T. Yoshikawa, “A 125–1250 MHz process-independent adaptive bandwidth spread spectrum clock generator with digital controlled self-calibration,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 763–774, Mar. 2009. [16] F. Pareschi, G. Setti, and R. Rovatti, “A 3-GHz serial ATA spread spectrum clock generator employing chaotic PAM modulation,” IEEE Trans. Circuits Syst. I, vol. 57, no. 10, pp. 2577–2587, Oct. 2010. [17] Y.-H. Kao and Y.-H. Hsieh, “A low-power and high-precision spread spectrum clock generator for serial advanced technology attachment

[26] [27]

[28]

[29] [30]

[31] [32] [33]

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applications using two-point modulation,” IEEE Trans. Electromagn. Comp., vol. 51, no. 2, pp. 245–254, May 2009. H.-M. Park, H.-B. Jin, and J.-K. Kang, “SSCG with Hershey-kiss modulation profile using dual sigma-delta modulators,” IEICE Electron. Express, vol. 7, no. 18, pp. 1349–1353, Sep. 2010. K. Hardin, R. A. Oglesbee, and F. Fisher, “Investigation into the interference potential of spread-spectrum clock generation to broadband digital communications,” IEEE Trans. Electromagn. Comp., vol. 45, no. 1, pp. 10–21, Feb. 2003. D. D. Caro, C. A. Romani, N. Petra, A. G. M Strollo, and C. Parrella, “A 1.27 GHz, all-digital spread spectrum clock generator/synthesizer in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1048–1060, May 2010. S. Hwang, M. Song, Y.-H. Kwak, I. Jung, and C. Kim, “A 3.5 GHz spread-spectrum clock generator with a memoryless Newton-Raphson modulation profile,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1199– 1208, May 2012. J. Balcells, A. Santolaria, A. Orlandi, D. Gonzalez, and J. Gago, “EMI reduction in switched power converters using frequency modulation techniques,” IEEE Trans. Electromagn. Comp., vol. 47, no. 3, pp. 569–576, Aug. 2005. F. Pareschi, G. Setti, R. Rovatti, and G. Frattini, “Short-term optimized spread spectrum clock generation for EMI reduction in switching DC/DC converters,” IEEE Trans. Circuits Syst. I, vol. 61, no. 10, pp. 3044–3053, Oct. 2014. M.-L. Yeh, W.-R. Liou, H.-P. Hsieh, and Y.-J. Lin, “An electromagnetic interference (EMI) reduced high-efficiency switching power amplifier,” IEEE Trans. Power Electron., vol. 25, no. 3, pp. 710–718, Mar. 2010. X. Ming, Z. Chen, Z.-K. Zhou, and B. Zhang, “An advanced spread sprectrum architecture using pseudorandom modulation to improve EMI in class D amplifier,” IEEE Trans. Power Electron., vol. 26, no. 2, pp. 638–646, Feb. 2011. J.-S. Lee, M.-S. Keel, S.-I Lim, and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electron. Lett., vol. 36, no. 23, pp. 1907–1908, Nov. 2000. W. Jung, H. Choi, C. Jeong, K. Kim, W. Kim, H. Jeon, G. Koo, J. Kim, J. Seo, M. Ko, and J. Kim, “A 1.2 mW 0.02 mm2 2 GHz current-controlled PLL based on a self-biased voltage-to-current converter,” in Proc. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 310–311. K.-Y. K. Chang, J. Wei, S. Li, Y. Li, K. Donnelly, C. Huang, and S. Sidiropoulos, “A 0.4–4-Gb/s CMOS quad transceiver cell using onchip regulated dual-loop PLLs,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 747–754, May 2003. M. Mansuri and C.-K. Yang, “A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1804–1812, Nov. 2003. J. G. Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, “Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1795–1803, Nov. 2003. American National Standard for Electromagnetic Noise and Field Strength Instrumentation, 10 Hz to 40 GHz Specifications, ANSI C63.2-2009. J. R. Carson, “Notes on the theory of modulation,” Proc. IRE, vol. 10, no. 1, pp. 57–64, Feb. 1922. A. Hajimiri, S. Limotyrakis, and T. H. Lee, “Jitter and phase noise in ring oscillators,” IEEE J. Solid-State Circuits, vol. 34, no. 6, pp. 790–804, Jun. 1999.

Hyuk Ryu (S’12) received the B.S. and M.S. degrees from the School of Electrical Engineering, ChungAng University, Seoul, South Korea, in 2010 and 2012, respectively. He is currently working toward the Ph.D. degree at the School of Electrical Engineering, Chung-Ang University. His research interests include CMOS RF transceivers, mm-wave circuits, and all-digital frequency synthesizers. He was a recipient of the IEEE International SOC Design Conference Design Award in 2012 and the IEEE Seoul Section Student Paper Contest Bronze Award in 2013.

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Sangyong Park (S’11) received the B.S. and M.S. degrees from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2011 and 2013, respectively. He is currently working toward the Ph.D. degree at the School of Electrical Engineering, Chung-Ang University. His research interests include delta-sigma modulators, the design of linear regulators for wireless communication, and clock and data recovery circuits for high speed communication using CMOS technology.

Eun-Taek Sung (S’14) received the B.S. degree from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2014. He is currently working toward the M.S. degree at the School of Electrical Engineering, Chung-Ang University. His research interests include the design of lowpower and energy-efficient sensor interfaces, data converters, and high performance clock generators for wireless sensor networks.

Seung-Gi Lee received the B.S. degree from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2015. He is currently working toward the M.S. degree at the School of Electrical Engineering, Chung-Ang University. His research interests include the design of linear regulators, high power amplifier, and CMOS RF transceiver design for the wireless communication.

Donghyun Baek (S’98–M’07–SM’13) received the B.S., M.S., and Ph.D. degrees from the Department of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 1996, 1998, and 2003, respectively. From 2003 to 2007, he was with the System LSI Division, Samsung Electronics Company, Ki-heung, Korea, where he designed mobile broadcasting RF receivers such as DVB-H, TDMB, and ISTB-T and led the CMOS power amplifier project for handsets. In 2007, he joined the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, where he is currently an Associate Professor. His research interests include analog, RF, and mixed-mode circuit designs for mobile system on chip, radar on chip, and sensor on chip integrated circuits.