A Study of Input Filter Design for High Power High

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A Study of Input Filter Design for High Power High Frequency Space Applications Conference Paper · June 2016

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A Study of Input Filter Design for High Power High Frequency Space Applications Bijeev N V∗ , Vasantray H Jani† , Peter K Joseph‡ and Naveen B Sharma§ Department of Space, Space Application Center , Indian Space Research Organization ISRO-SAC, Ahmedabad, Gujarat, India Email: ∗ [email protected], † [email protected], ‡ [email protected], § [email protected]

Abstract—Satellites are energized by the dc output power of solar panel. Every subsystem of a satellite requires stable and highly efficient power supply. The selection and design of an input filter is potentially important in power supply design. As the number of stages increases, the attenuation required will reduces; However the design complexity increases.This paper unveils the optimization of a two stage input filter for realizing a Phase Shifted Full bridge (PSFB) topology Electronic Power Conditioner for space applications. Attenuation challenges and filter interaction problems are tried to avoid with a novel optimization methodology. The experimental wave-forms and simulations in MATLAB and PSPICE are shown to validate the results.

also helps to prevent the switching noise of the system entering the bus. Many types of filter configurations are available[3-11] The required attenuation of an input filter critically depend on the input peak current[2-3]; and is given by the equation,

Keywords: Full bridge dc/dc converter; Middle Brooke criteria; Matlab-Simulink; Orcad-Pspice;EPC;

Vnoise = F irst Harmonic × LISN Impedance (Ref er M IL − ST D − 461E) = 6.09 × 36 = 218.484 V

I. I NTRODUCTION The primary objective of the satellite power system is to supply continuous electrical power to various Electronic, RF, Optical, Electro-Mechanical payloads throughout varying modes of operation like sunlit-condition, eclipse condition, varying signal traffic conditions, space environmental conditions etc. This task not only implies power generation and storage, but also the management of that power; its distribution throughout the satellite; consistent monitoring of power consumption; and ultimately, the protection of onboard electronics from faults that may form and propagate throughout the system.This propagation can be avoided or reduced by the implementation of a proper common mode or differential mode input filter. Electronic Power Conditioners (EPCs) are SMPS based regulated power supplies suitable to fit into a satellite platform and its main function is to energize various active subsystems of a satellite payload. Stability of EPC is very much sensitive to filter interactions, as explained by Middle-Brooke Criteria [1].This paper elaborates on the design and implementation of a novel differential mode input filter for a high power Phase Shifted Full Bridge EPC to energize a GaN based SSPA (Solid State Power Amplifier) subsystem [2] II. I NPUT F ILTER D ESIGN The primary input is a raw DC through power bus from solar panel in space. But it contains ripples and noise. The function of input filter is to prevent noise entering from bus to the system (block AC and pass DC). Input filter

Iavg 8.581 = = 9.534A D 0.9 2 × Ip−p = 6.069A F irst harmonic Irms = π Ip−p =

(1) (2)

(3)

Vnoise (indBµV )

= 20logVnoise = 166.788dBµV Attenuation required(dBµV ) = 166.788 − 67 = 99.788dBµV (4) Since the conventional bus is designed with nominal voltage of 28V and at this voltage the desired attenuation 67dBµV. But for 70V to 150V bus there is a relaxation of 6dB.We can afford filter attenuation about 99.78-6=93.78dB.The filter is designed for 99.78dBµV attenuation. A. Single Stage Filter The corner frequency of the differential filter, Fc

attenuation

40 = Fsw × 10( −99.788 = 200k × 10 40 = 640Hz

)

(5)

High value of capacitor is chosen to minimize the inductor value. So we choose the highest value; i.e. 120uF Since; Fo = 2π√1LC (6) L1

= =

1 4π 2 Fc2 C 515.346µH

(7)

R

q L = C = 2.07Ω

(8)

Fig. 1: Single stage filter Fig. 1 is the circuit diagram of the designed single stage filter.And in Fig. 3, the pink line shows the Magnitude bode plot of single stage filter.

B. Two Stage Filter

Fig. 3: Graphical representation of magnitude plot of 4 pole, 2 pole and 3 pole filter Greater number of components in the filter, the more degree of freedom available for optimization. Two stage filter with optimum damping is designed for required attenuation.

The corner frequency of the differential filter, Fc

= Fsw × 10

attenuation 60

III. INDUCTOR DESIGN = 4.34kHz

(9)

Here the attenuation level is high because of the loading effect of the second stage filter on the first stage filter and the ESR value[3] The 10µF capacitor is chosen for designing. The filter elements are designed based on the circuit equations as explained in[3]; Fc L1

=

L2

=

1 2π 6 × LC

(10)

1 = 22.41µH 4π 2 Fc2 C

(11)

6 × L1 = 134.46µH

(12)

=

√

L3 value is negligibly small due to the low current value. q L (13) R = 4×C = 0.748Ω Fig. 2 is the circuit diagram of the designed Two stage filter. And in Fig. 3, the blue line shows the Magnitude bode plot of two stage filter.

Fig. 2: Circuit Diagram of two stage filter

Since the circuit of the input filter is fixed as shown in Fig. 4, we can design the inductor from the specified values [11].

Fig. 4: Circuit Diagram of two stage filter Current flowing through L1 = L2 = Idc (avg) = 8.581A . The noise current flowing through L3 is always less than 0.5A. So for the design purpose we assuming the noise current flowing through L3 = 0.5A A. L2 (40µH) L I LI 2

= 40 × 10−3 mH = 0.040mH = 8.581A = 0.040 × 8.5812 = 2.9403

(14)

From the DC bias core selection chart[11], select permeability as 60µ ,since it satisfies the LI 2 criteria and available for testing.So choose part number as 55071.Which have inductance at 1000turns = 61mH8%. From DC bias core selector chart NHI = 0.154 . The number of turns, r L N = 1000 × = 25.6 (15) L1000

Providing a 20% roll-off regarding the saturation, the effective number of turns, N = 25.6 + 25.6 × 0.20 = 31 We know the value of

(16)

H N I ,so

H 0.154 × 31 × 8.581

H = NI × N I = 40.96Oersteds

(17)

For permeability Vs DC bias graph, choose plot for 60µ at 40.96 Oersteds. It yields 12% .Multiplying the nominal inductance by 88% yields 53.88mH/1000 turns .So at the time of saturation, the inductance of this core with 31 turns is thus

L1 N12

=

L1 312

=

L2 N22 51.5µH

(18)

Item Fop LI 2 Part µ Core dim.(mm) Weight AL (L1000 ) H (Oersteds) Core loss Tuns Copper loss Wire gauge Winding factor

L1 (8µH) 200kHz 0.6 55206 125µ OD=21.1 ID=12.07 Ht=7.11 10gm 68mH

MPP cores L2 (40µH) 200kHz 3 55071 60µ OD=33.8 ID=19.3 Ht=11.61 47gm 61mH

L3 (5µH) 200kHz 0.00125 55117 200µ OD=17.4 ID=9.53 Ht=7.11 6.8gm 115mH

34.13

40.96

1.224

28.38W 13 1.193W

41.58W 31 4.027W

0.0867W 7 0.006W

Litz wire; 40AWG 6727C.M 38.76%

Litz wire; 40AWG 6727C.M 36.10%

26AWG 254.1C.M

copperarea windowarea

=36.10% (Fea-

Fop LI 2 Part µ Core dim. (mm) Weight AL (L1000 ) H (Oersteds) Core loss No. of winding Copper loss Wire gauge Winding factor

Similarly the calculations for L1 and L3 are done from [11] and the results are shown in Table 1 .The design of L2 done with high flux core also. These cores are similar to standard MPP (molypermalloy powder) cores which have approximately an 80% nickel composition, but the high flux types have certain advantages that make them quite useful for applications involving high power or high DC. HF cores have a saturation flux density of 15000 gauss as compared to 7000 gauss for standard MPP cores or 4500 gauss for ferrites. The core loss of HF powder cores is significantly lower than powdered iron cores. The applications are for In-Line noise filters, Switching regulator inductors, Pulse transformers, Fly-back transformers etc.And the core comparison is validated in Table II.

1.27%

TABLE II: Core comparison Item

So the minimum inductance of 40µH has achieved. The current carrying is 8.581A.To increase the efficiency of operation, we use Litz wire. Because the proximity effect and skin effect is minimum due to special winding pattern of 700 strands with 40AWG (American Wire Gauge). The copper area of this specified Litz wire is 6727 circular mils. (1 circular mils = 5.07 × 10−6 cm2 ) For part number 55071, the window area is 577600 circular mils.

So the winding factor is = sible)

TABLE I: Inductor Design Chart

MPP cores L2 (40µH) 200kHz 3 55071 60µ OD=33.8 ID=19.3 Ht=11.61 47gm 61mH

HF Cores L2 (40µH) 200kHz 3 58322 160µ OD=36.7 ID=21.5 Ht=11.35 48.9gm 150mH

40.96

24.01

41.58W 31

106.63W 20

4.027W

2.695W

Litz wire; 40AWG 6727C.M 36.10%

Litz wire; 40AWG 6727C.M 18.70%

IV. M IDDLE -B ROOKE A NALYSIS

In space grade systems, there should be proper filter interaction between input and ouput side. That is the output impedance of the input filter should be less than input impedance of the converter[1].It will prevent the overlapped filter interaction and there by preventing unwanted sustained oscillations causing instability. The filter interaction of a particular system can be found out by MiddleBrooke Analysis [1] for the state of art optimization.

Fig. 5: Average circuit Switching mode regulators as shown in Fig. 5 have a negative input impedance at low frequencies. An inadequate input filter design can lead to instability. The input impedance of the converter(Zin) and output impedance of the filter(Zout) should be properly selected to guarantee system stability.Impedance curves are plotted for Zin and Zout.If their impedance curves overlap, the net circuit resistance becomes negative which leads to oscillations and system instability. [13]- [17]. So a well separated impedance curves with good Margin ensures the stability. The results are described in following waveform.

Fig. 8: Graphical representation of improved filter interaction The staggering is illustrated in Fig. 8 .So maximum margin is obtained.So system will be optimally stable. V. E FFECT OF F ILTER The function of input filter is to prevent noise entering from bus to the system (block AC and pass DC).

Fig. 9: Circuit without input filter Fig. 6: Graphical representation of poor filter interaction Fig. 6 illustrates the example of poor filter interaction. Here, the output impedance of the input filter and input impedance of the converter are overlapped at some points. At this points, the system will be unstable due to severe sustained oscillations.We have to stagger the peak to increase the margin and for better stability.

Input filter also helps to prevent the switching noise of the system entering the bus.And using Orcad-PSPICE , we tried to analyze the effect of filter and the merits of optimum damping in a closed loop circuit. If the input filter is not present, then the unwanted signals at the input will be passed to the secondary side without any hindrance. Fig. 9 designed using ORCAD-PSPICE,shows the circuit diagram of a converter without an input filter. It is clear that without input filter the pole-zero addition is not effective and the compensation will be no efficient. So even a small noise will cause severe distortion and interference in the system as well as the power bus.

Fig. 7: Middle-Brooke Solved circuit By the proper adjustment of input impedance and the output impedance which is shown in Fig. 7, the peaks can be optimally staggered with better margin.

Fig. 10: Circuit with input filter without damping

Fig. 10 shows the circuit diagram of an un-damped input filter. Here, the effect of pole-zero damping is completely terminated. From Fig. 12, it is clear that the gain margin is very much less in undamped case. So the stability of the system is questionable even at the presence of input filter.

filter and necessity of damping in input filter is presented with simulation results. By considering attenuation and stability criteria, two stage damped filter for high power 500W EPC for GaN based SSPA is designed successfully. Simulations verifies the required performance of the filter. The future scope includes the design of a universal digital control loop for space graded converters, which can be integrated with any bridge topology. R EFERENCES

Fig. 11: Circuit with optimally damped input filter Fig. 11 shows the circuit diagram of an optimally damped input filter. It will generate a phase boosting, as a result the system become more stable. And a very high gain margin is produced.

Fig. 12: Impedance plot of undamped and damped filter An impedance magnitude plot of undamped filter and damped filter are shown in Fig. 12. The plot is obtained by the advanced bode plot drawing tool of PSPICE. So it is clear that the design of damper circuit is crucial for the stability of an electronic system. The under damped and over damped circuits will create stability issues in a large scale. The performance of compensator and the controller will be effective only with the integration of an optimally designed input filter circuit. VI. C ONCLUSION Input filters are the inseparable parts of the EPC circuits.Input Filters are well understood in terms of attenuation and stability. If the output impedance of filter is not much less than the input impedance of power converter then the system can leads to oscillations. This paper has presented the detailed analysis of the power converter stability. Design criteria and methods of Single stage and two stage damped filter are also presented. The effect of input

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