A Variable Threshold Voltage Inverter For Cmos Programmable Logic ...

TÍTULO DE LA TESIS “POWER AND TIMING MODELING OF SUBMICRON CMOS GATES” AUTOR: Josep Lluís Rosselló DIRECTOR: Jaume Segura Fuster FECHA DE LECTURA 22 de Febrero de 2003 PUBLICACIONES DERIVADAS REVISTAS “A Variable Threshold Voltage Inverter for CMOS Programmable Logic Circuits” J. Segura, J.L. Rosselló, J.Morra, H.Sigg, IEEE Journal of Solid-State Circuits, pp.12621265, vol. 33. no. 8 Agosto 1998 "Charge-based analytical model for the evaluation of power consumption in sub-micron CMOS buffers" J.L. Rosselló and Jaume Segura IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems. pp.433-448, vol. 21, no. 4, Abril 2002. "Simple and accurate propagation delay model for submicron CMOS gates based on charge analysis" J.L. Rossello and J. Segura, Electronics Letters, IEE, pp. 772-774, Vol. 38, no. 15, Julio 2002 "An analytical charge-based compact delay model for submicron CMOS inverters", J.L. Rosselló and J Segura, IEEE Transactions on Circuits and Systems I, (Aceptado para su publicación) CONGRESOS Autores: J.L. Rosselló, E. Isern, M. Roca, E. García, J. Segura Título: An analytical model of the charge driven by CMOS buffers Tipo de participación: comunicación a congreso Congreso: XII Design of Circuits and Integrated Systems Conference Publicación: Proceedings, pp. 471-474 Lugar de celebración: Sevilla Fecha: Noviembre 1997 Autores: I. De Paul, R. Picos, J.L. Rosselló, M. Roca, E. Isern, J, Segura, C.F. Hawkins Título: Transient current testing based on current (charge) integration Tipo de participación: comunicación a congreso Congreso: International Workshop on IDDQ Testing Publicación: Proceedings, pp. 26-30 Lugar de celebración: San Jose, California, USA Fecha: Noviembre 1998

Autores: J.L.Rosselló, E.Isern, M.Roca and J.Segura Título: An analytical model of CMOS buffers power consumption Tipo de participación: comunicación a congreso Congreso: XIV Design of Circuits and Integrated Systems Conference Publicación: Proceedings, pp. 125-130 Lugar de celebración: Palma de Mallorca, Baleares, España Fecha: Noviembre 1999 Autores: J.L.Rosselló and J.Segura Título: A physical modeling of the alpha-power law MOSFET model Tipo de participación: comunicación a congreso Congreso: XV Design of Circuits and Integrated Systems Conference Publicación: Proceedings, pp 65-70 Lugar de celebración: Montpellier, Francia Fecha: Noviembre 2000 Autores: J.L.Rosselló and J.Segura Título: A simple power consumption model of CMOS buffers driving RC interconnect lines Tipo de participación: comunicación a congreso Congreso: XI International Workshop on Power and Timing Modeling Publicación: Proceedings, Artículo no. 4.2 Lugar de celebración: Yverdon-Les-Bains, Suiza Fecha: Septiembre 2001 Autores: J.L.Rosselló and J.Segura Título: Power-delay modeling of Dynamic CMOS gates for circuit optimization Tipo de participación: comunicación a congreso Congreso: the International Conference on Computer Aided Design (ICCAD’01) Publicación: Proceedings, pp 494-499 Lugar de celebración: San José, CA, USA Fecha: Noviembre 2001 Autores: J.L.Rosselló and J.Segura Título: Modeling the input-output coupling capacitor effects on the CMOS buffer power consumption Tipo de participación: comunicación a congreso Congreso: XVI Conference on Design of Circuits and Integrated Systems Publicación: Proceedings, pp 613-617 Lugar de celebración: Porto, Portugal Fecha: Noviembre 2001 Autores: J.L.Rosselló and J.Segura Título: A compact charge-based propagation delay model for submicronic CMOS buffers Tipo de participación: comunicación a congreso Congreso: XII International Workshop on Power and Timing Modeling (PATMOS 2002), Publicación: Proceedings, pp 219-228 Lugar de celebración: Sevilla, España Fecha: Septiembre 2002

Autores: J.L.Rosselló and J.Segura Título: A Simple Analytical Description of Power Dissipation in Submicronic CMOS Buffers Tipo de participación: comunicación a congreso Congreso: XVII Conference on Design of Circuits and Integrated Systems Publicación: Proceedings, pp 627-630 Lugar de celebración: Santander, España Fecha: Noviembre 2002 Autores: J.L.Rosselló and J.Segura Título: Power and Timing modeling of Submicron CMOS Gates Tipo de participación: Presentación poster Congreso: 40th Design Automation Conference (DAC’03) Publicación: Proceedings, pp 627-630 Lugar de celebración: Anaheim, CA, USA. Fecha: Junio 2003 Autores: J.L.Rosselló and J.Segura Título: A Compact Charge-Based Crosstalk Induced Delay Model for Submicronic CMOS Gates Tipo de participación: Comunicación a congreso Congreso: XII International Workshop on Power and Timing Modeling (PATMOS 2003) Publicación: Proceedings, pp 627-630 Lugar de celebración: Torino, Italia. Fecha: Septiembre 2003 Autores: J.L.Rosselló and J.Segura Título: A physically-based nth power law MOSFET model for efficient CAD implementation Tipo de participación: Comunicación a congreso Congreso: XVII Design of Circuits and Integrated systems Conference (DCIS’03) Publicación: Proceedings, pp 380-383 Lugar de celebración: Ciudad Real, España. Fecha: Noviembre 2003 Autores: J.L.Rosselló and J.Segura Título: A Compact Propagation Delay Model for Deep-submicron CMOS Technologies including Crosstalk Effects Tipo de participación: Comunicación a congreso Congreso: Design Automation and Test in Europe (DATE’04), Lugar de celebración: Paris, Francia. Fecha: Febrero 2004

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 8, AUGUST 1998

A Variable Threshold Voltage Inverter for CMOS Programmable Logic Circuits J. Segura, J. L. Rosselló, J. Morra, and H. Sigg

Abstract— A programmable input threshold voltage inverter compatible with double gate transistors fabrication processes is presented. Such a circuit is useful as a programmable input threshold buffer for general purpose circuits that can be included in both TTL and CMOS environments, or can be used as low cost analog programmable comparator. A prototype is fabricated and measured.

of the n-MOS and p-MOS transistors, respectively. The values that can take are determined by the relative sizing of the transistors composing the buffer. In the next section we present the design of the inverter, while the experimental results are reported in Section III. Finally, the conclusions are reported in Section IV.

Index Terms—Buffer circuits, integrated circuit design.

II. CIRCUIT OPERATION I. INTRODUCTION

I

N this work we develop a CMOS inverter compatible with double gate MOS technologies that can be programmed to different predefined threshold voltages. In the context of this work, the inverter logic threshold voltage ( ) is defined as the static input voltage at which the inverter output is . An input logic threshold programmable CMOS at inverter is of high interest in applications such as CMOS design of input buffers for general purpose circuits (as microcontrollers) to be used in both CMOS and TTL applications. Once the final application or environment of the circuit is known, the input circuitry can be programmed to match the outside signal threshold voltage (TTL or CMOS), thus optimizing the noise margin and the power consumption, as will be shown. A programmable logic threshold inverter is also of interest in analog applications, to be used as a voltage comparator. Instead of using a whole analog block (as an A/D or opamp) to determine if a signal is above or below a given reference, the proposed variable logic threshold inverter can be programmed to a voltage being the reference voltage required for each application. The inverter has the advantage of a significant area reduction given its simplicity and the reduced number of transistors required. Additionally, a comparator requires two inputs, while a programmable logic threshold buffer used as a comparator would only require a single package pin. The design proposed can be divided into two blocks: the programming circuitry and the buffer circuitry. The number of transistors of the buffer determines the different logic threshold levels of the whole inverter. A buffer with transistors ( , N-type transistors, and one P-type MOS), can logic threshold voltages between be programmed to and , and being the threshold voltages Manuscript received September 30, 1997; revised January 19, 1998. This work was supported in part by the Spanish Government under Grant TIC961602-E. J. Segura and J. L. Rosselló are with the Physics Department, Balearic Islands University, 07071 Palma de Mallorca, Spain (e-mail: dfsjsf4@ ps.uib.es). J. Morra and H. Sigg are with the Microcontroller Product Group, Philips Semiconductors, Albuquerque, NM 87113 USA (e-mail: Jim.Morra@ abq.sc.philips.com). Publisher Item Identifier S 0018-9200(98)05530-9.

The logic threshold voltage of a CMOS inverter is given of the N and P transistors. In by the aspect ratio general, both transistors have the same length. Thus, the ratio (the ratio between the transistor widths) is the value that determines the inverter logic threshold voltage. For general applications, inverters are designed to have a curve symmetric static transfer characteristic, i.e., the at . Therefore, intersects the unity-gain line using the Shockley model to describe the behavior of the MOS transistor, and assuming the same value of the gate oxide thickness for both transistors, then the aspect ratio that gives a symmetric transfer characteristic has the well-known expression

(1)

and are the electron and hole mobility, respecwhere and are the transistors threshold voltages. tively, and In those cases where the transfer characteristic is not symmetric, the logic threshold voltage can be expressed as [1]

(2)

where it has been assumed that both transistors have the same ). length (i.e., A. Buffer Design A simplified schematic of a programmable logic threshold voltage inverter (with the programming circuitry not shown) is given in Fig. 1. Its operation is based on the expression stated in (2). The inverter uses a single gate p-MOS enhancement transistor and a pulldown transistors net composed of one single gate n-MOS enhancement transistor and several double gate n-MOS devices connected in parallel. The value of is fixed, while the effective value of can be changed

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using the TLV

that has its vector components defined as if otherwise

Fig. 1. Simplified schematic of a programmable logic threshold inverter. The programming circuitry is not shown.

by programming or unprogramming the double gate n-MOS transistors. The different logic threshold voltages of the programmable , can be derived from (2) obtaining inverter,

(3) is the ratio between the gate oxide where capacitance per unit area for the double and single gate is the width of the th double gate n-MOS transistors, is a Boolean variable associated to the th device, and is double gate transistor programming state. The value of one when such device is unprogrammed and zero otherwise. Each programming configuration of double gate transistors has associated a unique set of Boolean variables that define , as a threshold level vector (TLV), (4) identifies each vector and is the decimal The subindex representation of the TLV, defined as (5) , each one of the If TLV’s will lead to a different value of . ratio (the width of transistors and The in Fig. 1) is used to set the maximum value that can take, i.e., the logic threshold voltage associated to the TLV . Only of the whole remaining voltages can be independently chosen. The remaining levels will be a combination of the independent ones. We use a simple and straightforward technique to determine the size of each double gate transistor: associate each logic threshold level to one of the double gate transistors. This means that the inverter will be programmed to the logic threshold level

for

to

(6)

and single gate transistors Therefore, only both the for the and one of the double gate devices (the transistor TLV ) must be considered to calculate the width of each programmable transistor. From (3) we get

(7) B. General Design The whole programmable inverter, containing both the buffer and the programming circuitry, is shown in Fig. 2. The programming circuitry consists of transistors that connect or isolate the gate of the n-MOS transistors value, and from the input buffer depending on the that drive the gate programming transistors . One register—the Programming Register—holds signal the TLV during the programming mode, and is reset in normal transistors. When , operation to turn off all the drives all the the inverter is in the normal mode, the input n-MOS transistors, and the equivalent active circuitry is the same as that in Fig. 1. Given that no dc current goes into the transistors can be gate of the n-MOS devices, the size of the , the inverter is in the programming minimum. When mode, the inverter input is disconnected from the n-MOS transistors gates, and the double gate transistors are driven by the contents of the Programming Register. In this mode, the inverter input is used to drive the drain of the double gate devices through the p-MOS transistor. During programming, the TLV is held in the Programming Register to drive the ) to the desired devices through programming gate signal ( transistors. The function of bit and the is different from the remaining bits and transistor devices, and are used to turn off the nonprogrammable to prevent current through this device in the transistor programming mode. In applications where more than one inverter is used, the programming register is shared by all the inverters of the circuit, and the input signal In is used to select which inverter is being programmed. C. A Programmable TTL/CMOS Input Inverter A particular case of the general design is a programmable TTL/CMOS input buffer. Such a circuit would be the simpler case of a programmable logic threshold inverter given that only one double gate device is required. The width ratio of the P and N single gate transistors is used to set the logic threshold level of the CMOS buffer configuration, while the width of the double gate transistor adjusts the TTL configuration input logic threshold. Given that the circuit is initially unprogrammed, it is set to the TTL configuration by default. The double gate device must be programmed and turned off to switch to the CMOS configuration. The TLV for an input TTL/CMOS buffer has a single bit, , which is set to program the CMOS configuration

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Fig. 2. Schematic of the programmable logic threshold inverter including the programming circuitry.

Fig. 3. Photograph of the prototype.

and reset for the TTL configuration. In the next section we present the results obtained from a fabricated prototype.

(a)

III. EXPERIMENTAL RESULTS We designed and fabricated a CMOS-TTL programmable input buffer using the Philips 23G 1 double poly single metal stacked gate EPROM process. The circuit was placed on the scribe of a wafer, and the sensitivity of the input buffer logic threshold to process variations was characterized. Only the buffer circuitry was fabricated. The programming circuitry was not included as the devices were accessed separately with probe tips for programming. Measurements were made with an HP4155 Semiconductor Parameter Analyzer. Fig. 3 shows a photograph of the circuit. The prototype was designed to have two programmable logic threshold voltages corresponding to the TTL and the CMOS switching level. The TTL configuraV, while the CMOS tion was designed to have V. configuration was Fig. 4 reports the voltage and current static transfer characteristics of the buffer for both the TTL and CMOS modes. The is 1.35 V, while the experimental value obtained for CMOS configuration logic threshold voltage is 3 V [Fig. 4(a)]. The deviations from the theoretical values are 0.05 V for the TTL configuration and 0.3 V for the CMOS one. These small deviations are due to the use of the Shockley transistor

(b) Fig. 4. (a) Static voltage transfer characteristic and (b) current consumption measured for the programmable inverter for both the CMOS and the TTL configurations.

model in (7) to derive the effective widths of programmable transistors. The use of more accurate models that take into account second order effects of the transistor would correct these small deviations.


INPUT LOGIC THRESHOLD VOLTAGES Circuit TTL CMOS

A 1.35 2.99

AND

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TABLE I DEVIATIONS FOR THE TTL AND CMOS CONFIGURATION OF SEVERAL MEASURED TTL-CMOS BUFFERS

B 1.37 3.02

C 1.39 3.02

D 1.41 3.02

Fig. 4(a) shows that programming the input buffer logic threshold improves the noise margin of each application. Fig. 4(b) reports that the power consumption of the buffer is optimized when the circuit is used in a CMOS environment, obtaining a reduction in the current from 60 A to less V). Therefore, the switching power than 1 A (for consumption will be lowered in a CMOS environment using a programmable inverter because the maximum static current dissipation is reduced from 120 to 20 A. Such a reduction will contribute to lower short-circuit current dissipation, and therefore the overall circuit consumption [2]–[4]. Table I shows the input buffer logic threshold values measured for different circuits. It can be observed that the TTL buffer logic threshold values have a larger variation than the CMOS buffer logic threshold values, but in both cases the variations are small. Maximum speed transient measurements were not possible since we did not include output buffers to drive the large capacitance of the bond pads and measurement equipment [5]. The operation speed of the input buffer can be enhanced by adding normal inverter stages to obtain a tapered buffer. The number of stages and its size depends on the capacitance to be driven as has been extensively studied [6]–[8]. The penalty of the area overhead is small given that the transistors added to each inverter for the size of the programming circuitry can be minimum sized. Additionally, pass only one programming register and one set of transistors are required for all programmable buffers in the die. devices can be distributed The programming register and anywhere in the design which contributes to compact layout. IV. CONCLUSIONS A programmable input logic threshold voltage inverter for double gate transistor technologies is described, along with

E 1.28 3.02

F 1.32 3.05

Max. dev. Mean dev. 8.5% 0.05 11.4% 0.23

Std. dev. 0.046 0.017

its principle of operation and design procedure. A CMOSTTL input buffer has been designed and fabricated showing that it can be programmed to the CMOS and TTL levels depending on the outside environment of the final application. Measurements show good agreement between predicted and obtained logic threshold voltages. Measurements also show a significant enhancement of the noise margins of the circuit. Finally, the input buffer provides the capability of reducing the input circuitry power consumption, especially for CMOS applications. ACKNOWLEDGMENT The authors would like to thank D. Vancil from Phillips USA for his assistance in the buffer design.

REFERENCES [1] J. P. Uyemura, Fundamentals of MOS Digital Integrated Circuits. Reading, MA: Addison-Wesley, 1988. [2] H. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. 19, pp. 468–473, 1984. [3] S. Ma and P. Franzon, “Energy control and accurate delay estimation in the design of CMOS buffers,” IEEE J. Solid-State Circuits, vol. 29, pp. 1150–1153, Sept. 1994. [4] U. Ko and P. T. Balsara, “Short-circuit power driven gate sizing technique for reducing power dissipation,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 3, pp. 450–455, Sept. 1995. [5] C. Yoo, M. K. Kim, and W. Kim, “A static power saving TTL-to-CMOS input buffer,” IEEE J. Solid-State Circuits, vol. 30, pp. 616–620, May 1995. [6] B. S. Cherkauer and E. G. Friedman, “A unified design methodology for CMOS tapered buffers,” IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 3, pp. 99–111, Mar. 1995. [7] C. Prunty and L. Gal, “Optimum tapered buffer,” IEEE J. Solid-State Circuits, vol. 27, pp. 118–119, Jan. 1992. [8] T. Sakurai, “A unified theory for mixed CMOS/BiCMOS buffer optimization,” IEEE J. Solid-State Circuits, vol. 27, pp. 1014–1019, July 1992.

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 4, APRIL 2002

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Charge-Based Analytical Model for the Evaluation of Power Consumption in Submicron CMOS Buffers José Luis Rosselló, Member, IEEE, and Jaume Segura, Member, IEEE

Abstract—The authors present an accurate analytical method for analyzing the power consumption in CMOS buffers. It is derived from the charge transferred through the circuit and makes use of the physically based MM9 MOSFET model (Velghe et al., 1994), (Foty et al., 1997) as well as a modified Sakurai alpha-power law model. The resulting analytical model accounts for the effects of input slew time, device sizes, carrier velocity saturation effects, input-to-output coupling capacitance, output load, and temperature. Results are compared to HSPICE simulations (level 50) and to other models previously published considering a large set of parameters for a 0.18 and 0.35 m technologies, showing significant improvements. Index Terms—Closed form expressions, deep submicron, power modeling and estimation.

NOMENCLATURE A)

Input Parameters to the Model zero bias low field mobility; gate field mobility reduction coefficient (MM9 parameter); nMOS, pMOS gate field mobility reduction coefficient (MM9 parameter); drain field mobility reduction coefficient (MM9 parameter); nMOS, pMOS drain field mobility reduction coefficient (MM9 parameter); buffer output load; gate oxide capacitance; frequency; substrate sensitivity when depleting bulk doping (MM9 parameter); substrate sensitivity when depleting surface doping (MM9 parameter); channel length; channel length of nMOS; channel length of pMOS; gate source/drain underdiffusion (MM9 parameter); nMOS, pMOS gate source/drain underdiffusion (MM9 parameter);

Manuscript received July 20, 2000; revised August 3, 2001 and December 15, 2001. This work was supported by the Spanish Comisión Interministerial de Ciencia y Tecnología under Project CICYT-TIC98-0284. This paper was recommended by Associate Editor K. Mayaram. The authors are with the Physics Department, Balearic Islands University, 07071 Palma de Mallorca, Balears, Spain (e-mail: [email protected]; [email protected]). Publisher Item Identifier S 0278-0070(02)02473-9.

B)

process bias on the channel length (MM9 parameter); normalization constant; surface potential for strong inversion (MM9 parameter); transition time of input voltage; voltage of transition between and (MM9 parameter); physical threshold voltage with no substrate or drain bias (MM9 parameter); nMOS, pMOS physical threshold voltage with no substrate or drain bias (MM9 parameter); channel width; nMOS, pMOS Channel width; isolation reduction of channel width (MM9 parameter); process bias on the channel width (MM9 parameter); Intermediate Parameters velocity saturation index; nMOS, pMOS velocity saturation index; MOSFET conductivity; nMOS, pMOS conductivity; body effect coefficient; nMOS body effect coefficient; overvoltage; maximum overvoltage; overvoltage at ; charge stored at the output node flowing through the nMOS transistor when the output is discharged; output voltage swing; effective carriers mobility; interconnect resistance per square; area capacitance; fringing capacitance to underlying conductor for single line; input to output coupling capacitance; input to output coupling capacitance value when the input voltage is high, low; minimum output capacitance allowed by the technology; total output capacitance when the input voltage is low; short-circuit energy; short-circuit energy dissipated in a falling, rising input transition; transient energy;

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transient energy dissipated in a falling, rising input transition; nMOS, pMOS drain current; drain current at ; drain current at and ; nMOS, pMOS drain current at ; saturated drain current; nMOS, pMOS saturated drain current; drain current; maximum short-circuit current; maximum short-circuit current for heavily loaded buffers; maximum short-circuit current for unloaded buffers; short-circuit current; effective channel length; minimum lithographic channel length allowed by the technology; effective channel length of pMOS; total power consumption; charge stored at and ; overshoot charge transferred (OCT); overshoot charge transferred for a fast input tran); sition ( overshoot charge transferred for a slow input ); transition ( overshoot charge fraction transferred during the ; interval overshoot charge fraction transferred during the ; interval short-circuit charge transferred when ; short-circuit charge transferred for a rising input transition; effective resistance of nMOS; short-circuit current time interval when ; short-circuit current time interval; time; time at which the short-circuit current is maximum; time at which the short-circuit current is maximum for unloaded buffers; time at which the short-circuit current is maximum for heavily loaded buffers; mathematical limit of when ; time at which the nMOS transistor starts to conduct; overshoot time; time at which the overshoot current is maximum; time during which the pMOS device passes a negative current; saturation voltage at ; saturation voltage of pMOS at ; saturation voltage; saturation voltage of pMOS; supply voltage; drain voltage;

smoothing function used by MM9 between limand ; iting values gate voltage; input voltage; output voltage; short-circuit input voltage swing for ; threshold voltage used by the alpha-power law MOSFET model; nMOS, pMOS alpha-power law threshold voltage; effective channel width; minimum lithographic channel width allowed by the technology; nMOS, pMOS effective channel width. I. INTRODUCTION

P

OWER dissipation emerged as an important concern in circuit design during the last decade due to heating problems in high-density/high-performance circuits and to power savings required for portable applications. A growing fraction of the power consumed by very large scale integration (VLSI) circuits is due to the clock distribution network, signal repeaters, I/O drivers, and busses all based on inverters. Moreover, the analytical description of the power dissipated in a CMOS inverter is the most important step in the description of more complex gates [3]. It is well known that power dissipation in CMOS circuits has a dynamic and a static component. The dynamic dissipation is due to the charge/discharge of the gate output load and to the short-circuit current due to the direct supply-ground conducting path created during the transition [4]–[6]. Many high-level approaches consider only the first contribution to compute power in large circuits [7], [8], given the complexity and computing cost of considering the short-circuit component. The static dissipation is mainly due to current leakage from transistors in the off state, although reverse biased diodes from the device diffusions and well regions also contribute to this current. The off-state current, referred to as subthreshold leakage, is becoming more important with technology scaling since the device threshold voltage ( ) is reduced to maintain circuit performance. This term is usually neglected since ( being the Boltzmann constant, the temperature in Kelvin, and the electron charge) [9]. Several works model the short-circuit power consumption. Veendrick [4] obtained an expression for unloaded buffers although the short-circuit component has a strong dependence on the output capacitance. Hedenstierna et al. [5] calculated the short circuit current using the Shockley MOSFET model for loaded buffers. This model cannot be applied to short-channel devices since they exhibit a linear dependence of saturation current versus the gate voltage, rather than the traditional square-law model used for long-channel devices [6]. Sakurai et al. [6] derived a model for long and short channel devices using their -power law MOSFET model for unloaded buffers. This model, as the model in [4], is useful to estimate the short-circuit component upper bound but cannot be used for a detailed power dissipation description since the output load effect must be included. Turgis et al. [10] derived an expression

ROSSELLÓ AND SEGURA: CHARGE-BASED ANALYTICAL MODEL FOR EVALUATION OF POWER CONSUMPTION

for the short-circuit dissipation assuming that carriers were always moving at the saturation velocity and took into account overshooting effects. This model is valid only for deep submicron technologies and introduces the concept of equivalent capacitance, thus allowing a direct and frequency-independent comparison of the various power components. Hamoui et al. [11] obtained an expression for the short-circuit power dissipation using a modified version of the th power law MOSFET model in [12]. This approach requires numerical computing in a three-step process to determine the time when the short-circuiting transistor changes its mode of operation. Nikolaidis et al. [13] obtained an expression of the short-circuit dissipation for buffers driving long interconnect lines using the -model of an RC load and the -power law model for submicron devices. They took into account the input–output capacitance effects while the short-circuit current contribution was neglected when computing the output waveform. Recently, Nose et al. [14] derived a closed-form expression for the short-circuit power dissipation of CMOS gates taking into account short-channel effects, but not overshooting effects of increasing importance in submicron CMOS circuits. The work concluded that the ) will not short-circuit power to total power ratio ( is kept constant. change with scaling if the ratio In this work, we propose and evaluate a model to compute accurately the power consumption of CMOS buffers accounting for the main effects in submicron technologies as the input–output coupling capacitance and carriers velocity saturation effects avoiding time-consuming numerical procedures. The energy is computed from a detailed description of the various charge transference mechanisms involved during transitions. The final expression is the sum of the power dissipated when charging/discharging the output capacitance plus the short-circuit component that is accurately computed describing the impact of overshooting effects. The modeling process is described in detail providing a deep insight into the energy mechanisms involved as well as their interrelationship. The model is compared to HSPICE simulations (level 50) and to other models previously published considering a large set of parameters for a 0.35- and 0.18- m technology, showing significant improvements over previous works. The paper is organized as follows: in Section II we describe the energy components and the method used to derive each contribution. Section III presents the MOSFET models used, while Sections IV and V derive the short-circuit and transient energy components, respectively. Section VI presents the results and Section VII concludes the work. II. ENERGY COMPONENTS We derive the energy consumption of a CMOS buffer (Fig. 1) describing the charge transfer mechanisms in the circuit when an input ramp is applied. The dynamic behavior of the circuit in Fig. 1 is described by (1) is the output load that includes the gate capacitances where driven by the buffer, the interconnect wiring capacitance, and is the input–output the diffusion capacitances of the buffer.

Fig. 1.

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CMOS buffer model used to compute the energy dissipation.

capacitance, the output voltage, and the pMOS the input and nMOS transistors current, respectively, and voltage. Fig. 2 illustrates the time evolution of the output voltage and the current through the nMOS and pMOS devices when a rising input voltage is applied. The input voltage is described with a linear ramp as (2) . From Fig. 2 it follows that (the short-circuit current time interval . when overshooting is neglected) and We compute separately the short-circuit energy dissipation component ( ) and the energy associated with the output node discharge ( ). The short-circuit energy is obtained from the short-circuit charge, while the expression of the transient energy is derived computing the charge that flows from the output node and ) to ground. We use (i.e., the charge stored at and for the short-circuit and transient energy components, respectively, for a rising input, while and refer to these energies for a fall input transition. The power dissipation in one period is computed as

where

(3) is the frequency of the input signal. where The current through the pMOS transistor ( in Fig. 2) has two components clearly distinguished by its sign. The negative pMOS current is due to a partial discharge of the output capacitance from the output node to the supply rail. This effect appears when the input–output capacitance drives the output voltage be) at the beginning of the transition yond the supply value ( [15]. When the nMOS device starts to conduct, it pulls the output voltage down. This effect is known as overshooting, and the time during which the output voltage is beyond the supply value . Once the output voltage goes is called the overshoot time , the pMOS current is positive corresponding to the below short-circuit component due to the simultaneous conduction of both devices. From this picture it is clear that the overshoot and short-circuit current components are related and their relative contribution is determined by the input transition time. If the input voltage is (the input voltage value at which the pMOS below

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Fig. 2. Output voltage and current evolution in the nMOS and pMOS transistors for a rising input linear voltage.

turns off; is the pMOS threshold voltage) at , then there will be a short-circuit current period from this time until the pMOS is turned off. This case will be referred to as a slow input transition. In the case of a fast input transition the output when the input reaches . voltage is still beyond ( being the time at which the nMOS In this case, is the short-circuit current transistor starts to conduct and time interval when there is no overshooting; see Fig. 2) and there is no short-circuit period. For a fixed input transition time, the greater the overshoot time (i.e., the greater the input-output coupling capacitance), the shorter is the duration of the short-circuit current contribution. The overshoot time depends on the relationship between the input–output capacitance (that drives ) and the driving strength of the the output voltage beyond nMOS transistor (that pulls this output voltage down), while the short-circuit period termination is determined uniquely by the input transition time. This effect is illustrated in Fig. 3, obtained from simulation, showing a set of pMOS current curves for a fixed input rise time and different coupling capacitance values. The short-circuit current contribution tail end is independent of the time at which short-circuit starts (since it is determined by ), while its negthe time at which the input voltage is ative slope does not vary significantly in all cases because the pMOS transistor is saturated. Note that overshooting does not only impact short-circuit duration, but also decreases its maximum value. We included the overshooting effects on the short-circuit expression through the overshoot time using a geometrical approach following the behavior reflected in Fig. 3. This process is detailed in Section IV. The short-circuit energy ( ) will be computed from the pMOS current since this component can be clearly identified. The energy associated with the overshoot charge transferred will be neglected since this energy is proportional not only to the small amount of charge involved, but also on the voltage difference through which it flows, which is also very small when compared to the supply voltage. The transient energy ( ) corresponds to the energy dissipated when discharging the output capacitance. The energy of a

Fig. 3. pMOS current shape variation for a fixed input rise time and different values of the input–output coupling capacitor.

discharging constant capacitance is simply , where is the voltage swing and the charge initially stored in the capacitance and discharged through the nMOS transistor (defined as dynamic charge). The voltage swing of the output node in the but a higher one, say buffer circuit is not the supply voltage , due to overshooting. The dynamic charge will be derived using charge conservation by computing the charge at the beginning of the transition minus the charge at its end. It is important to remark that the overshoot charge (that is the charge transferred from the output node to the supply rail) must be subtracted from this term since it flows through a voltage difference and not through as occurs for the charge flowing from the output node to ground. Therefore, although the overshoot charge is small and its overall energy contribution can be neglected, this charge must be subtracted from the charge variation at the output node since only the dynamic charge is multi) when computing plied by a large voltage difference ( the transient energy. The output node charge is stored in both the input–output caand the load capacitance . Since the transient pacitance energy is derived from the computation of the charge at the beginning and the end of the transition, we require an expression of the input–output capacitance (which is strongly dependent on the input–output voltage) only for these two static operating in the static input low state ( ) conditions. The value of considering the side-wall capacitance of both transistor drains and the gate to drain overlap capacitance of the pMOS transistor in the linear region is given by (4) and being the gate source/drain underdiffusion with and for the pMOS and nMOS transistors, respectively. are the nMOS and pMOS effective channel width, while is the effective channel length of the pMOS transistor. The effective channel length and width are [2]

(5)


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where and are the process bias on the channel is the isolation rewidth and length, respectively, while duction of channel width. For a static input high the capacitance can be obtained similarly. III. MOSFET MODEL USED Equation (1) cannot be solved in a closed form even when the simple Shockley MOSFET model is considered. Moreover, since carrier saturation effects become important with technology scaling, more advanced MOSFET models accounting for such effects must be considered. The alpha-power law MOSFET model [16] is a simple shortchannel MOSFET model expressed as

(6)

with (7) The saturation voltage

Fig. 4. Comparison of the saturation voltage provided by MM9 with the linear description of (8) (with n = 1) for a 0.35-m technology.

the carriers mobility, while and are the effective and channel width and length, respectively. The parameters are the gate field and drain bias mobility reduction coefficients and is given by

is given by [16] (8)

instead of the traditional dependence We took of the saturation voltage [6] to simplify Sakurai’s equations in the linear region. A comparison of (8) with the physically based saturation voltage for an nMOS transistor with dimenm and m is plotted in Fig. 4. sions The parameter is the velocity saturation index that takes a value between two (long-channel devices) and one (shortand are the drain curchannel). The two parameters , while rent and the saturation voltage for and are fitting parameters [6]. parameters and can be computed using any physically based MOSFET model. We used the MOSFET model 9 (MM9) to compute these parameters (see [1] and [2] for a detailed description of the MM9 structure). The MM9 is a short-channel model that is being included in many widely used general-purpose circuit simulators and thus is drawing a significant amount of attention. A relatively small number of model equations and parameters are used when compared with many other models [2]. MM9 basic equation is (9) is a smoothing function being equal to the drain where to source voltage when the transistor is in the linear region is the and to the saturation voltage when it is saturated. is the threshold voltage. gate to source voltage and with being the gate oxide capacitance,

(10) is the substrate sensitivity when depleting surface where is the substrate sensitivity when depleting bulk doping and is a voltage of transition between and doping. . is the surface potential for strong inversion while and are MM9 constants from [1] and [2]. A detailed description of parameter extraction for this model from the device I-V current characteristics can be found in [17]. in (7) is computed using (9) while in The value of (8) is obtained from [2] (11)

Alpha-power law model equations are mathematically simpler than physically based MOSFET models like MM9 with the disadvantage that the relationship between the empirical paramand the foundry supplied process parameters is not eters , developed directly. We use the following relationship [18] to relate to physical parameters: (12) The expression for

in the MOSFET Model 9 is [2]: (13)

To obtain a better fitting of the transistor characteristics we by adjusting this threshold voltage to fit derive a value of . We obtain this the drain saturation current at

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current value (denoted as ) from (9) and equate it to the predicted value of the alpha-power law

The short-circuit charge transferred (SCCT) is the integral of from the time at which the nMOS is turned on, , up to the (see Fig. 2) time at which the pMOS turns off,

(14) (18) with

given by (12). We use (14) to get value leading to

from the predicted

That leads to the following: (19)

(15)

, , , and The parameters can be obtained using any physically based MOSFET and model since . analytically to Equations (12) and (15) relate and physical parameters without the need for time-consuming numerical computations. IV. SHORT-CIRCUIT COMPONENT We derive the short-circuit charge in a first step, neglecting overshooting effects which are included in a second step through the overshoot time. ), the short-circuit In the case of unloaded buffers ( current is equal to the nMOS saturation current for the interval and to the pMOS saturation current when , where is the time at which the short-circuit current is maximum. Therefore, using the alpha-power law MOSFET model, the short-circuit current for an unloaded buffer is

(16) This current dependence is taken as a reference to obtain an expression for the short-circuit current for loaded buffers using ) and the time at which the values of the maximum current ( ) derived in Appendix A. and have it occurs ( been derived considering the limit of unloaded buffers (i.e., paand ) and heavily loaded buffers (rerameters , ). ferred to as As an analogy to (16), the short-circuit current is shown in (17) at the bottom of the page.

The value of is selected to set the value of (19) equal to the . This parameter is required to adjust HSPICE simulation of the charge and accounts for deviations mainly due to differences (from the -power model) and the physical , between as well as other second-order effects not considered similar to channel length modulation. This value has been found to be close to 1.5 and 1.7 for 0.35and 0.18- m technologies, respectively, for a large range of parameters values, including variation of the channel length (and therefore ), the buffer symmetry (which has a strong effect on the short-circuit current shape), input rise/fall time, output capacitance, input–output capacitance, etc. The value of is the same for rising or falling input transitions and must be adjusted only once for the technology since its value remains constant for all the parameters considered in the model. Fig. 5 compares (17) to HSPICE simulations for various to 50 ). When values of the output capacitance (from is small, the maximum current time is close to while HSPICE results are close to the current shape predicted by (16). As the output capacitance increases, the time at which the short-circuit current is maximum also increases and is close for large values of . The areas under the curves to described by (17) and HSPICE simulations (i.e., the charge) are nearly the same. Overshooting effects are included through the overshoot time . Simulations in Fig. 3 showed that overshooting displaces the short-circuit current to the right, maintaining the current slopes invariant. This can be described analytically using a geometrical approach as shown in Fig. 6. The short-circuit current curve displacement is approximated with straight lines of conis the area of the triangle , while the restant slope. ) is the area within the duced SCCT due to overshooting ( . With this geometrical analogy, is derived triangle using as from (20) given by (19). Equation (20) is an approximation obwith tained assuming that the short-circuit current is linear with time

(17)


Fig. 5. Short-circuit current versus C for a 0.35-m technology. The maximum short-circuit current and the time at which such a maximum takes place are fitted by the model proposed.

and it does not vanish for is lation for any

Fig. 6.

Geometrical derivation of Q

439

from Q

using t .

. A more accurate re-

(21) The mean deviation of (21) with respect to (20) is less than and provides negligible values for . 10% of We plot a comparison of (21) to HSPICE in Fig. 7 showing for different values of , with good accuSCCT versus is given in Appendix B. racy. The mathematical derivation of Finally, the energy associated with SCCT for a rising input is computed as (22) Fig. 7. Short-circuit charge transfer versus coupling capacitor for various values of C in a 0.35-m technology.

V. TRANSIENT DISSIPATION The transient energy is dissipated when the output node is discharged. Conceptually this contribution can be subtracted from the short-circuit energy given that only the short-circuit charge flows through the short-circuiting transistor (that is the pMOS (nMOS) transistor for a low to high (high to low) input transition). In the buffer model of Fig. 1 the charge at the output node is stored in both the output and coupling capacitances, leading . to As discussed in Section II, overshooting has two main effects: first, it raises the voltage from which the output is discharged (say ), and second, part of the charge beyond through initially stored at the output node is transferred to the pMOS (this charge was referred to as the overshoot charge ). The overshoot charge does not contribute to the transient energy in the same way as the charge that goes to ground since the overshoot charge flows through a smaller voltage drop (see Fig. 2). Therefore, the energy expression associated with the discharge of the output node must contain only a fraction of the charge initially stored in the output capacitances. The energy dissipated by the nMOS transistor for a high-to-low output tran(energy dissipated for sition is given by

a constant discharging capacitance). is the charge transferred from the output node to ground through the nMOS tranis the voltage swing given by . sistor and Thus, the discharging energy is expressed as (23) is the charge at the output node at time (when where is the charge the nMOS transistor starts to conduct), stored at the output node when the output transition is finished, is the overshoot charge transferred from the output and node capacitances through the pMOS transistor (and therefore not dissipated in the nMOS transistor) during time that both ). The output voltage swing transistors are conducting ( is We write considering at the output node is equal to the that the charge for charge at that node at the beginning of the input transition ) minus the charge that has ( through the pMOS been transferred from the output to transistor until the nMOS transistor starts to conduct (defined

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as ). Since charge transferred is

and the total overshoot , (23) takes the form

with (30)

(24) If the parasitic input–output capacitance is neglected ( ), the overshooting and overvoltage vanish ( and ) and the well-known expression for the transient energy is obtained as (25) To compute the transient energy in (24) we derive an expresand the overvoltage . sion for the overshoot charge A. Overshoot Charge Transfer The overshoot charge transfer differs for fast and slow input transitions since in the first case the pMOS transistor is off when overshooting ceases and in the second case this device is still conducting. We compute the overshoot charge for the slow and and , respectively) and then comfast input transitions ( bine both equations in a unified expression. , i.e., the 1) Slow Input: In this case has not reached at . The input is given charge stored at the output node at time , while at the by beginning of the transition the charge stored at the output . The difference node is is the overshoot charge plus the charge . Therefore, the that passed through the nMOS until overshoot charge expression is

where the parameter defines the transition between the two regions. 2) Fast Input: For a high-speed transition the pMOS is off (i.e., ) and the overshoot charge is before calculated from the current passed through the pMOS. We use (9) neglecting the velocity saturation effect of the gate voltage ) with neither of the quadratic or higher order terms ( (the drain voltage of the pMOS during overshooting is of small) leading to (31) Given that

(32) is computed from (1) At the beginning of the transition ), neglecting the nMOS and the pMOS current ( which are negligible with respect to the current injected through that is proportional to which is large for fast inputs). So in this case (1) simplifies to (33) from (33), the pMOS drain voltage takes the form , thus (32) leads to

(26) is close to , therefore the For a slow input transition is still valid and the integral over the approximation nMOS transistor current can be neglected. The term into the parenthesis of (26) corresponds to the input voltage swing that determines the amount of charge flowing through the pMOS transistor during overshooting and cannot go since for these values the pMOS is off. The beyond can go beyond leading to an overestimation in time the input voltage swing. Therefore, we correct the expression of in (26) with a time . (27) must be equal to the overshoot time for Knowing that for large ones, we use small values and that saturates to the following expression: (28) is a function that saturates to where and is equal to when

when , defined as (29)

, we obtain

(34) and : Equations 3) Combining Expressions for (27) and (34) are unified into a single analytical expression for high-speed for the overshoot charge that is equal to for slow inputs transitions and to (35) Fig. 8 shows the charge transferred through the pMOS tranfor sistor for a high-to-low output transition as a function of different nMOS channel widths. Squares are HSPICE simulations while solid lines correspond to the charge model developed ). The charge transferred for high-speed transitions is ( mostly due to overshooting (a total negative charge is obtained) while for slow-input transitions the short-circuit component is dominant (overall positive charge). The curves in Fig. 8 show a good fit to (35) and (21) to describe the charge through the pMOS. B. Overvoltage Evaluation computing the We obtain the maximum overvoltage . We adjust this expression to meet the output voltage at limit of an ideal step input using charge conservation.


Fig. 8. pMOS charge transference versus input rise time for three different channel widths for a 0.35-m technology (Symbols: HSPICE simulations, solid lines: Model proposed).

The derivation of

441

Fig. 9. Maximum overvoltage versus input rise time for various values of C for 0.35-m technology.

requires solving (36)

where Equation (36) is derived from (1) and is valid for is neglected since the nMOS is off. To get an analytical so, we take the pMOS curlution of (36) and compute rent expression with the approximations of small drain voltage and neglect gate saturation effects (31). We also take an average as leading to value of (37) We solve (36) using (37) and compute the overvoltage when the nMOS transistor starts to conduct ( ) obtaining (38) Equation (38) provides a partial description of the maximum output voltage. For an ideal step input, the maximum overvoltage is obtained from charge conservation as (39) . The maxThis result is not provided by (38) when imum overvoltage is also determined by the discharging nMOS current and the capacitance being discharged ( ). To account for these effects we define an effective resistance for the nMOS and incorporate an additional transistor as term to (38) to estimate the maximum overvoltage beyond (40) Equation (40) is an empirical expression that provides an excellent agreement with HSPICE simulations as shown in Fig. 9. The plot presents the overvoltage versus the input rise time for (from to 50 ). different values of

Fig. 10. Power dissipation versus input-to-output transition time ratio for 0.18-m technology. Three different capacitance values (C , 3C , and 5C ) driven by three different buffers (I , 3I , and 5I ) are considered.

VI. RESULTS We compare the model predictions versus HSPICE simulations for 0.35- and 0.18- m technologies considering energy versus input transition time, output capacitance, channel length, supply voltage, temperature, and the pMOS to nMOS channel width ratio. For each plot we include results from the models in [10], [11], or [14], depending on which best fits the energy consumption for the parameter considered. Fig. 10 plots the energy dissipated per cycle versus the input-to-output time ratio for the 0.18- m technology. The output time is taken from HSPICE simulations as an average value of the rise and fall times at the buffer output ), where and are proportional to the time ( at the output ( ) to 0.1 at the output ( ) from 0.9 ). Three different design scenarios (i.e., are considered: a minimum inverter driving a minimum sized m m ) inverter ( and 5 ) with output capaciand two scaled inverters (3 and 5 , respectively. The input time ranges tances of 3 from 20 ps to 1 ns (0.5 to 3.5 in the plot) covering both fast

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Fig. 11. Power dissipation versus input time to output time ratio for three different inverter sizes in 0.18-m technology. Different W =W ratios are considered.

Fig. 12. Power dissipation versus output capacitance for three different input rise times for 0.18-m process technology with W = 1 m and W = 2 m. The model is compared to HSPICE simulations and a recently published model [14].

and slow input transitions. Simulation results show that both models (the model proposed and the model in [10]) provide a good description of the energy for the whole design space considered. Fig. 11 plots the power dissipation versus the input-to-output and time ratio for five inverters, three with ratios m m m m and m m and two with and ratios m m and m m for 0.18- m technology. The input times range from 20 ps to 1 ns. The model presented reports better fitting with respect to previous works (we include results only from [14] as the model better describing the energy for this parameter) maintaining an accurate description of power . for different values of Fig. 12 shows the power dissipation dependence with the ps, output capacitance for three input rise time values ( ns, and ns) for a 0.18- m technology CMOS m m. The model proposed and inverter with the model in [14] are compared to HSPICE simulations showing similar accuracies, thus verifying the accuracy of the proposed model to describe the short-circuit and transient components.

Fig. 13.

Energy dissipation versus input-to-output time ratio for different ratios for 0.35-m technology. When t =t > 1 the short-circuit component is dominant while for t =t < 1 the overvoltage contribution increases the total power.

W =W

Fig. 14. Energy dissipation versus channel length for 0.35-m technology. This graph shows the behavior of the proposed model when varying the velocity saturation index () and the coupling capacitance.

Fig. 13 plots the energy dissipated per one cycle period versus the input-to-output time ratio for 0.35- m technology. Four different inverters are considered with different values ratio and two values of the output capacitance of the (all the values specified in the graph). The input time ranges from 20 ps to 1.5 ns. Results show that the model presented describes correctly HSPICE simulations under all the parameter combinations considered representing an improvement over previous models. Fig. 14 compares the energy versus channel length with and a minimum channel HSPICE for different values of m). This graph shows good accuracy of the width ( model proposed for different velocity saturation index values ( ) since this parameter is strongly dependent on the channel length. As the device length decreases, the conductance of the transistors is reduced leading to lower values of SCCT; this is ns. The power contribution due to the the case for coupling capacitance increases with channel length for shorter input transitions.


Fig. 15. Energy dissipated versus power supply for 0.35-m technology. The model developed provides a good description for the entire range considered.

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Fig. 17. Energy versus temperature for three supply voltages for 0.35-m technology.

Fig. 18. Energy versus pMOS width with W = 3 m and C = 10C for 0.18-m technology. This graph shows the behavior of the model when nonsymmetrical buffers are considered in the deep-submicron regime. Fig. 16. Energy dissipated versus power supply for 0.18-m technology. The model proposed describes the entire range considered.

The energy variation with the power supply voltage is shown m, m, in Fig. 15 for a CMOS buffer with and different input rise an output capacitance of times (from 50 ps to 1 ns). HSPICE simulations are compared to the proposed model and the model in [11]. Energy models require good accuracy with supply voltage since it is one of the key parameters used to control power consumption. Simulations show that the model proposed represents a contribution in describing this dependence. The energy versus power supply for 0.18- m technology is shown in Fig. 16 for a CMOS buffer with m m, , and ps, 500 ps, and 1 ns. The model proposed provides a good description in all the range considered. Fig. 17 plots the energy versus temperature for three different supply voltages. The MOSFET Model 9 temperature dependence [2] is included in the basic parameter set. The model accuracy is maintained over the whole period considered ( 50 to 150C) showing that the low voltage regime is less sensitive to temperature variation. Fig. 18 plots the energy in one cycle

versus the pMOS channel width for a fixed value of the nMOS channel width for 0.18- m technology. Different values of the are considered (from 50 ps to 1 ns). Fig. 18 reinput times flects the accuracy of the model to describe the time at which the maximum short-circuit current takes place as the maximum dc current location is dependent on the buffer symmetry. Fig. 19 shows the energy dissipated by a CMOS buffer driving a long interconnect line. We considered a 1- m width level model [20] for 0.35- m tech2 metal simulated using a nology. For this technology the metal 2 to well capacitance per m its fringing caunit of area is m, and its square resistance is pacitance is m sq. The total output capacitance (used in the , where model) was computed as is the output capacitance of the buffer, is the parais the input capacitance sitic interconnect capacitance, and of the driven gate. We compared HSPICE simulations (squares) to the model developed and a specific model for long interconnect lines [13] for two different input times of 50 ps and 1 ns. The model derived in this work reports good fitting for interconnect lines lengths below 5 mm, leading to energy underestimation for higher wire lengths. This underestimation is

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TABLE I AVERAGE ERROR OF ENERGY ESTIMATION VERSUS HSPICE FOR 0.18- AND 0.35-m TECHNOLOGY

TABLE II PERCENTAGE OF ENERGY DUE TO COUPLING CAPACITANCE EFFECTS ( E ) AND TO SHORT-CIRCUIT CURRENTS ( E ) WITH RESPECT TO THE TOTAL POWER

%

Fig. 19. line.

%

Power consumption for a CMOS buffer driving a long interconnect

due to the increase of the line resistance with its length. When the line resistance becomes comparable to the buffer output resistance, part of the output capacitance is shielded from the buffer, thus decreasing the gate delay and increasing the short-circuit dissipation [21], [22]. We compare this result with the model developed by Nikolaidis et al. [13] (dashed line in Fig. 19). That model provides an accurate description for the delay of an inverter driving an RC line but uses a fixed value for the time at which maximum short-circuit takes place (set ). Therefore, the dependence of this time as with the output capacitance increase (Fig. 5) is not described, leading to a underestimation of the energy dissipated as shown in Fig. 19. We calculated the mean deviation of the Energy versus input time, channel length, supply voltage, output capacitance, and pMOS channel width from HSPICE simulations for the models in [10], [11], and [14] and the model proposed for the 0.18- and 0.35- m technologies considered. The percentage deviations are reported in Table I showing the improvement achieved by the model proposed with an overall accuracy within 5% of HSPICE simulations, thus representing an improvement over previous works. The model in [10] provides the better agreement with HSPICE simulations for the 0.18- m technology rather than the 0.35- m technology since it was developed for deep-submicron technologies. Table II reports the percentage of energy due to coupling ca) and short-circuit currents ( ) with pacitance effects ( is kept constant respect to the total power. The ratio for the two technologies considered and the input time is se). The percentage lected to be equal to the output time ( of the short-circuit power is nearly the same for the two technologies (as predicted in [14]) while the influence of the coupling capacitance on the total power increases for the 0.18- m technology. Finally, we computed the power dissipation for 10 transitions with HSPICE and the analytical models on a Pentium III processor-based computer. Simulation times are reported in Table III showing that the models in [5], [6], [10], [14], and the proposed model are up to three orders of magnitude faster than HSPICE, while the models in [11] and [13] are two orders of magnitude faster than the simulator. The numerical approaches

TABLE III COMPUTATION TIME FOR 10 TRANSITIONS

used in [11] to obtain the time at which the maximum short-circuit current takes place (using the bisection method) and the complex equations in [13] to model the RC line at the output of the buffer increase computation considerably. VII. CONCLUSION We have developed an analytical expression for the energy dissipation in CMOS buffers by solving the dynamics of the circuit and considering a physically based -power law MOSFET model. The various energy components are discussed and modeled in detail highlighting the parameters involved and their interrelationship. Several nonlinear problems are solved with simple and accurate formulas to avoid time-consuming numerical procedures. Exhaustive comparisons to HSPICE results are provided to demonstrate the validity and accuracy of the model for both submicron (0.35 m) and deep-submicron (0.18 m) technologies. This model is expected to remain valid for scaled technologies as long as the subthreshold leakage component does not dominate active power, since the main submicron effects are accounted at the device level. It represents an improvement over previous models since results show an overall high accuracy in describing the energy for all the parameters considered (Figs. 10–19), while previous models maintain accuracy only for some parameters or technologies. The model proposed has an average error within 5% of HSPICE simulations for a wide range of parameter variation.


445

The model presented underestimates energy when the resistance of the line driven by the buffer is comparable to the effective resistance of the transistors in the buffer. Additional efforts are required to account for these resistive effects [22]. APPENDIX A COMPUTATION OF THE MAXIMUM SHORT-CIRCUIT CURRENT Maximum Current for Unloaded Buffers When the output capacitance is small (i.e., when the shortcircuit current has a greater impact [4]) the circuit behavior is . close to the inverter dc operation in the sense that At the beginning of the transition, the pMOS transistor drives a current equal to the nMOS saturation current, while at the end of the transition the pMOS is saturated. In this particular case, the . Using (7) and maximum current takes place when for the nMOS and (2) and using for the pMOS, leads to (A1) is the time at which the short-circuit current is where is maximum for unloaded buffers and

Fig. 20. HSPICE and (A3) comparison for 0.35-m technology of the time at which the short-circuit current is maximum for lightly loaded buffers. Different inverters with different W =W ratios are considered.

taken as while the input voltage is described with a linear ramp [see (2)]. Under these assumptions and neglecting overshooting effects (that will be included later), (1) becomes (A6)

(A2) We found a good approximation to the solution of (A1) for (which is the range for these parameters) as

given by (7) and with using (7) and (2) obtaining

. We solve (A6)

(A7) (A3) where (A8)

where

(A4)

Equation (A7) is used for the linear expression of the pMOS ) in the alpha-power law MOSFET model current ( (6) with

Equation (A3) leads to the exact solution of (A1) when , or , or , . Equation (A3) also . A comgives an accurate description for the case parison of (A3) to HSPICE simulations is shown in Fig. 20 for ) ratio for various buffers with different values of the ( 0.35- m technology. Once the maximum time is obtained we derive the maximum short-circuit current for unloaded buffers from (7), using (2) and (A3) as

(A9)

(A5)

that are obtained from (A7), (2), and (8), respectively, leading to

Computation of the Maximum Current for Heavily Loaded Buffers values. In this case, Equation (A3) is inaccurate for large the current through the pMOS transistor can be neglected and

(A10)

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with

(A11) The time at which the maximum current takes place for is obtained solving heavily loaded buffers (A12) where

and

take the form

(A13)

Fig. 21. HSPICE simulations of t and t in 0.18- and 0.35-m process technologies for a minimum-sized inverter driving another minimum-sized inverter. Different input rise times are considered.

Now we obtain the maximum short-circuit current for heavily given by (A13). loaded buffers computing (6) at We take into account only the linear dependence of on to simplify the expression. This approach is justified since the drain voltage swing during the input transition is not large for heavily loaded buffers. The result is

(A14)

Combining Both Expressions and , respecEquations (A12) and (A14) diverge to . We construct an expression for the maximum tively, for and time that leads to short-circuit current and for large values of and to and for . function must be a constant for small output loads The is load independent) while for large loads it must (since , i.e., a function of the show the same dependence as form (A15) where is load-independent. An asymptotic function that follows the required limits is

Fig. 22. Overshoot time variation with input rise time for various values of the output capacitor. The parameter t is nearly independent of C as predicted by (B5).

The function for the time at which the short-circuit is maximum must lead to (A12) for heavily loaded buffers and to (A3) for unloaded buffers. Equation (A12) is a function of the form (where both and are load-in(independent). We define the linear transformations and and version and translation) as and the linear transformation (a translation followed by an inversion). With this transformation we obtain a function similar to (A15) from

(A16) (A18) is the constant value of where fore, the equivalent expression for is

for in terms of

Thereand

(A17)

is applied to (A3). We define The same transformation and and then obbetween in (A18) and tain a smoothing function using (A16). Then we transform with the inverse of


447

(B4)

transformation function between

( and

) to obtain a smoothing

Since , we then have (B4), shown at the top of the page. The solution of (B4) is

(A19)

(B5)

as

with , and Given that for the maximum current time, (A19) leads to

(B6) (A20)

APPENDIX B OVERSHOOT TIME COMPUTATION

with HSPICE for different Fig. 22 is a comparison of . It is shown that this time is almost independent values of of the load capacitance as predicted by (B5). ACKNOWLEDGMENT

An accurate description of the overshoot time requires a detailed modeling of the device behavior; for this reason we use the MOSFET Model 9 (MM9) [1], [2] to calculate the overshoot used in (21) and (26). time is a nonlinear problem. To avoid The solution of (1) to get numerical procedures we compute the time at which the overand relate to this value. shoot current is at maximum and for a 0.18Fig. 21 shows HSPICE simulations of and 0.35- m process technology obtained from a minimumsized inverter driving another minimum-sized inverter showing a linear relationship. The different simulations correspond to different input rise time values. This relationship can be expressed as (B1) since its analytical derivation is simWe will compute pler than the derivation of The maximum overshoot time is obtained from (1) neglecting the nMOS transistor the short-circuit current. Since at , (1) is reduced to is saturated and (B2) Using the long-channel approximation of the saturation voltage [2], [19] and neglecting the in the denominator of (9) as a first product term approximation, the drain saturation current of the nMOS is

(B3)

The authors wish to thank the anonymous reviewers for their constructive comments. REFERENCES [1] R. Velghe, D. Klaassen, and F. Klaassen, “MOS Model 9,” Philips Electronics, N.V., Unclassified Report NL-UR 003/94, 1994. [2] D. Foty, Mosfet Modeling With SPICE. Principles and Practice. Upper Saddle River, NJ: Prentice Hall, 1997. [3] J. L. Rosselló and J. Segura, “Power-delay modeling of dynamic CMOS gates for circuit optimization,” in Proc. Int. Conf. Computer-Aided Design. ICCAD 2001, San José, CA, Nov. 4–8, 2001, pp. 494–499. [4] H. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 468–473, Aug. 1984. [5] N. Hedenstierna and K. O. Jeppson, “CMOS circuit speed and buffer optimization,” IEEE Trans. Computer-Aided Design, vol. CAD-6, pp. 270–281, Mar. 1987. [6] T. Sakurai and R. Newton, “Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas,” IEEE J. SolidState Circuits, vol. 25, pp. 584–594, Apr. 1990. [7] A. P. Chandrakasan, S. Sheng, and R. W. Brodersen, “Low-power CMOS digital design,” IEEE J. Solid-State Circuits, vol. 27, pp. 473–484, Apr. 1992. [8] R. Rogenmoser and H. Kaeslin, “The impact of transistor sizing on power efficiency in submicron CMOS circuits,” IEEE J. Solid-State Circuits, vol. 32, pp. 1142–1145, July 1997. [9] R. X. Gu and M. I. Elmasry, “Power dissipation analysis and optimization of deep submicron CMOS digital circuits,” IEEE J. Solid-State Circuits, vol. 31, pp. 707–713, May 1996. [10] S. Turgis and D. Auvergne, “A novel macromodel for power estimation in CMOS structures,” IEEE Trans. Computer-Aided Design, vol. 17, pp. 1090–1098, Nov. 1998. [11] A. Hamoui and N. Rumin, “An analytical model for current, delay and power analysis of submicron CMOS logic circuits,” IEEE Trans. Circuits Syst.—II: Analog and Digital Signal Processing, vol. 47, pp. 999–1007, Oct. 2000. [12] T. Sakurai and R. Newton, “A simple MOSFET model for circuit analysis,” IEEE Trans. Electron. Devices, vol. 38, pp. 887–894, Apr. 1991. [13] S. Nikolaidis, A. Chatzigeorgiou, and Kyriakis-Bitzaros, “Delay and power estimation for a CMOS inverter driving RC interconnect loads,” in Proc. IEEE Int. Symp. Circuits Systems, vol. VI, Monterey, CA, May 1998, pp. 368–371. [14] K. Nose and T. Sakurai, “Analysis and future trend of short-circuit power,” IEEE Trans. Computer-Aided Design, vol. 19, pp. 1023–1030, Sept. 2000.

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[15] K. O. Jeppson, “Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay,” IEEE J. Solid-State Circuits, vol. 29, pp. 646–654, June 1994. [16] T. Sakurai and R. Newton, “Delay analysis of series-connected MOSFET circuits,” IEEE J. Solid-State Circuits, vol. 26, pp. 122–131, Feb. 1991. [17] U. Weidenmueller, E. O’hAnnaidh, S. Healey, and K. McCarthy, “Implementation of direct extraction methods for compact model parameters. Part I: The FORTRAN code,” Philips Research, Nat. Lab., Unclassified Report 010/97, 1997. [18] J. L. Rosselló and J. Segura, “A physical modeling of the alpha-power law MOSFET model,” in Proc. 15th Design Circuits and Integrated Systems Conf., Montpellier, France, Nov. 21–24, 2000, pp. 65–70. [19] Y. Tsividis, Operation and Modeling of the MOS Transistor, 2nd ed. New York: McGraw-Hill, 1999. [20] H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. New York: Addison-Wesley, 1990. [21] J. Qian, S. Pullela, and L. Pillage, “Modeling the effective capacitance for the RC interconnect of CMOS gates,” IEEE Trans. Computer-Aided Design, vol. 13, Dec. 1994. [22] J. L. Rosselló and J. Segura, “A simple power consumption model of CMOS buffers driving RC interconnect lines,” in Proc. XI Int. Workshop Power and Timing Modeling. Optimization and Simulation PATMOS 2001, Yverdon-Les-Bains, Switzerland, Sept. 26–28, 2000, paper 4.2.

José Luis Rosselló (M’02) received the M.S. and Ph.D. degrees in physics from the Balearic Islands University, Spain, in 1996 and 2002, respectively. He is a Teaching Assistant in the Physics Department, Balearic Islands University. His research interests include device and circuit modeling, CMOS IC testing, and low-power design.

Jaume Segura (M’94) received the M.S. and Ph.D. degrees from the Balearic Island University and the Polytechnic University of Catatonia in Spain, respectively. Since 1993, he has been an Associate Professor in the Physics Department, Balearic Islands University (UIB), Palma de Mallorca, Spain. He was on leave from UIB in 1994 and 2001 as an Invited Reasearcher at Philips Semiconductors, USA, and Intel Corporation, respectively. His research interests include device and circuit modeling and VLSI design and testing. Dr. Segura has served on the technical program committee of a number of conferences including the Design and Test in Europe (DATE), the International On-Line Testing Workshop (IOLTW), and the International workshop on current and Defect Based Testing (DBT). He is also member of the organizing committee of the VLSI Test Symposium (VTS) and served as General Co-Chair of the IOLTW in 2000.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 7, JULY 2004

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An Analytical Charge-Based Compact Delay Model for Submicrometer CMOS Inverters José Luis Rosselló and Jaume Segura

Abstract—We develop an accurate analytical expression for the propagation delay of submicrometer CMOS inverters that takes into account the short-circuit current, the input–output coupling capacitance, and the carrier velocity saturation effects, of increasing importance in submicrometer CMOS technologies. The model is based on the th-power-law MOSFET model and computes the delay from the charge delivered to the gate. Comparison with HSPICE level 50 simulations and other previously published models for a 0.18- m and a 0.35- m process technologies show significant improvements over previous models. Index Terms—Analytical model, circuit modeling, delay estimation, submicrometer MOSFETs.

I. INTRODUCTION

T

IMING analysis is one of the most critical topics in very large-scale integration (VLSI) design. The nonlinear behavior of CMOS gates requires numerical calculations for accurate timing analysis at the expenses of large computation times. Moreover, the impact of design parameters such as fan-in, fan-out, or transistor sizes on the propagation delay are difficult to understand and optimize using numerical procedures. The dynamic behavior of submicrometer CMOS inverters depends on several nonlinear effects like the velocity saturation of carriers due to the high electric fields in submicrometer technologies, the short-circuit current appearing when both pMOS and nMOS transistors conduct simultaneously [1], and the additional effect of the input–output coupling capacitance [2]. Several methods have been proposed to derive the delay of CMOS inverters [2]–[8] as a first step to describe more complex gates [9], [10]. Cocchini et al. [3] obtained a piecewise expression for the propagation delay based on the Berkeley short-channel IGFET model (BSIM) MOSFET model [11]. The model included overshooting effects (due to the input-to-output coupling capacitance) while the short-circuit current was neglected. Jeppson in [2], and Bisdounis et al. in [4], presented a model for the output response of CMOS inverters using a quadratic current-voltage dependence for MOSFET devices which is not longer valid for submicrometer technologies. Daga and Auvergne [5] obtained an empirical expression for

Manuscript received May 25, 2003; revised August 31, 2003. This work was supported in part by the Spanish Ministry of Science and Technology, in part by the Regional European Development Funds (FEDER) under EU Project TIC2002-01238, and in part by Intel Laboratories-CRL. This paper was recommended by Associate Editor A. I. Karsilayan. The authors are with the Physics Department, Balearic Islands University, 07071 Palma de Mallorca, Spain (e-mail: [email protected]; jaume.segura@ uib.es). Digital Object Identifier 10.1109/TCSI.2004.830692

the propagation delay taking into account both overshooting and short-circuit currents. Hirata et al. [6] derived a propagation delay model with numerical procedures based on the th-power-law MOSFET model [12] considering both short-circuit and overshooting currents. The model provides an accurate description of the propagation delay but the numerical procedures used in their analysis increase the computation time considerably. Bisdounis et al. [7] developed a piecewise solution with seven operation regions for the transient response of a CMOS inverter based on the -power-law MOSFET model [13] including both overshooting and short-circuit currents. Recently, Kabbani et al. obtained, in [8], a transition time model considering a quadratic relationship between the saturation current and the gate–source voltage (assumption only valid for micronic devices) without considering the effect of the input–output coupling capacitance. In [9], Sakurai and Newton obtained a simple expression for the propagation delay of CMOS gates based on their th-power-law MOSFET model neglecting both short-circuit and overshooting currents. In this paper, we propose an analytical model to accurately compute the propagation delay of a CMOS inverter accounting for the main effects of submicrometer technologies like the input–output coupling capacitance, carriers velocity saturation effects and short-circuit currents. The model is based on an accurate physically-based th-power-law MOSFET model [14] and on a previous power dissipation model for CMOS inverters [15]. The model can be applied to compute the propagation delay of CMOS inverters and represents a valuable approach for the evaluation of delay in complex gates as these can be collapsed to a single equivalent inverter for delay evaluation [10]. Comparisons with previously published models and HSPICE simulations using the Philips MOSFET Model 9 (MM9) for 0.18- m and 0.35- m process technologies show significant improvements in terms of accuracy. This paper is organized as follows. In Section II, we describe briefly the switching characteristics of CMOS inverters and introduce the MOSFET device model used in this work. In Section III, we derive an analytical charge-based expression for the switching response of a single pMOS/nMOS transistor charging/discharging a capacitor, that are generalized to CMOS inverters in Section IV by including overshooting and short-circuit effects. Section V presents an analytical model for the output transition time based on the delay model developed. The model proposed is compared to HSPICE simulations and other previously published models for a 0.35- m and a 0.18- m process technology in Section VI. Finally, in Section VII, we conclude the paper.

1057-7122/04$20.00 © 2004 IEEE

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dependence of the propagation delay with design parameters is nonlinear and difficult to model given that (1) cannot be solved in a closed form even using the simple Shockley MOSFET model [17]. Moreover, carrier saturation effects become important with technology scaling, thus requiring more complex MOSFET models accounting for such effects. The th-power-law MOSFET model [12] is a widely used short-channel drain-current model, and will be used in this work to derive the propagation delay and the output transition time of CMOS inverters. The drain current is given by Fig. 1. CMOS inverter model.

(3)

II. ANALYSIS OF CMOS INVERTER SWITCHING CHARACTERISTICS The dynamic behavior of the CMOS inverter in Fig. 1 is described by

with (4)

(1) where is the output capacitance that is composed by the drain capacitances of both nMOS and pMOS transistors, the output node wiring capacitance, and the input capacitance of and are the the gates connected to the inverter output. are the output and input voltages, respectively, while and is the input-topMOS and nMOS currents, respectively. output coupling capacitance, which is strongly voltage depenwhen the input is low ( ) is comdent. The static value of puted considering the overlap capacitances of both transistor drains and the gate-to-drain capacitance of the pMOS transistor that operates in the linear region [16] (2) with and being the effective channel width of is the effective channel pMOS and nMOS, respectively, length of pMOS, while and are the gate–drain underdiffusion for the nMOS and pMOS transistors, respectively. For is obtained similarly. a static input high, the capacitance Fig. 2 illustrates the input and output voltages evolution of the inverter along with the current through the nMOS and pMOS transistors for a low-to-high input transition. The current through the pMOS transistor ( in Fig. 2) has two components clearly distinguished by the sign of the current. The negative pMOS current is due to a partial discharge of the output capacitance from the output node toward the supply rail and appears when the input–output capacitance drives the ) at the beginning output voltage beyond the supply value ( of the transition [2]. This effect is known as overshooting and the time during which the output voltage is beyond the supply . When the nMOS value is defined as the overshoot time, device starts to conduct, it pulls the output voltage down. , the pMOS current is Once the output voltage goes below positive corresponding to the short-circuit component due to the simultaneous conduction of both devices. for a high-to-low The propagation delay (defined as output transition) is typically defined as the time interval from voltage input to the 50% voltage output. The the 50%

where , , and are the gate, supply, and saturation is the drain current at voltages, respectively, and . The parameter is the velocity saturation index that ranges between 2 (long-channel devices) and 1 (shortchannel) [12], and describes the channel length modulation. is given by The saturation voltage (5) is the saturation voltage at , The parameter and are empirical parameters [12]. These while equations are mathematically simpler than physically-based MOSFET models such as BSIM3v3 or MM9 with the disadvantage that, in the original model developed by Sakurai and Newton, the relationship between the empirical parameters and the process parameters supplied by manufacturers is not provided. Therefore, the variation of th-power-law model predictions with key parameters like the supply voltage are not taken into account in the original formulation performed by Sakurai and Newton, where each parameter must be recomputed if the supply voltage or any device dimension change. In this paper, we use the physical formulation for the th-power-law MOSFET model proposed in [14] and used in [15]. This physical formulation provides an analytical relationship between the th-power-law parameters and the foundry-provided MOSFET parameters. III. CHARGE-BASED PROPAGATION DELAY OF SINGLE nMOS DISCHARGING TRANSISTOR The analysis of discharging a capacitor through a nMOS transistor is developed in Appendix A (for a pMOS charging a capacitor the analysis is equivalent). Four cases are considered depending on the input voltage state (rising or static high) and the nMOS region of operation (ohmnic or saturation). In this section we use the output voltage expressions obtained in Appendix A to evaluate a charge-based expression for the propagation delay. We state initially some definitions that will be used extensively during the development of the model.

ROSSELLÓ AND SEGURA: ANALYTICAL CHARGE-BASED COMPACT DELAY MODEL

Fig. 2.

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Output voltage and current evolution in the nMOS and pMOS transistors for a rising input linear voltage.

In the context of this work, a fast-output transition refers to the cases were the nMOS transistor enters in its linear region while the input is changing. Otherwise (if the nMOS is saturated ), the output transition is considered to be slow. while We also define the discharging time up to a given voltage as the time interval from the beginning of the input transition until the instant at which the output is discharged at (an arbitrary voltage value between 0 and ). Finally, the propagation delay ( ) is defined as the time to (See Fig. 2). If interval from is defined as the input transition time, the propagation delay as is related to for (6) In this section, we first obtain an analytical expression of the discharging time for slow outputs, and then, we correct this expression to account also for fast outputs. The discharging time will be expressed in terms of the charge transferred through the and equal to ). nMOS transistor (defined as This charge is expressed in terms of four components (7) where and are the charges transferred while the input is rising and the nMOS is in saturation and linear region, respecand are defined similarly but when the input is tively. static high (i.e., ). The discharging time expression will be given in terms of these four charge components. A. Slow-Output Transitions For a slow-output transition, the nMOS transistor is saturated during the whole input transition and the output voltage evolution is given by (A6) (see Appendix A). Once the input is high, the output voltage is described by (A2) and (A4) since the nMOS

is initially saturated and enters the linear region at the end of the output transition. We express the time needed to discharge the until (discharging time) as a funcoutput from , , tion of the charge transferred during each region ( and ) using (A2), (A6), and (A4)

(8) where , and is the velocity saturation index of nMOS [in general, a subindex denotes a parameter for the nMOS(pMOS) ]. , , and , we define the saturation To obtain , and the linear charge as the total charge charge transferred when the nMOS transistor is in the saturation and in the linear region respectively. From these definitions, it follows that

(9) where is the maximum charge that can be transferred through the nMOS transistor operating in the saturation region, given by

where as

is the output capacitance. We obtain

from (10)

where is given by (9) and is the maximum charge that can be transferred through the saturated nMOS transistor during the input transition. The value of this maximum charge

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is obtained integrating the nMOS current during the rising input transition

is obtained by computing the discharging The value of time (14) at the end of the input transition (that is, when ). For this special case, we can set that

(11) Therefore, part of the saturation charge ( ) is transferred ), and the other part is transferred while the input is rising ( while the input voltage remains high (defined as ) (16) (12) After some algebra, (16) leads to Finally, for the slow-output ramp case we have that , since by definition, the input is high when the device enters the linear region. B. Inclusion of Fast-Output Transition Range Equation (8) is valid only if the nMOS transistor is saturated during the whole rising input period (for this case, the term is zero). For fast-output transitions, the case in which the nMOS enters in its linear region while the input is rising has no analytical solution (see Appendix A), and an approximation is required for an analytical description of the discharging time. The delay components of in (8) show mathematical analogies among the terms corresponding to the period during which the input is rising (the two first terms), and those corresponding to the input being static high (the two last). The time during which the nMOS is saturated and the input is high is given by ) while the time during the third term in (8), (that is, which the nMOS is saturated but the input is rising also contains ) but corrected with the same charge to current ratio ( an expression that depends on the transition time and the saturation velocity (13) When the output transition is fast, the linear charge is nonzero ), and must appear in the when the input is rising (i.e., in assuming delay expression of . We include the term that the charge component due to the static and dynamic input periods are of the same form

(17) In (17), we use because the input transition is ) and achieves its maximum value. The finished ( is obtained solving (17) value of (18) where

is given by (11). Finally,

is obtained from

(19) In Fig. 3, we plot HSPICE simulations of the output response of a single discharging nMOS transistor for a 0.35- m technology showing very good accuracy. Both slow- and fast-output transitions are simulated for various output capacitance values to , where is the input capacitance of (from a minimum sized inverter). From (14), the propagation delay is obtained applying (6). IV. PROPAGATION DELAY FOR CMOS INVERTER In this section, we consider a whole inverter (and not only a charging/discharging transistor) and include the effect of the short-circuit (due to the pMOS/nMOS transistor during the discharging/charging process) and overshooting currents ). Their (due to the input–output coupling capacitance contribution is included as additional charges to be transferred through the charging/discharging transistor. We develop only the discharging case as the charging case is equivalent. A. General Equation

(14) From (14), we must evaluate the parameters and . Similar to the previous analysis of the saturation charge, the ) linear charge transferred during the rising input transition ( that is the maximum is bounded by a maximum value charge that can be transferred through the nMOS transistor operating in the linear region while the input is rising (15)

The charge transferred from the output capacitances (both and in Fig. 1) through the nMOS transistor ( ) is computed from the difference between the charge initially stored at and the charge remaining in the output node this node when the output voltage reaches the desired value . , we have Assuming that (20) where and are the sum of the output capacitances when the input is low and high, respectively. and , while, when , we Initially,


Fig. 3. Falling transition for a W=L

assume that is charge

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=2-m/0.35-m nMOS transistor with different output loads (the input rise time is fixed to 200 ps).

. From (20), the maximum saturation

(21) For the evaluation of the propagation delay, we are interested in the charge transferred only from the output capacitances and through the nMOS transistor. Therefore, we use the same terms defined in the previous section for charges , , , and . It is important to remark that, by definition, these charges come from the capacitances connected to the output node and therefore do not include short-circuit con, the maximum value of saturation tribution. Therefore, charge during the rising input, is obtained from (11) by substracting the short-circuit charge transferred (SCCT) (22) where is the SCCT for a rising input transition. The expression of this component is taken from [15]. The charge transferred through the nMOS transistor comes from the output capacitances ( ) and the power supply through the pMOS transistor (SCCT). The propagation delay is computed considering both contributions by including an additional charge (a fraction of the SCCT) to the charge transferred from the output capacitances. Therefore, from (6) and (14), the propagation delay expression is given by

is a fraction of the SCCT ( ) and is defined as where . the SCCT during the time interval such that This short-circuit charge is added to the saturation charge for simplicity. The expression used for the evaluation of is , , computed in the Appendix B while parameters and are computed at . V. OUTPUT TRANSITION TIME COMPUTATION (

)

The effective output transition time can be related to a percentage of the derivative at the half point. Using from the 70% of this property, Sakurai et al. approximate derivative [9]. From SPICE simulations, we observed the that the output voltage shape is different depending on the relative switching speed between the input an the output voltages. For fast-output transitions (see Fig. 4), the output voltage evolution is close to the dc voltage characteristics of the inverter and (since the the output transition slope is strongly dependent of ). For slow-output nMOS conductance mainly depends on transitions (see Fig. 5), the output voltage slope is nearly conalmost from the stant since the nMOS gate voltage is at beginning of the output transition. Therefore, the percentage of derivative at that must be used to compute the depends on the relative switching speed of and , varying from 90% to 40% for a slow or fast-output transitions respectively. We use an empirical expression for the output transition that takes into account this effect time (24)

(23)

ratio provides the information of the relawhere the tive switching speed between the two nodes. This ratio is close to 0 or greater than 1 for fast and slow output transitions reand is given in Apspectively. The exact definition of used in (24) shows an expendix B. The expression for cellent agreement with respect to HSPICE simulations for both

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Fig. 4. and t


Comparison between HSPICE simulations of inverter output switching characteristics and model predictions for a fast-output transition (C

= 600 ps).

Fig. 5. Comparison between HSPICE simulations of inverter output switching characteristics and model predictions for a slow-output transition (C and t = 50 ps).

slow and fast-output transitions. In the analysis for the evaluaderivative at the short-circuit and overtion of the shooting currents are neglected for simplicity. is obtained from the discharging time The derivative as

=C

= 100C

depending on the transistor state at . For the special case in which the input is high, the discharging time derivative is

(25)

where . The derivative must be . At this time point, the transistor computed for can be in the linear or saturation region and the input can be rising or already at the high value. Therefore,

Note that when , we obtain the case in , see (14)], and which the nMOS is saturated [that is, the device is in the linear region when when and (25) leads to .


Fig. 6.

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Propagation delay versus input rise time for different values of the configuration ratio.

If the input voltage is rising when the output is at can be simplified to discharging time at

, the

(26) where

is given by

(27) Therefore,

is given by

(28) Since

is similar to (25), then

We use the following expression for (25) and (29) for each case:

(29) that leads to

(30) Note that the power term in (30) is equal to 1 when and (25) is recovered. Finally, the derivative at is of

(31) This expression is valid for both fast- and slow-output transitions.

VI. RESULTS We plotted model results versus HSPICE level 50 simulations for a 0.35- m and for a 0.18- m technology. Results show that the propagation delay versus the input transition time, the supply voltage, and the ratio. In Figs. 4 and 5, we show the output waveform of a CMOS inverter driven by a slow and a fast input transition, respectively (with parameters fF, 600 ps and 500 fF, 50 ps, respectively). Both figures show that the model developed for the propagation delay and the output time approximate the output response of the inverter with very good accuracy. In Fig. 6, we plot the propagation delay versus the input time for different values of the ratio for a 0.35- m technology. HSPICE simulations (dots) are compared to the model proposed and to a previous model [3]. Since the short-circuit current is not taken into account in the model in [3], the propagation delay is underestimated. The model in [3] proposes a piecewise solution of the propagation delay, i.e., depending on the input transition (fast or slow input transitions) it uses an approximated or an exact expression. The approximated propagation delay is used when the nMOS transistors change from the saturation to the linear region and the input is rising [3, eq. (11)]. Otherwise, an exact expression for the output response is used. This leads to a discontinuity in the propagation delay when changing between regions (see Fig. 6). Fig. 7 plots the propagation delay versus the input rise time for a 0.18- m technology. When the ratio is small the propagation delay decreases for increasing input rise times. The model in this work (solid lines) provides an excellent approximation to HSPICE simulations (dots) while previously published models [6], [7], that account for both overshooting and short-circuit currents, lead to underestimations.

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Fig. 7. Propagation delay versus input rise time for different values of the configuration ratio for a 0.18-m technology.

Fig. 8.

Propagation delay versus supply voltage for a 0.18-m technology.

Fig. 8 is a plot of HSPICE simulations (dots) and model predictions of the propagation delay versus the supply voltage. The model proposed in this paper provides a much better fit of the delay than the models in [6] and [7], especially for the low-voltage regime. The model in [7] shows discontinuities because it uses different expressions (Taylor series expansions) for the output response depending on the operation region of transistors. In Fig. 9, we show the propagation delay variation with temperature for three different supply voltage values. Different trends can be appreciated for each supply voltage value when increasing temperature. The propagation delay increases for 1.8 V, while for 0.9 V, the propagation delay decreases. This effect is described properly by the

proposed model since we are using the physically-based th-power-law MOSFET model developed in [14] that relates the th-power-law parameters to physical parameters (that are temperature-dependent) as the carrier mobility. For a more detailed description of this model, the reader is referred to [14], [15]. Fig. 10 plots the output switching response of a CMOS in, verter for different output loads ( and ) for a 0.18- m technology. It is shown that the model provides an excellent description of the gate delay, as the deviation of the output voltage with respect to the simulais very small. tions at Table I compares the model with HSPICE simulations of the propagation delay for a 60-CMOS inverters chain with


Fig. 9.

Fig. 10.

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Propagation delay versus temperature. Different delay trends versus temperature can be appreciated at different supply voltages.

Comparison between HSPICE simulations of inverter output switching characteristics and model predictions.

TABLE I DELAY VALUES OF 60-INVERTER CHAIN FOR 0.18-m TECHNOLOGY AT DIFFERENT SUPPLY VOLTAGES

10 m 5 m and m for different power supply values. A 1-GHz input signal drives the first inverter input. This experiment is used to check both the output transition time and the propagation delay model developed since the propagation delay of each stage is dependent on its of input rise time , that is, the output transition time the previous stage. The proposed model provides very good accuracy with respect to HSPICE. In Table II, we show the mean error of the model proposed and the models in [6] and [7] with respect to HSPICE simulations performed in Figs. 6–8. As can be appreciated, the model proposed provides a better accuracy than previously published models for scaled technologies. Table III compares the comcalculations of the propagaputation time used to perform tion delay of one single inverter with different analytical models and HSPICE simulations using a Pentium-III 500-MHz pro-

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TABLE II MEAN ERROR FOR PROPOSED MODEL AND PREVIOUSLY PUBLISHED MODELS FOR 0.35-m AND 0.18-m TECHNOLOGIES

subindex that

is referring to the nMOS value of ). Assuming , then, the solution of (A1) leads to (A2)

CASE 2: nMOS in the Linear Region and : This case is more complex since the nMOS current depends on the output voltage. Using the linear expression for the nMOS current (3), then (A3) We solve (A3) with the initial condition obtaining

TABLE III COMPUTATION TIME OF 10 TRANSITIONS WITH PENTIUM–III PROCESSOR@500 MHz

(A4) CASE 3: nMOS Saturated and the Input is Rising: We model a rising input transition as a linear function of the form (A5) cessor. As expected, analytical models are much more faster than HSPICE (about three orders of magnitude). The model in [6] leads to a greater computation time due to the use of numerical procedures. VII. CONCLUSION An accurate analytical expression to compute the propagation delay and the output transition time of CMOS inverters based on charge analysis has been presented. The main effects present in current submicrometer CMOS technologies like the input–output coupling capacitance, carriers velocity saturation effects and short-circuit currents are taken into account in a single analytical expression. The model is compared to HSPICE simulations (using the MM9 model) and to other previously published works for a 0.18- m and a 0.35- m process technology reporting a high degree of accuracy. It provides an analytical relationship of the delay to design parameters (device dimensions), input transition time, supply voltage, and temperature. The model is an accurate tool to compute the propagation delay and the input rise/fall time. It provides up to 15% and 100% of improvement in computing time with respect the models presented in [7] and [6], respectively, and a 1000 factor with respect to HSPICE simulations. APPENDIX A DERIVATION OF OUTPUT RESPONSE OF SINGLE nMOS DISCHARGING TRANSISTOR The differential equation to be solved is derived from (1) (A1) The output voltage evolution depends on the nMOS current expression and the initial condition at . Therefore, there depending on the input will be different solutions for voltage evolution and the operation region of the transistor (linear or saturation). We derive the analytical solution for each case. CASE 1: nMOS Saturated and : For this case, the nMOS current expression is fixed at (where the

where is the input rise time. At the beginning of the . When the transition, the nMOS is off and input voltage goes beyond the nMOS threshold voltage (i.e., ), the nMOS transistor starts to conduct in the saturation region. The initial condition is given . We solve (A1) using (4) and (A5) and by neglecting channel-length modulation as a first approach (A6) is the velocity saturation index of nMOS. where CASE 4: nMOS in the Linear Region and the Input is Rising: For this case, the differential equation (A1) has no analytical solution. APPENDIX B DERIVATION OF SHORT-CIRCUIT CHARGE TRANSFERRED AT The propagation delay, defined as the time interval between the time points at which the input and output voltages are at , depends on the SCCT during this interval. This charge (for a rising input transition, for a falling input is defined as transition we use the notation ) and is a fraction of the total SCCT during the transition. We obtain an empirical expression as a function of the total SCCT ( ) developed in [15]. of This empirical relationship is developed considering both fast and slow-output transitions. For slow-output transitions, the input is high before and can be considered to be equal to . For fastoutput transitions the short-circuit current is maximum when and the SCCT at this time point ( ) can be ). approximated to the half value of the total SCCT ( is dependent on the relative switching Therefore, since as speed of the input with respect to the output, we express a function of the ratio , where parameters and depends on the output and the input transition time and and . are defined as the input is considered slow and the SCCT If is taken as . If we consider that


the input is fast and the expression for the short-circuit charge is . The parameter is derived from at (14) (considering the nMOS transistor in saturation, neglecting for the short-circuit charge and assuming that simplicity)

(B1) Therefore, the relative switching speed

is (B2)

An empirical expression is used for as a function of . A linear relationship of with respect to the ratio is used for an output response with a value of lower than a threshold time . Otherwise, we take constant and equal to (B3) Parameter is taken such that is the time at which the pMOS transistor enters in the off state (that is, when , the short-circuit current ceases and we can consider that ). From this restriction, we find parameter to be (B4) and expressed The empirical relationship between in (B3) is found to be with a good agreement with HSPICE simulations over a wide variation of inverter configurations and transistor sizes. The total SCCT is obtained from the model in [15]

(B5) is the overshoot time (see Fig. 2), is the time where at which the short-circuit current is maximum, is the time is the maxduring which the short-circuit takes place and imum short-circuit current. The input–output coupling capacitance is taken into account in the exponential term while the maxthrough parameter takes into account both slowimum short-circuit current and fast-output transitions. The detailed description of all parameters involved are extensively explained in [15]. REFERENCES [1] H. Veendrick, “Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 468–473, Aug. 1984. [2] K. O. Jeppson, “Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance of the CMOS inverter delay,” IEEE J. Solid-State Circuits, vol. 29, pp. 646–654, June 1994.

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[3] P. Cocchini, G. Piccinini, and M. Zamboni, “A comprehensive submicrometer MOST delay model and its application to CMOS buffers,” IEEE J. Solid-State Circuits, vol. 32, pp. 1254–1262, Aug. 1997. [4] L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, “Propagation delay and short-circuit power dissipation modeling of the CMOS inverter,” IEEE Trans. Circuits Syst. I, vol. 45, pp. 259–270, Mar. 1998. [5] J. M. Daga and D. Auvergne, “A comprehensive delay macro modeling for submicrometer CMOS logics,” IEEE J. Solid-State Circuits, vol. 34, pp. 42–55, Jan. 1999. [6] A. Hirata, H. Onodera, and K. Tamaru, “Estimation of propagation delay considering short-circuit current for static CMOS gates,” IEEE Trans. Circuits Syst. I, vol. 45, pp. 1194–1198, Nov. 1998. [7] L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, “Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices,” IEEE J. Solid-State Circuits, vol. 33, pp. 302–306, Feb. 1998. [8] A. Kabbani, D. Alkhalili, and A. J. al-Khalili, “Technology portable analytical model for DSM CMOS inverter transition time estimation,” IEEE Trans. Computer-Aided Design, vol. 22, pp. 1177–1187, Sept. 2003. [9] T. Sakurai and R. Newton, “Delay analysis of series-connected MOSFET circuits,” IEEE J. Solid-State Circuits, vol. 26, pp. 122–131, Feb. 1991. [10] J. L. Rosselló and J. Segura, “Simple and accurate propagation delay model for submicron CMOS gates based on charge analysis,” Electron. Lett., vol. 38, no. 15, pp. 772–774, 2002. [11] D. Foty, MOSFET Modeling with SPICE. Principles and Practice. Englewood Cliffs, NJ: Prentice-Hall, 1997. [12] T. Sakurai and R. Newton, “A simple MOSFET model for circuit analysis,” IEEE Trans. Electron Devices, vol. 38, pp. 887–894, Apr. 1991. , “Alpha-power-law MOSFET model and its implications to CMOS [13] inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, pp. 584–594, Apr. 1990. [14] J. L. Rosselló and J. Segura, “A physically-based nth power-law MOSFET model for efficient CAD implementation,” in Proc. 18th Design of Circuits and Integrated Systems Conf. (DCIS’03), Ciudad Real, Spain, Nov. 19–21, 2003, pp. 380–383. [15] , “Charge-based analytical model for the evaluation of power consumption in submicron CMOS buffers,” IEEE Trans. Computer-Aided Design, vol. 21, pp. 433–448, Apr. 2002. [16] J. E. Meyer, “MOS models and circuit simulation,” RCA Rev., vol. 32, pp. 42–63, 1971. [17] W. Shockley, “A unipolar field effect transistor,” Proc IRE, vol. 40, pp. 1365–1376, Nov 1952.

José Luis Rosselló received the M.S. and Ph.D. degrees in physics from the University of the Balearic Islands, Palma de Mallorca, Spain, in 1996 and 2002, respectively. He is currently an Associate Professor at the same university. His research interests include device and circuit modeling, very large-scale integration design and test, and low-temperature CMOS design.

Jaume Segura received the M.S. and the Ph.D. degreed from the University of the Balearic Islands (UIB), Palma de Mallorca, Spain, in 1989 and 1992, respectively. He has been an Associate Professor at UIB since 1993. He was an Invited Researcher at Philips Semiconductors, Hilsboro, OR, in 1994, and Intel Corporation, Hilsboro, OR,, in 2001, on sabbatical from the UIB. His research interests include device and circuit modeling and very large-scale integration design and test. Prof. Segura is the Chairman of the IEEE Circuits and Systems Spanish Section.

Transient Current Testing Based on Current (Charge) Integration I. de Patil, R. Picas, J.L. Rossell6, M. R.oca, E. Isern, J. Segura and C. F. Hawkins* Physics Depa.rtment, Balearic Islands University, 07071 Palma de Ma,llorca,, SPAIN * EECE Dept., The U niversity of New Mexico and Sandia. Na.tional Labs., Albuquerque, NM 57131, ‘IISA

Abstract

We present experimental data from a. test, chip where several defects can be activated. The transient current was measured and t,he integrated value of the charge computed. ‘This work analyzed the sensitivity of the met.hod t.o defect location, circuit topology, and input stimuli. The next sect,ion describes the experimental met,hods. Section 3 discusses result,s, while Section 4 summarizes the work.

We evaluated a technique that uses power supply charge as the test observable. Charge was c o m p u t e d from the measured supply transient current waveform. Data shorn that this method is eficient to detect those defects that prevent current elevation (mainly “hard” opens) and therefore represents a valid extension of

IDDQ

1

2

Introduction

The experiments used an &bit shift, register in which several mask defects were designed. We evaluated the charge based test, technique to detect hard opens (i.e. those t#hat prevent current elevation). Transmission gates were connected to selected nodes of the circuit to emulate t,he presence of open defects, and were controlled with a 5 to 132 decoder t,o reduce circuit PIN count. Each decoder input, combination activated a unique open defect by turning off a given transmission gate. When a t,ransmission ga.te is off (i.e. it does not propa.gate signal), we say that its corresponding open defect is activated. The code 00000 does not activat,e any defect and was used t,o obt,a.in a reference measure from the fault. free circuit. Fig l(a) is a schematic of t.he 8 bit shift register with the t,ra.nsmission gates labeled for ea.ch defect,. Fig l(b) shows a detailed design of the single flip-flops composing the shift register. The circuit was designed with ES2 n-well dual metal 1.0 p m technology. Separate PADS were used for the B-bit. shift register core I,,>0 supply, the decoder and the input/output PADs. Measurements were taken at the 1’0~ circuit pin to avoid ground noise from input/output PADS and decoder switching. Current was measured by sensing the voltage drop at) a very-low inductive MP930 Caddok 300 R resistor with a Tektronix P6247 1 GHz bandwidth differential probe connected to a TDS640 ‘Tektronix scope with a 2 Gs/s sampling rate. A dedicat,ed board with differ-

Current testing (or IDDQ testing) is a widely used method to verify digital CMOS ICs. The main advantage of IDDQ is the high observability that allows a high defect coverage with a relatively small set of test, vectors. Opens can leave internal nodes at intermediate voltages, and cause quiescent current elevation that is easily detected with this technique. Despite this, IDDQ has limitations in detecting those defects that prevent current elevation (mainly certain opens). Several techniques are under development. to overcome these limitations and extend the use of current monitoring. Most of t#he t,echniques point toward dynamic current testing that monitors the power consumption not only during the quiescent periods, but also during the transients. Different transient techniques have been proposed. Beasley et al. [l] analyzed the idd signature when pulsing both VDD and GND levels from an intermediate value to their nominal values. Maki et al. [2] analyzed the change in the transient current peaks to detect defect,s in the circuit, while Plusquelic [3] and Vinnakota [4] considered both time and frequency domains while monitoring the signal. Cole et al. [5] measured the transient 2100 signature to detect defects. Our work used the power supply charge driven into the circuit during a single transition or a set of transitions as the observable for test. This parameter is directly related to the transient current. The principles of this technique were given in [6].

26 O-8186-9191-3/98 $10.00 0 1998 IEEE

Experimental Methods

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the output of one flip-flop (t,ransmission gates labeled as Oi). - Class-b. Opens preventing clock propagat,ion from the defect site t,o the end of t,he regist,er (transmission gates labeled as Ki).

Figure 1: &bit shift register used to measure the charge (a). The flap-flop d esign is reported

in

(b).

- Class-c. Opens preventing clock signal t,o a single latch wit,hout, affecting clock propagation to ot,her cells of the register (transmission gates labeled as Hi or 1i)

ent supply planes for core and PADS, and two ground planes connected with a low frequency bridge to avoid loop currents [7] was designed to minimize switching (high frequency) noise. Measurements were compared to HSPICE simulations from the extracted layout to evaluate the noise contribution. 50 waveform currents were measured and averaged for each test, vector. The charge was computed by numerical integration of the current waveform. The appropriate test vectors for each defect were generated following the procedure in [6]. Since this technique monitors the transient current, the test vectors were calculated to induce a given transition rather than setting a static input. For this reason we refer to State Transition Test Vectors (STTV) instead of static test vectors. STTVs were chosen to induce a current path in the fault free circuit that is missing in the defective one because of the defect. This depends on the defect site and its effect on the circuit. The mask generated defects shown in Fig l(a) can be put into three classes:

The charge difference bebween the faulty and t,he fault-free circuit can be maximized by shifting a STTV into the chain that: 1. Does not change the stat,e of the flip-flops located between the chain input and the defect site, and 2. Induces a state transition t,o all the flip-flops between the defect site and the output. This maximizes the charge difference between the fault, free and faulty circuit. Following this rule we derived one STTV for each defect (Fig. 2). The STTV derived for defect d (STTL’~) was used to measure the transient current at the rising and falling edge of t#he clock transition with data settled (Fig. 2).The STTV that complements all bits of each STTl/d (referred to as STTVd) was also used following rules 1 and 2 described before. We measured the transient current through the circuit power supply. A difference bet,ween idd(t) a.nd

27

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Figure 3: Transient current waveforms for circuit of Fig.1 measured at the rising and falling clock edges when no defect activated. b)

IDDQ is that, for a given vector, the current signature differs if it is measured at the power supply or at the ground rail, because of the charge contribution coming from the logic gate output capacitor loads. Additionally different charge values will be obtained when sensing the current at the rising or falling edge of the clock. This is shown in Fig. 3 where two waveform currents measured at the rising and falling edges of the clock for the same STTV are reported. 3

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Figure 4: Transient current waveforms measured for the same STTV at the good circuit and activating def e c t s Ii’2 to I& ( a ) , and their corresponding charge values with time (b).

Results and Discussion

Figure 4(a) shows eight current waveforms measured for STTVK (Fig 2) when Ka, . . , Ii’s are activated and for the fault free configuration. Current contributions are due to switching of the flip-flop clock inverters (Fig. 1.b) since STTVK does not, change any register data values. The largest current peak was obtained for the fault free configuration because all flipflops are driven by the clock. A smaller current, peak was obta.ined when defect 1^M P = Q e P >I ,= >RMSe , P R bo q 7 h > h K 9 r ] 9, fs 7 K , 7 ? G e'eb!tfqu vIw &1tfp u vIw 9 : It qu vIw >St p u vIw f I S7 K x L K h > h L Ss h

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W?|hL_U|L? Vkrfnoh|*v PRVIHW prgho ^4` lv wkh vlpsohvw irup wr h{suhvv wkh L0Y fkdudfwhulvwlfv ri d PRV0 IHW wudqvlvwru1 Krzhyhu/ wklv wudglwlrqdo vtxduh0 odz prgho ljqruhv wkh fduulhuv* yhorflw| vdwxudwlrq hhfwv zklfk ehfrphv surplqhqw lq dfwxdo vkruw0 fkdqqho ghylfhv1 Gxh wr lwv pdwkhpdwlfdo vlpsolf0 lw|/ wkh doskd0srzhu odz PRVIHW prgho ^5` lv d zlgho| xvhg gudlq fxuuhqw prgho wr dqdo|wlfdoo| gh0 ulyh jdwh sdudphwhuv olnh ghod|/ rxwsxw vohz wlph ru srzhu glvvlsdwlrq ^6`0^;`1 Wkh prgho wdnhv lqwr df0 frxqw wkh yhorflw| vdwxudwlrq hhfw/ zklfk ehfrphv grplqdqw lq vkruw0fkdqqho ghylfhv/ jlylqj dq h{fho0 ohqw lqwxlwlyh xqghuvwdqglqj ri wkh uhodwlrqvkls eh0 wzhhq wkh gudlq vdwxudwlrq fxuuhqw dqg wkh jdwh yrow0 djh1 Krzhyhu/ wkh hpslulfdo qdwxuh ri wkh sdudph0 whuv lqfoxghg lq wkh prgho +wkdw pxvw eh h{wudfwhg iurp phdvxuhphqwv ru VSLFH vlpxodwlrqv, fdqqrw surylgh d uhdo sk|vlfdo uhodwlrqvkls ehwzhhq prgho sdudphwhuv dqg fduulhuv* vdwxudwlrq hhfwv wkhuhiruh uhtxlulqj dgglwlrqdo frpsxwdwlrqdo hruw iru sdud0 phwhu h{wudfwlrq1 Uhfhqwo| d sk|vlfdo doskd0srzhu odz PRVIHW prgho kdv ehhq suhvhqwhg ^ LG4 , > +YJ5 > LG5 , dqg +YJ6 > LG6 , duh wkuhh srlqwv iurp wkh YJV LG sorw1 Rqfh YWK lv ghwhuplqhg/ lv rewdlqhg dv= orj +LG4 @LG5 , +7, orj ++YJ4 YW K , @ +YJ5 YW K ,, Wklv prgho lv hqwluho| hpslulfdo surylglqj d kdqg| irupxod wkdw fdq eh hdvlo| xvhg wr vroyh v|vwhpv ri pruh wkdq rqh wudqvlvwru olnh lqyhuwhuv ru frpsoh{ jdwhv dv uhsruwhg lq pdq| zrunv ^6`0^;`1 Htxdwlrq +6, surylghv kljkhu wkuhvkrog yrowdjh wkdq rwkhu sk|vlfdoo|0edvhg h{suhvvlrqv1 Dv dq h{0 dpsoh zh vkrz d frpsdulvrq ehwzhhq wkh wkuhvkrog yrowdjh jlyhq e| ht1 +6, dqg wkh wkuhvkrog yrowdjh h{suhvvlrq iurp wkh PRVIHW prgho < lq Ilj1 4 iru d 3168p whfkqrorj|1 H{suhvvlrq +6, ryhuhvwlpdwhv wkh wkuhvkrog yrowdjh zlwk d pd{lpxp huuru ri 47(1 D odfn ri sk|vlfdo phdqlqj +olnh wkh wkuhvkrog yrow0 djh uroo0xs suhvhqw, fdq eh fohduo| dssuhfldwhg lq Ilj1 41 Wkh sk|vlfdoo|0edvhg doskd0srzhu odz PRVIHW prgho ^ zlwk Fr{ ehlqj wkh jdwh r{lgh fdsdf0 lwru/ zkloh Zhii dqg Ohii duh wkh hhfwlyh fkdqqho zlgwk dqg ohqjwk uhvshfwlyho|1 hii lv wkh hhfwlyh fduulhuv prelolw| h{suhvvhg dv=

3

hii @

n-MOS Saturation current vs. gate voltage (L=0.35um,W=1..6um) 3.5 3

5

4. 4.

2 1.5 1

+;,

+4 . 4 Yjw , +4 . 6 Ygvdw , 4 dqg 6 duh wkh jdwh hog dqg gudlq eldv prelo0 lw| uhgxfwlrq frhflhqwv uhvshfwlyho|1 Ygvdw lv wkh vdwxudwlrq yrowdjh jlyhq e|=

Ygvdw @

Model Sak HSPICE

2.5

Isat (mA)

5 Lgv @ Yjw Ygvdw Ygvdw 5

Yjw

56 Yjw 4 5

+ 8 @ 3=41 NR dqg N duh wkh vxe0 vwudwh vhqvlwlylw| zkhq ghsohwlqj vxuidfh dqg exon grslqj uhvshfwlyho|/ S KLE lv wkh vxuidfh srwhqwldo iru vwurqj lqyhuvlrq dqg Y VE[ lv d yrowdjh ri wudq0 vlwlrq ehwzhhq NR dqg N 1Dv d ydoxh ri zh fkrrvh +Yjw @ +YGG YWK , @5, = Zh fdq hdvlo| rewdlq LG3 dqg YG3 iurp htxdwlrq +:, dqg + 3=9p> 3=;p> 4=3p> dqg 4=8p ri fkdqqho ohqjwk iru erwk s0PRV dqg q0PRV ghylfhv vkrz0 lqj d vlplodu dffxudf|1 Iljv1 : dqg ; vkrzv vxfk uhvxowv e| sorwwlqj KVSLFH suhglfwlrqv yv1 prghov

W deoh 4 Huuruv= 3=68p 3=8p 3=9p 3=;p 4=3p 4=8p 6=3p

Pd{1 614 614 519 519 518 517 514

Phdq1 51: 519 5 41< 41< 41; 41;

Pd{1^5` 518 41: 5 41< 41; 41; 41
wsKO @ O GG . W w +47, 5LG3 4. 5 W zkhuh wW lv wkh lqsxw ulvh2idoo wlph dqg yW @ YWK @YGG 1 Zh fdq revhuyh wkh glhuhqfh ri xvlqj lq +47, wkh wudglwlrqdo sdudphwhuv iru YWK dqg ru htxdwlrqv +44, dqg +46,1 Ilj1 < vkrzv wkh yduldwlrq ri wkh ghod| wlph ri d FPRV lqyhuwhu zlwk lqsxw ulvh dqg idoo wlph1 Dv fdq eh dssuhfldwhg/ erwk irupx0 odwlrqv ri wkh doskd0srzhu odz prgho ohdgv wr wkh

Sakurai's model fitness with HSPICE (p-MOS and n-MOS) L={0.35um..3um}

Model

3

Model

3

2.5

2.5

Ids(mA) (Model)

Ids(mA) (Traditional model)

Model fitness with HSPICE simulations (p-MOS and n-MOS) L={0.35um..3um}

2 1.5 1 0.5

2 1.5 1 0.5

0

0 0

Iljxuh : ~

0.5

1

1.5 2 Ids(mA) (HSPICE)

2.5

3

Frpsdulvrq ehwzhhq KVSLFH ohy1

0

83

0.5

1

1.5 2 Ids(mA) (HSPICE)

2.5

3

Iljxuh ; ~ Frpsdulvrq ehwzhhq KVSLFH ohy1

83 dqg

dqg vdnxudl*v suhglfwlrq iru wkh q0PRV dqg s0PRV

prgho suhglfwlrq iru wkh q0PRV dqg s0PRV fxuuhqwv

fxuuhqwv iru d vhw ri ghylfhv ehwzhhq

iru d vhw ri ghylfhv ehwzhhq

6=3p ri fkdqqho

3=68p

dqg

ohqjwk1

3=68p

dqg

6=3p

ri

fkdqqho ohqjwk1

vdph rughu ri dffxudf| +zlwklq d 6( ri phdq hu0 uru,1 Ilj1 43 vkrzv ghod| yduldwlrq zlwk fkdqqho ohqjwk iru d {hg q0PRV dqg s0PRV frqgxfwdqfh +Zq @Oq @ 3=8@3=68 dqg Zs @Os @ 4=3@3=68 ,1

^6` A 5@!h@ @?_ + i|L? #i*@) @?@*)tt Lu tihit

D L?U*tL?t

^7` @|3}iLh}Lc 5 !L*@_t @?_ W AtL!@*@t

D qhz irupxodwlrq ri wkh Doskd0srzhu odz PRV0 IHW prgho kdyh ehhq suhvhqwhg1 Prgho wdnhv lqwr dffrxqw sk|vlfdo sdudphwhuv wr ghvfuleh wkh fduul0 huv* vdwxudwlrq hhfwv lq d vlpsoh zd|1 Vlpsolflw| dqg dffxudf| ri wkh suholplqdu| prgho ghyhorshg e| Vdnxudl hw do1 kdyh ehhq pdlqwdlqhg1 Wkh prgh0 odwlrq fdq eh lqfoxghg lq pdq| kdqg| irupxodh gh0 yhorshg iurp wkh doskd0srzhu odz PRVIHW prgho ^6`0^;` zlwkrxw orrvh ri dffxudf| dqg doorzlqj d gl0 uhfw uhodwlrqvkls zlwk surfhvv sdudphwhuv1 U!?L*i_}4i?|t Wklv zrun kdv ehhq vxssruwhg e| wkh Vsdqlvk %Frplvlrq Lqwhuplqlvwhuldo gh Flhqfld | Whfqrorjld% xqghu wkh surmhfw FLF\W0WLF6 whfkqrorj| vkrzlqj vljqlfdqw lpsuryhphqwv1

4

Lqwurgxfwlrq

Dv LF whfkqrorj| ideulfdwlrq surfhvvhv vfdoh grzq/ qhz sk|vlfdo hhfwv pxvw eh frq0 vlghuhg zkhq dqdo|}lqj dqg prgholqj FPRV flufxlwv1 Yhorflw| vdwxudwlrq gxh wr kljk lqwhuqdo hohfwulf hogv/ lqsxw0rxwsxw frxsolqj fdsdflwru hhfwv gxh wr wkh qduurzhu jdwh r{lgh wklfnqhvv/ ru rq0fkls lqwhufrqqhfw uhvlvwdqfh +wkdw grhv qrw vfdoh grzq zlwk ihd0 wxuh vl}h, duh vrph ri wkh hhfwv wkdw pxvw eh frqvlghuhg wr rewdlq dffxudwh prghov1 D odujh iudfwlrq ri wkh srzhu glvvlsdwhg lq wrgd| YOVL LFv lv gxh wr wkh L2R gulyhuv dqg exvvhv dqg wkh forfn glvwulexwlrq qhwzrun/ zklfk duh edvhg rq lqyhuwhu jdwhv1 Khqfh/ wkh dqdo|wlfdo ghvfulswlrq ri srzhu glvvlsdwhg lq d FPRV lqyhuwhu lv ri lqfuhdvlqj lpsruwdqfh iru FPRV LFv srzhu hvwlpdwlrq1 Lw lv zhoo nqrzq wkdw srzhu glvvlsdwlrq lq FPRV flufxlwv kdv d g|qdplf dqg d vwdwlf frpsrqhqw1 Wkh g|qdplf glvvlsdwlrq +ghqhg dv wudqvlhqw hqhuj|, lv gxh wr wkh fkdujh2glvfkdujh ri wkh jdwh rxwsxw ordg/ dqg wr wkh vkruw0flufxlw fxuuhqw gxh wr wkh vxsso|0jurxqg frqgxfwlqj sdwk fuhdwhg gxulqj wkh wudqvlwlrq ^4`1 Vhyhudo zrunv kdyh ehhq irfxvvhg rq prgholqj wkh vkruw0flufxlw srzhu frqvxpswlrq ri FPRV exhuv1 Yhhqgulfn ^4` dqg Vdnxudl hw do1 ^5` rewdlqhg dqdo|wlfdo prghov iru xq0 ordghg exhuv xvlqj d orqj0fkdqqho dqg d vkruw0fkdqqho PRVIHW prgho uhvshfwlyho|1 Qrvh hw do1 ^6` ghulyhg d prgho iru vxeplfurq FPRV exhuv gulylqj d vlqjoh fdsdfl0 wru1 Wklv prgho grhv qrw wdnh lqwr dffrxqw erwk wkh lqsxw0rxwsxw frxsolqj fdsdflwru +LRFF, hhfwv qru wkh olqh uhvlvwdqfh dw wkh exhu rxwsxw1 Wxujlv hw do1 ^7` ghulyhg dq h{suhvvlrq iru wkh vkruw0flufxlw srzhu wdnlqj lqwr dffrxqw wkh LRFF dqg qhjohfwlqj wkh uhvlvwdqfh dw wkh exhu rxwsxw1 Qlnrodlglv hw1 do ^8`/ rewdlqhg dq h{suhvvlrq ri wkh vkruw0flufxlw glvvlsdwlrq iru exhuv gulylqj orqj lqwhufrqqhfw olqhv xvlqj wkh srzhu odz PRVIHW prgho1 Wkh dqdo|vlv zdv edvhg rq wkh 0prgho ri dq UF ordg dqg gh0 yhorshg iru vxe0plfurq ghylfhv1 Wklv prgho wdnhv lqwr dffrxqw wkh LRFF exw qhjohfwv wkh vkruw0flufxlw fxuuhqw frqwulexwlrq zkhq frpsxwlqj wkh rxwsxw zdyhirup1 Lq wklv zrun zh suhvhqw dq dffxudwh dqg vlpsoh prgho wr frpsxwh wkh srzhu frq0 vxpswlrq ri FPRV exhuv dffrxqwlqj iru wkh pdlq hhfwv lq vxeplfurq FPRV whfk0 qrorjlhv dv wkh LRFF dqg wkh olqh lqwhufrqqhfw uhvlvwdqfh/ ri lqfuhdvlqj lpsruwdqfh lq fxuuhqw vxeplfurq LFv1 Forvhg0irup h{suhvvlrqv iru srzhu hvwlpdwlrq duh rewdlqhg

5

Dxwkruv Vxssuhvvhg Gxh wr H{fhvvlyh Ohqjwk

dyrlglqj wlph0frqvxplqj qxphulfdo surfhgxuhv1 Wkh prgho lv frpsduhg wr KVSLFH vlpxodwlrqv +ohyho 83, dqg wr rwkhu suhylrxvo| sxeolvkhg prghov iru d 3=4;p dqg d 3=68p whfkqrorjlhv vkrzlqj d vljqlfdqw lpsuryhphqw lq whupv ri dffxudf|1 Wkh uhvw ri wklv zrun lv rujdql}hg dv iroorzv= lq vhfwlrq 5 zh rewdlq dq h{suhvvlrq iru wkh wudqvlhqw hqhuj|1 Vhfwlrq 6 ghulyhv wkh vkruw0flufxlw hqhuj| frpsrqhqw dqg Vhfwlrq 7 suhvhqwv wkh uhvxowv zkloh Vhfwlrq 8 frqfoxghv wkh zrun1

5

Wudqvlhqw glvvlsdwlrq

Wkh wudqvlhqw hqhuj| +Hwu , lv ghqhg dv wkh hqhuj| glvvlsdwhg zkhq wkh rxwsxw fdsdflwru lv fkdujhg2glvfkdujhg1 Lq d FPRV exhu wkh fkdujh dw wkh rxwsxw qrgh +Trxw , lv vwruhg lq erwk wkh rxwsxw dqg wkh frxsolqj fdsdflwru dqg fdq eh h{suhvvhg dv= Trxw +Ylq > Yrxw , @ +FP . FO , Yrxw FP Ylq

+4,

zkhuh Yrxw lv wkh rxwsxw yrowdjh/ Ylq wkh lqsxw yrowdjh/ FP lv wkh LRFF/ dqg FO lv wkh wrwdo fdsdflwdqfh dw wkh exhu rxwsxw1 O , lv Wkh ydoxh ri FP zkhq wkh lqsxw lv lq wkh vwdwlf orz vwdwh +ghqhg dv FP frpsxwhg frqvlghulqj wkh vlgh0zdoo fdsdflwdqfh ri erwk wudqvlvwru gudlqv/ wkh jdwh wr gudlq fdsdflwdqfh ri wkh sPRV wudqvlvwru lq wkh olqhdu uhjlrq/ dqg lv jlyhq e|= Zshii Oshii O +5, @ Fr{ FP . ODSs Zshii . ODSq Zqhii 5 zlwk ODSs dqg ODSq ehlqj wkh jdwh gudlq xqghuglxvlrq iru wkh sPRV dqg qPRV wudqvlvwruv uhvshfwlyho|/ Zqhii dqg Zshii wkh qPRV dqg sPRV hhfwlyh fkdqqho zlgwk/ Oshii wkh hhfwlyh fkdqqho ohqjwk ri wkh sPRV wudqvlvwru/ dqg Fr{ wkh jdwh r{lgh K fdsdflwdqfh1 Iru d vwdwlf lqsxw kljk wkh fdsdflwdqfh FP fdq eh rewdlqhg vlploduo|1 Wkh hqhuj| glvvlsdwhg dw wkh qPRV wudqvlvwru iru d kljk wr orz rxwsxw wudqvlwlrq lv jlyhq e| Hwu @ TYGG @5/ zkhuh T lv wkh fkdujh wudqvihuuhg iurp wkh rxwsxw qrgh wr jurxqg wkurxjk wkh qPRV wudqvlvwru/ dqg YGG lv wkh yrowdjh vzlqj1 Wkxv/ wudqvlhqw hqhuj| lv h{suhvvhg dv= Hwu @ ^Trxw +Ylq @ 3> Yrxw @ YGG , Trxw +Ylq @ YGG > Yrxw @ 3,`

YGG 5

+6,

zkhuh Trxw +3> YGG , lv wkh fkdujh vwruhg dw wkh rxwsxw qrgh dw wkh ehjlqqlqj ri wkh wudqvlwlrq dqg Trxw +YGG > 3, lv wkh fkdujh vwruhg dw wkh rxwsxw qrgh zkhq wkh wudqvlwlrq lv qlvkhg1 Xvlqj ht1+4, zh rewdlq= 5 4 O K +7, YGG FO . FP . FP 5 Wkh vdph h{suhvvlrq lv rewdlqhg zkhq d orz wr kljk rxwsxw wudqvlwlrq lv frqvlghuhg1 Hwu @

6

Vkruw0flufxlw srzhu prgho

Zh frpsxwh wkh vkruw0flufxlw hqhuj| glvvlsdwhg lq d FPRV exhu +Ilj1 4, iru d orz wr kljk lqsxw wudqvlwlrq +iru d kljk wr orz lqsxw wudqvlwlrq wkh prgho lv htxlydohqw,1 Lq rxu dqdo|vlv zh lqlwldoo| qhjohfw wkh uhvlvwdqfh ri wkh lqwhufrqqhfw olqh U dqg wkh lqsxw0rxwsxw frxsolqj fdsdflwru FP / wkdw zloo eh lqfoxghg odwhu1

D vlpsoh srzhu frqvxpswlrq prgho ri FPRV exhuv gulylqj UF lqwhufrqqhfw olqhv

6

Ilj1 41 FPRV exhu prgho

Wkh vkruw0flufxlw frpsrqhqw lv rewdlqhg e| frpelqlqj wkh vroxwlrq rewdlqhg iru wkh olplw ri d idvw lqsxw wudqvlwlrq +ru d odujh rxwsxw fdsdflwru, dqg wkh rqh rewdlqhg iru wkh olplw ri d vorz lqsxw wudqvlwlrq +ru d vpdoo rxwsxw fdsdflwru,1 Ilqdoo| zh lqfoxgh wkh hhfwv ri wkh lqsxw0rxwsxw fdsdflwru dqg wkh uhvlvwdqfh ri wkh lqwhufrqqhfw1 614

Vkruw0flufxlw prgho iru khdylo|0ordghg exhuv

Wkh g|qdplf ehkdylru ri wkh flufxlw lq Ilj1 4 lv ghvfulehg e|= gYrxw gYlq +8, @ Ls Lq . FP gw gw zkhuh Ls dqg Lq duh wkh sPRV dqg qPRV fxuuhqwv uhvshfwlyho|1 Xvlqj d vlpsoh vkruw0fkdqqho PRVIHW prgho iurp ^9`/ dqg qhjohfwlqj fkdqqho0 ohqjwk prgxodwlrq hhfwv/ wkh gudlq fxuuhqw h{suhvvlrq lv jlyhq e|= +FO . FP ,

LGV

; +YJV _ YW K , ?3 Y 3 3 , YYGV LG3 +YGV ? YG3 , 3 3 @ +5 YGV G3 G3 = 3 3 +YGV YG3 , LG3

+9,

zlwk= 3

LG3 @ LG3

YJV YW K YGG YW K

q +:,

3 Wkh vdwxudwlrq yrowdjh YG3 lv jlyhq e| ^9`= 3 YG3 @ YG3

YJV YW K YGG YW K

p +;,

Wkh sdudphwhu q lv wkh yhorflw| vdwxudwlrq lqgh{ wkdw wdnhv d ydoxh ehwzhhq 5 +orqj0 fkdqqho ghylfhv, dqg 4 +vkruw0fkdqqho,1 Sdudphwhuv LG3 dqg YG3 duh wkh gudlq fxuuhqw dqg vdwxudwlrq yrowdjh iru YJV @ YGV @ YGG / zkloh sdudphwhuv q/ p dqg YW K duh wwlqj sdudphwhuv1 Wkh lqsxw yrowdjh lv ghvfulehg zlwk d olqhdu udps dv= Ylq +w, @ YW Q . YVF

w wq wvf

+ wvf @ YYGG YGG wkh qPRV dqg sPRV wkuhvkrog yrowdjhv/ dqg wlq lv wkh lqsxw ulvh wlph1 Dw wkh ehjlqqlqj ri wkh wudqvlwlrq/ wkh qPRV wudqvlvwru lv vdwxudwhg1 Iru khdylo|0 ordghg exhuv wkh vkruw0flufxlw dqg ryhuvkrrwlqj hhfwv fdq eh qhjohfwhg dqg ht1+8, fdq eh vlpsolhg wr= gYrxw 3 +43, @ LG3 q gw 3 O O zlwk LG3q jlyhq e| ht1 +:, dqg FV @ FO . FP 1 Zh fdq vroyh ht1 +43, zlwk wkh lqlwldo frqglwlrq Yrxw +wq , @ YGG rewdlqlqj= FVO

q .4 w wq q +44, Yrxw +w, @ YGG YG wvf zkhuh wq lv wkh wlph dw zklfk wkh qPRV wudqvlvwru vwduwv wr frqgxfw dqg YG lv jlyhq e|= qq YVF LG3q wvf +45, YG @ O FV +qq . 4, YGG YW Q Ht1 +44, lv xvhg lq wkh olqhdu h{suhvvlrq ri wkh sPRV fxuuhqw +vhh ht1 +9,,1 Iru wkh sPRV wudqvlvwru zh h{suhvv wkh gudlq/ jdwh dqg vdwxudwlrq yrowdjhv dv= YGV @ YG

w wq wvf

qq .4

+46,

w wq YJV @ mYW S m . YVF 4 w vf q YG3s YVF 4 ww wvf 3 YG3s @ +YGG mYW S m, zkhuh d ydoxh ri p @ 4 lv frqvlghuhg dw wkh vdwxudwlrq yrowdjh h{suhvvlrq1 Vlqfh zh duh qrz frqvlghulqj khdylo|0ordghg exhuv/ wkhq wkh gudlq0vrxufh yrowdjh dw wkh sPRV wudqvlvwru lv vpdoo ehfdxvh wkh rxwsxw fdsdflwru lv odujh1 Wkxv/ zh wdnh rqo| d uvw rughu h{suhvvlrq iru wklv fxuuhqw lq whupv ri YGV iurp ht1+9,1

zkhuh L3s

YG Ls @ 5 L3s YG3s kdv wkh irup=

w wq wvf

qq .4

w wq 4 wvf

qs 4

+47,

qs 4 YVF +48, L3s @ LG3s YGG mYW S m Wkh wlph dw zklfk wkh pd{lpxp fxuuhqw wdnhv sodfh iru khdylo| ordghg exhuv O $4 lv rewdlqhg vroylqj Cw Ls @ 31 wF pd{ qq . 4 qq . qs Wkhq/ wkh pd{lpxp fxuuhqw iru khdylo|0ordghg exhuv lv h{suhvvhg dv=

O $4 @ wq . w wF vf pd{

FO $4 Lpd{ s

YG @5 L3s YG3s

qq . 4 qq . qs

qq .4

qs 4 qq . qs

qs 4

+49,

+4:,


615

8

Vkruw0flufxlw prgho iru xqordghg exhuv

Zkhq wkh rxwsxw fdsdflwdqfh lv vpdoo +l1h1 zkhq wkh vkruw0flufxlw fxuuhqw kdv wkh juhdwhu lpsdfw ^4`, wkh flufxlw ehkdylru lv forvh wr wkh lqyhuwhu GF rshudwlrq vlqfh Ls * Lq 1 Dw wkh ehjlqqlqj ri wkh wudqvlwlrq/ wkh sPRV wudqvlvwru gulyhv d fxuuhqw htxdo wr wkh qPRV vdwxudwlrq fxuuhqw/ zkloh dw wkh hqg ri wkh wudqvlwlrq wkh sPRV lv vdwxudwhg1 Lq 3 3 wklv sduwlfxodu fdvh/ wkh pd{lpxp fxuuhqw wdnhv sodfh zkhq LG3 s @ LG3q 1 Jlyhq wkdw Y iru wkh qPRV dqg Y iru wkh sPRV/ wkh wlph dw zklfk wkh YJV @ Ylq JV @ YGG lq vkruw0flufxlw lv pd{lpxp +ghqhg dv wFO@3 , fdq eh rewdlqhg vroylqj= pd{ 3

4qq 3 4qs wFO@3 wFO pd{@3 mYW S m Y Y YGG pd{ Y W Q GG GG wlq wlq D @ LG3 C D LG3q C s YGG YW Q YGG mYW S m

+4;,

zkhuh LG3q dqg LG3s duh wkh sdudphwhuv LG3 ri wkh qPRV dqg wkh sPRV wudqvlvwru uhvshfwlyho|1 Zh rewdlqhg d jrrg dqdo|wlfdo dssur{lpdwlrq wr wkh vroxwlrq ri ht1 +4;, dv=

O @3 wF pd{

WQ mYWS m 4 YYGG YGG @ wq . wlq 5 q .q 4.I s q

+4 dqg wr Lpd{s iru FO @ 31 Lpd{ irup D@FVO dqg wkhuhiruh glyhujhqw zkhq FO @ 31 Wr suhyhqw vxfk d glyhujhqfh zh xvh wkh iroorzlqj h{suhvvlrq iru wkh pd{lpxp vkruw0flufxlw fxuuhqw1 Lpd{s @

FO $4 FO @3 Lpd{ s Lpd{s FO $4 FO @3 Lpd{s . Lpd{ s

+54,

Wkh vkruw0flufxlw fxuuhqw lv lqlwldwhg zkhq wkh qPRV wudqvlvwruvwduwv wr frqgxfw WQ , dqg fhdvhv zkhq wkh sPRV lv r +dw wlph ws @ wlq 4 mYWS m ,1 Wkh +dw wq @ wlq YYGG YGG vkruw0flufxlw fkdujh wudqvihuuhg +VFFW, lv rewdlqhg dssur{lpdwlqj wkh vkruw0flufxlw fxuuhqw vkdsh dv d wuldqjoh zlwk pd{lpxp ydoxh Lpd{s +wuldqjoh DEF lq Ilj1 5,1 Wkhq/ wkh duhd xqghu wkh wuldqjoh zloo eh sursruwlrqdo wr wkh VFFW= T3vf @

mYW S m YW Q Lpd{s wlq 4 5 YGG YGG

+55,

9


zkhuh lv d wwlqj sdudphwhu dffrxqwlqj iru wkh ghyldwlrq ri wkh vkruw0flufxlw fxuuhqw vkdsh iurp dq lghdo wuldqjoh1 Wkh sdudphwhu lv forvh wr 4 iru ghhs0vxeplfurq whfk0 qrorjlhv gxh wkh olqhdu ghshqghqfh ehwzhhq wkh vdwxudwlrq fxuuhqw dqg wkh jdwh yrowdjh +wkdw ghvfulehv dq lghdo wuldqjoh,1 Iru orqj0fkdqqho ghylfhv @ 5@6 vlqfh wkh ghshq0 ghqfh ehwzhhq wkh vdwxudwlrq fxuuhqw dqg wkh jdwh yrowdjh lv txdgudwlf +wkh duhd ri d wuldqjoh frpsrvhg e| wzr sduderodv lv 46 Lpd{s +ws wq ,,1 Wkhuhiruh/ wkh sdudphwhu wdnhv d ydoxh ehwzhhq 5@6 +orqj0fkdqqho, dqg 4 +ghhs0vxeplfurq,1 Wkh sdudphwhu lv wdnhq htxdo iru erwk idoolqj dqg ulvlqj lqsxw wudqvlwlrqv iru vlpsolflw|1 Iru wkh wzr whfkqrorjlhv xvhg lq wklv zrun zh rewdlqhg @ 3=9< dqg @ 3=:8 iru wkh 3=68p dqg wkh 3=4;p whfkqrorjlhv uhvshfwlyho|1 617

Ryhuvkrrwlqj hhfwv

Geometry extraction of Qsc from Qsc(CM=0) and tov B

50 40

E Q sc 0

Current ( µ A)

30 20

Q sc r

10 D

0

t ov

A

C

-10 -20 0

20

40

60

80

100

t (ps)

Ilj1 51 Jhrphwulfdo ghulydwlrq ri 'orS iurp 'frS dqg |J

Hhfwv ri ryhuvkrrwlqj rq wkh vkruw0flufxlw fxuuhqw Ilj1 5 lv d sorw ri wkh fxuuhqw wkurxjk wkh vkruw0flufxlwlqj wudqvlvwru gxulqj wkh wudqvlwlrq1 Wzr fdvhv duh frqvlghuhg/ FP @ 3 dqg FP 9@ 31 Vlpxodwlrqv lq Ilj1 5 vkrzhg wkdw ryhuvkrrwlqj glvsodfhv wkh vkruw0flufxlw fxuuhqw wr wkh uljkw/ pdlqwdlqlqj wkh fxuuhqw vorshv lqyduldqw1 Wklv fdq eh ghvfulehg dqdo|wlfdoo| xvlqj d jhrphwulfdo dssurdfk dv vkrzq lq Ilj 51 Zh dssur{lpdwh wkh vkruw0flufxlw fxuuhqw fxuyh glvsodfhphqw zlwk vwudljkw olqhv ri htxdo vorshv/ zlwk wkh glvsodfhphqw gxh wr ryhuvkrrwlqj1 T3vf lv wkh duhd ri wkh wuldqjoh DEF +VFFW zkhq FP @ 3, dqg lv nqrzq iurp ht1 +55,/ zkloh wkh uhgxfhg VFFW gxh wr ryhuvkrrwlqj +Tuvf , lv wkh duhd xqghu wkh wuldqjoh GHF1 Xvlqj wklv jhrphwulfdo dqdorj| Tuvf lv ghulyhg iurp T3vf xvlqj wry dv= Tuvf

@

T3vf

5 wry wq 4 wvf

+56,

Li wry A wq . wvf / ht1+56, qr orqjhu krogv dqg Tuvf @ 3= Ryhuvkrrw wlph hydoxdwlrq Wkh vroxwlrq ri ht1+8, wr jhw wry lv d qrq0olqhdu sureohp zlwk qr0forvhg irup h{suhvvlrq1 Wkhuhiruh/ zh uhodwh wklv sdudphwhu wr wkh wlph dw


:

450 0.18um Design Rule 0.35um Design Rule Eq. (24)

400 350

t ov (ps)

300 250 200 150 100 50 0 0

50

100

150 tov max (ps)

200

250

300

iru d fH>6 dqg d f D>6 surfhvv whfkqrorj|1 D Ilj1 61 KVSLFH vlpxodwlrqv ri |J dqg |4@ J plqlpxp vl}hg lqyhuwhu gulylqj dqrwkhu plqlpxp vl}hg lqyhuwhu duh frqvlghuhg zlwk glhuhqw lqsxw ulvh wlphv

zklfk wkh ryhuvkrrwlqj fxuuhqw lv pd{lpxp +ghqhg dv wpd{ ry ,/ wr jhw dq dqdo|wlfdo h{suhvvlrq iru wry = Ilj1 6 vkrzv KVSLFH vlpxodwlrqv ri wry dqg wpd{ ry iru d 3=4;p dqg d 3=68p surfhvv whfkqrorj| iru d plqlpxp vl}hg lqyhuwhu wkdw gulyhv dqrwkhu plqlpxp vl}hg lqyhuwhu1 Wkh glhuhqw vlpxodwlrqv duh rewdlqhg ydu|lqj wkh lqsxw ulvh wlph1 D olqhdu uhodwlrqvkls lv rewdlqhg zlwk wkh irup= wry wq @

6 +wpd{ ry wq , 5

+57,

Wkh pd{lpxp ryhuvkrrw wlph lv rewdlqhg iurp ht1+8, qhjohfwlqj wkh fxuuhqw wkurxjk wkh qPRV wudqvlvwru lv vdwxudwhg dqg wkh rxwsxw yrowdjh lv wkh sPRV1 Dw w @ wpd{ ry pd{lpxp + gYgwrxw @ 3,1 Wkhq ht1 +8, lv uhgxfhg wr= FP

gYlq 3 LG3 q @3 gw

+58,

Ht1+58, fdq eh h{suhvvhg dv= YGG LG3q FP wlq

#

$qq wpd{ YGG wrylq YW Q @3 YGG YW Q

+59,

Vroxwlrq wr ht1 +59, ohdgv wr= wpd{ ry

wlq @ YGG

#

YW Q . +YGG YW Q ,

FP YGG LG3q wlq

q4 $ q

+5:,

Rqfh wpd{ lv rewdlqhg/ wry lv jlyhq e| ht1+57,1 ry Ilqdoo|/ wkh hqhuj| dvvrfldwhg wr wkh vkruw0flufxlw fxuuhqw iru d ulvlqj lqsxw wudqvlwlrq lv frpsxwhg dv= u Hvf @ Tuvf YGG

+5;,

;


Ilj1 71 Lqwhufrqqhfwlrq vfkhph1 D Z prgho lv xvhg wr vlpxodwh wkh lqwhufrqqhfwlrq olqh1

618

Lqfoxglqj wkh uhvlvwlylw| ri wkh lqwhufrqqhfw olqh

Zh lqfoxgh wkh hhfw ri wkh lqwhufrqqhfw olqh e| xvlqj wkh hhfwlyh fdsdflwdqfh frqfhsw ^:`1 Wr rewdlq dq dqdo|wlfdo h{suhvvlrq ri wkh hhfwlyh fdsdflwdqfh wr eh xvhg lq wkh vkruw0flufxlw prgho zh dqdo|}h wkh UF qhwzrun ri Ilj1 71 Wkh qrgh yrowdjh Y4 dqg Y5 duh uhodwhg e| d v|vwhp ri glhuhqwldo htxdwlrqv1 Y Y gY4 4 5 4 LG3 q gw @ F4 U +56 whfkqrorj|1

7

Uhvxowv

Lq Ilj1 8 zh sorw KVSLFH vlpxodwlrqv ri wkh vkruw0flufxlw hqhuj| glvvlsdwhg shu rqh f|0 foh shulrg yv1 olqh uhvlvwdqfh iru d 3=4;p whfkqrorj|1 Wkh lqwhufrqqhfw olqh lv vlpxodwhg zlwk KVSLFH xvlqj wkh 6 prgho1 Wkuhh glhuhqw lqyhuwhuv zlwk glhuhqw ydoxhv ri wkh Zs @Zq udwlr duh frqvlghuhg1 Wrwdo fdsdflwru dw wkh rxwsxw lv {hg dw FO @ 3=5sI= Dv fdq eh dssuhfldwhg wkh vkruw0flufxlw srzhu lqfuhdvhv zkhq lqfuhdvlqj wkh olqh uhvlv0 wdqfh1 Wklv lv ehfdxvh sduw ri wkh rxwsxw fdsdflwdqfh lv vklhoghg iurp wkh exhu/ wkxv ghfuhdvlqj wkh jdwh ghod| dqg lqfuhdvlqj wkh vkruw0flufxlw glvvlsdwlrq ^:`1 Zh frpsduh KVSLFH vlpxodwlrqv +grwv, zlwk prgho lq ^8` dqg wkh prgho sursrvhg1 Wkh prgho lq ^8` xqghuhvwlpdwhv hqhuj| zkloh wkh prgho sursrvhg suhvhqwv dq ryhudoo jrrg dffxudf|1 Lq Ilj1 9 zh vkrz KVSLFH vlpxodwlrqv ri wkh hqhuj| glvvlsdwhg shu rqh f|foh shulrg yv1 wkh lqsxw wlph iru d 3=68p whfkqrorj|1 Wzr glhuhqw lqyhuwhuv duh frqvlghuhg zlwk glhuhqw ydoxhv ri wkh Zs @Zq udwlr dqg wzr ydoxhv ri wkh lqwhufrqqhfw uhvlvwdqfh +U @ 3 dqg U @ 4n ,1 Wkh wrwdo fdsdflwru dw wkh exhu rxwsxw lv {hg dw FO @ 4sI 1

43


Dv fdq eh dssuhfldwhg/ wkh prgho ghyhorshg ghvfulehv fruuhfwo| KVSLFH vlpxodwlrqv iru doo wkh frqglwlrqv frqvlghuhg1 Ilqdoo|/ lq Wdeoh 4 zh vkrz wkh wrwdo dqg wkh phdq huuru ri wkh vkruw0flufxlw hqhuj| glvvlsdwhg iru wkh prghov lq ^6/ 8` dqg wkh prgho sursrvhg uhvshfw KVSLFH vlpxodwlrqv lq Iljv1 8 dqg 91 Dv fdq eh dssuhfldwhg/ wkh prgho sursrvhg uhsuhvhqwv dq lpsuryhphqw lq whupv ri dffxudf|1 Wdeoh 41 Phdq dqg pd{lpxp huuruv ri wkh vkruw0flufxlw hqhuj| glvvlsdwhg iru d 3=4;p dqg d 3=68p whfkqrorj| Huuru Pd{1+3=4;p, Phdq+3=4;p, Pd{1+3=68p, Phdq+3=68p, 6( 63( ;( Prgho 8( 99( 8:(

A Variable Threshold Voltage Inverter For Cmos Programmable Logic ...

A Variable Threshold Voltage Inverter For Cmos Programmable Logic ...

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